1 pixel h. wieman hft cdo lbnl 25-26-feb-2008. 2 topics pixel specifications and parameters pixel...
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PIXEL
H. WiemanHFT CDOLBNL25-26-Feb-2008
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topics
Pixel specifications and parameters Pixel silicon Pixel Readout
STAR telescope tests Mechanical organization
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Pixel geometry
2.5 cm radius
8 cm radius
Inner layer
Outer layer
End view
One of two half cylinders
20 cm
coverage +-1
total 40 ladders
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Some pixel features and specifications
Pointing resolution (13 19GeV/pc) m
Layers Layer 1 at 2.5 cm radiusLayer 2 at 8 cm radius
Pixel size 30 m X 30 m
Hit resolution 10 m rms
Position stability 6 m (20 m envelope)
Radiation thickness per layer
X/X0 = 0.28%
Number of pixels 164 M
Integration time (affects pileup) 0.2 ms
Radiation tolerance 300 kRad
Rapid installation and replacement to cover rad damage and other detector failure
Installation and reproducible positioning in a shift
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Silicon program
pixel chips (MAPS) produced by
IReS/LEPSI IPHC (Strasbourg)
M. Winter
C. HuC. ColledaniW. DulinskiA. HimmiA. ShabetaiM. SzelezniakI. Valin
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MAPS
Properties:
Signal created in low-doped epitaxial layer (typically ~10-15 μm)
Sensor and signal processing integrated in the same silicon wafer
Standard commercial CMOS technology
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IPHC Functional Sensor Development
Data Processing in RDO and on chip by generation of sensor.
The RDO system design evolves with the sensor generation.
•30 x 30 µm pixels•CMOS technology•Full Reticule = 640 x 640 pixel array
Mimostar 2 => full functionality 1/25 reticule, 1.7 µs integration time (1 frame@50 MHz clk), analog output. (in hand and tested)
All sensor families:
Phase-1 and Ultimate sensors => digital output (in development)
SensorPixels
AnalogSignals ADC /
Disc.CDS
DataSparsification
RDOto
DAQ
Mimostar sensors
Phase-1sensors - 640 us integration time
Ultimate sensors - < 200 us integration time
Leo Greiner
next year
Phase 1 – Nov 2008Ultimate – Nov 2009
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Grzegorz Deptuch
MIMOSTAR 2/3 technology
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Phase 1 / Ultimate technology (MIMOSA8/16/22)
VREF1 PWR_ON
MOSCAP
RESET
VREF2 VDD
PWR_ON
VR1
VR2
READ
CALIB
ISF
PIXEL
COLUMN CIRCUITRY
OFFSET COMPENSATED COMPARATOR
(COLUMN LEVEL CDS)
SOURCEFOLLOWER
latch
Q
Q_
READ
READ
+
+
+
+
+ +
-
- -
-
LATCH
CALIB
READ
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IHCP Marc Winter et al
Preliminary tests in Saclay of chips with 20 µm and 14 µm thick epitaxy layer• Fe55 tests• Noise and Fixed pattern noise measured
In beam MIP detection efficiency measured with silicon strip telescope
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IHCP Marc Winter et al
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IHCP Marc Winter et al
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Silicon summary, development of STAR pixels
Finished MIMOSTAR 2 with readout development Working on MIMOSTAR 3 studies Fab Phase 1 based on MIMOSA16/22 technology (digital output,
no zero suppression) Fab Ulitimate based on MIMOSA16/22 and SUZE technology
(digital with zero suppression)
Issues MIMOSTAR 3 yield Radiation hardness (bulk damage)
Reduce temperature Investigate silicon improvements
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Readout system
LBNL
Leo Greiner
Xiangming SunMichal SzelezniakThorsten StezelbergerChinh VuHoward Matis
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1 m – Low mass twisted pair
6 m - twisted pair
System Design – Physical Layout
Sensors, Ladders, Carriers(interaction point)
LU Protected Regulators,Mass cable termination
RDO Boards DAQ PCs
Magnet Pole Face(Low Rad Area ?)
DAQ Room
PowerSupplies
Platform
30 m
100 m - Fiber optic cables
Leo Greiner
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Detailed System Structure – System Level Functioning
PowerSupplies
RDO PCs
DAQ,Control,Monitor
RDO Boards
event data
JTAG to ladder
JTAG to RDO
trig
ger
cont
rol
mo
nito
r
syn
cLVDS, signal,controlMass TerminationPatch
LU protectedVoltageRegulators
address data
JTAG to ladder
sync
clk, marker, sync clk, marker, sync
LU detect / reset
address data
JTAG to ladder
sync
clk, marker, syncLadder X 4
Sensor X 10
LU protected powerpower
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Data Rates - Parameters
2.5 hits / cluster. 1 kHz average event rate. 10 inner ladders, 30 outer ladders. No run length encoding.
246 24 8 X 1027
295 29 3 X 1027
R = 2.5 R = 8.0
200 us
640 us
IntegrationTime
Radius
Leo Greiner
L
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Data Rates
Ultimate => 49.7 MB / s raw addresses.
Phase–1 => 59.6 MB / s raw addresses
Dead time primarily limited by number of externally allocated readout buffers
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Prototype test in STAR with 3 Sensor Telescope
Our goal was to test functionality of a prototype MIMOSTAR2 detector in the environment at STAR in the 2006-2007 run at STAR. We obtained information on:
Charged particle environment near the interaction region in STAR. Performance of our cluster finding algorithm. Performance of the MIMOSTAR2 sensors. Functionality of our tested interfaces to the other STAR subsystems. Performance of our hardware / firmware as a system. The noise environment in the area in which we expect to put the final PIXEL detector.
Stack of 3 MIMOSTAR2 pixel chips, Chip dimension: 4 mm X 4mm, 128 X 128 pixels
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Telescope DAQ
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Distribution of track angles in Mimostar2 telescope
Xiangming SunMichal Szelezniak
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Summary of 2007 Au + Au test in STAR
Integrated background small compared to real interaction signals
No noise pickup Hit rate as expected Readout system worked well in the STAR trigger DAQ
environment Cluster finding system worked well
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Digital data transfer test (LVDS)
200 MHz test 160 MHz required 40 data pairs (one
ladder worth) Programmed tuning of
each IO delay on Virtex5 FPGA, 7.5 ps steps
No bit errors, 12 hr, random data
ladder data generator
42 fine gauge twisted pairs
6 m robust twisted pair cable
eye pattern
Virtex5 development boardmother boardDDL/SIU fiber link
5 ns
Duplicate ~10 times for final system
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Mechanical Program
Eric Anderssen, LBNL engineer working on ATLAS pixels is phasing into our pixel program – full time in April 2008 (carbon composite expert)
Contracted ARES company for analysis on cooling, precision mount design and refinement of ladder stability. Phone meetings weekly Report due end February
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HFT Mechanical requirements
Full self consistent spatial mapping prior to installation
Installation and removal does not disturb mapping
Rapid replacement
20 Micron stability
(mapping of BaBar with visual coordinate machine)
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Rapid installation (8hr) while preserving spatial map
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Summary
Silicon design and development carried out by IPHC additional testing at LBNL
Readout system with STAR integration, well advanced, LBNL Mechanical work
Project engineer: Eric Anderssen LBNL Consulting work: ARES corporation, Los Alamos branch
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Next slide backup
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MIMOSTAR 3edgegood
MIMOSTAR 3centerbad
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Silicon Cost
Chips per ladder 10
Ladders per Detector 40
Number of Detector Copies
4
Number of working chips
1600
Yield 60%
Total chips 2700
Total wafers 44
Wafer Cost Each 7.2 k$
Wafer Costs 316 k$
Mask Cost 220 k$
Total 536 k$
8 inch wafers
60 chips/wafer
237 k$ incremental silicon cost for the 3 spare copies
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yearly dose numbers
Au + Au RHIC II luminosity: 7X1027 1/(cm2 sec) Weeks per year operation: 25 Fraction of up time: 60% radius: 2.5 cm
pion dose: 73 kRad UPC electron dose: 82 kRad Total dose: 155 kRad TLD measured projection: 300 kRad
radius: 8 cm pion dose: 7 kRad UPC electron dose: 2 kRad Total dose: 9 kRad TLD measured projection: 29 kRad
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RDO Board(s)
New motherboard
Two board System – Virtex-5 Development board mated to a new HFT motherboard
Xilinx Virtex-5 Development Board
•Digital I/O LVDS Drivers•4 X >80 MHz ADCs•PMC connectors for SIU•Cypress USB chipset•SODIMM Memory slot•Serial interface•Trigger / Control input
•FF1760 Package•800 – 1200 I/O pins•4.6 – 10.4 Mb block RAM•550 MHz internal clock
Note – This board is designed for development and testing.Not all features will be loadedfor production.
Leo Greiner