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Product Product OverviewOverviewVoice Specific Analog-to-Digital Conversion Voice Specific Analog-to-Digital Conversion ChipChipMeeting demands of high quality voice Meeting demands of high quality voice applications such as: Digital Telephony, applications such as: Digital Telephony, Digital Hearing Aids and VOIP.Digital Hearing Aids and VOIP.

TEAM W3:Digital Voice Processor 525

Jarrett Avery (W3-1)Sean Baker (W3-2) Huiyi Lim (W3-3)

Sherif Morcos (W3-4) Amar Sharma (W3-5)

Date: 5/3/2006

Final Presentation

Design Manager: Abhishek Design Manager: Abhishek JajooJajoo

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Final Presentation Final Presentation AgendaAgenda

Product Background & MarketingProduct Background & MarketingJarrett AveryJarrett Avery

Algorithm & Design ProcessAlgorithm & Design ProcessSean BakerSean Baker

Floorplan Evolution & Component Floorplan Evolution & Component LayoutLayoutSherif MorcosSherif Morcos

Top Level Layout & Digital Top Level Layout & Digital VerificationVerificationAmar SharmaAmar Sharma

Analog/Overall Verification, Specs, & Analog/Overall Verification, Specs, & Summary SummaryHuiyi LimHuiyi Lim

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Product Background & Product Background & MarketingMarketingJarrett AveryJarrett Avery

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Product BackgroundProduct Background

Find a CustomerFind a Customer Complement Current Market TrendsComplement Current Market Trends Develop for Multiple ApplicationsDevelop for Multiple Applications

Design a Comprehensive ProductDesign a Comprehensive Product Fulfill classroom design goalsFulfill classroom design goals Include useful features and benefitsInclude useful features and benefits

Use Talents of a Diverse TeamUse Talents of a Diverse Team Analog and Digital Design SkillsAnalog and Digital Design Skills

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Voice MarketVoice Market

Target CustomersTarget Customers IP Telephone ProvidersIP Telephone Providers

Vonage, Skype, and CRMVonage, Skype, and CRM Government and Security AgenciesGovernment and Security Agencies Hearing Aid ProducersHearing Aid Producers

Goal of the ProductGoal of the Product Better-Cheaper Telephone Service Better-Cheaper Telephone Service

(VOIP)(VOIP) Secure Private Telephony Secure Private Telephony Custom Hearing Aids for Specific Custom Hearing Aids for Specific

ConditionsConditions More Accurate Speech to TextMore Accurate Speech to Text

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Specific ApplicationsSpecific Applications

Communication DevicesCommunication Devices Voice Over IP HandsetsVoice Over IP Handsets Encrypted TelephonyEncrypted Telephony Digital Hearing AidsDigital Hearing Aids Speech RecognitionSpeech Recognition

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Why Choose DVP-525Why Choose DVP-525

Better than other products on the Better than other products on the marketmarket Superior Features Include:Superior Features Include:

Precision 1Precision 1stst Order Delta Sigma ADC Order Delta Sigma ADCIntegrated Butterworth Low-Pass FilterIntegrated Butterworth Low-Pass FilterBuilt on 180 nm TechnologyBuilt on 180 nm TechnologyIncludes a Min/Max Input IndicatorIncludes a Min/Max Input Indicator

Important Benefits:Important Benefits:Low Power Design – For mobile applicationsLow Power Design – For mobile applicationsSmall Foot Print – Fits into larger signal Small Foot Print – Fits into larger signal

chainschainsResilience to Circuit Noise – Optimized to Resilience to Circuit Noise – Optimized to

reduce interferencereduce interference

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Delta Sigma (Delta Sigma (ΔΣΔΣ) ) DesignDesign

AdvantagesAdvantages Accurate Conversion, oversamples Accurate Conversion, oversamples

the input signal and filters the the input signal and filters the desired signal band.desired signal band.

Filters off unwanted noise in the Filters off unwanted noise in the signal signal

Good design for audio applicationsGood design for audio applications Consists of two part design for the Consists of two part design for the

team team Analog ModulatorAnalog ModulatorDigital DecimatorDigital Decimator

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Algorithm & Design ProcessAlgorithm & Design ProcessSean BakerSean Baker

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ΔΣΔΣ Algorithm (Analog) Algorithm (Analog)

Lowpass Filter

Delta Sigma Modulator

Input from outside world

Bitstream into sinc filter

Filtered

analog

signal

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ΔΣΔΣ Algorithm (Digital) Algorithm (Digital)

Sinc Filter Peak Input Indicator

Bitstream from

modulator Nyquist clock

Digital output

Digital Output Max / Min

output

Oversampled clock

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Top Level SchematicTop Level Schematic

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Design ProcessDesign Process

Integrate &

Simulate

Integrate &

Simulate

Integrate &

Simulate

Architecture

Behavioral Circuit Elements

Topologies

Schematic

Layout

Extract

Architecture

Behavioral Verilog

Structural Verilog

Schematic

Layout

Extract

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Design Process (cont.)Design Process (cont.)

Both teams worked somewhat Both teams worked somewhat independentlyindependently Analog side used behavioral sinc filterAnalog side used behavioral sinc filter Digital side used simulated inputsDigital side used simulated inputs

When either team takes a major When either team takes a major step, make sure everything still step, make sure everything still worksworks Compare structural to behavioral, Compare structural to behavioral,

schematic to structural, etcschematic to structural, etc When possible, put the two halves When possible, put the two halves

togethertogether

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Major Design DecisionsMajor Design Decisions

Focus on voice specific frequencies: 0 – Focus on voice specific frequencies: 0 – 10 KHz10 KHz Sets Nyquist clock at 20 KHzSets Nyquist clock at 20 KHz

First order modulatorFirst order modulator Oversampling rate of 256Oversampling rate of 256

Sets oversampled clock at 5.12 MHzSets oversampled clock at 5.12 MHz Second order sinc filterSecond order sinc filter

Lth order modulator requires L+1 order sinc Lth order modulator requires L+1 order sinc filterfilter

16 bit resolution16 bit resolution Mth order sinc filter requires Mth order sinc filter requires

[ M*log[ M*log22(OSR) ] bits(OSR) ] bits Designed with NCSU design kitDesigned with NCSU design kit

Might’ve been easier to use GPDK, if used Might’ve been easier to use GPDK, if used from the startfrom the start

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Floorplan EvolutionFloorplan EvolutionComponent LayoutComponent Layout

Sherif MorcosSherif Morcos

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Floorplan EvolutionFloorplan Evolution

Floorplan changed several timesFloorplan changed several times Original floorplan:Original floorplan:

18 bit decimator and 218 bit decimator and 2ndnd order modulator order modulator Overall chip area = 335 Overall chip area = 335 μμm x 230 m x 230 μμm = m =

77,000 77,000 μμm²m² Modified floorplan Modified floorplan

22ndnd order analog modulator with enormous order analog modulator with enormous resistors and capacitors (about 150 resistors and capacitors (about 150 μμm x m x 50 50 μμm = 7,500 m = 7,500 μμm² each)m² each)

33rdrd order 24-bit digital sinc filter plus PII order 24-bit digital sinc filter plus PII module and clock divider (14,500 module and clock divider (14,500 transistors)transistors)

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Original FloorplanOriginal Floorplan

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Floorplan Evolution Floorplan Evolution (cont’d)(cont’d)

Final floorplan:Final floorplan: With previous floorplan, might have With previous floorplan, might have

violated area constraint of 300,000 violated area constraint of 300,000 μμm²m² Change to analog modulator reduced Change to analog modulator reduced

size of designsize of design Determined that passive elements could Determined that passive elements could

be reduced in size considerablybe reduced in size considerably After modifications, floorplan area was After modifications, floorplan area was

estimated at about 400 estimated at about 400 μμm x 340 m x 340 μμm = m = 136,000 136,000 μμm²m²

Final layout grew slightly to 500 Final layout grew slightly to 500 μμm x m x 378 378 μμm = 189,000 m = 189,000 μμm² with slight m² with slight increase in size of passive componentsincrease in size of passive components

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Final FloorplanFinal Floorplan

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ΔΣΔΣ Modulator Transistor - Modulator Transistor - LayoutLayout

17 Analog Transistors17 Analog Transistors

Differential Op AmpDifferential Op Amp ComparatorComparator D Flip FlopD Flip Flop

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Decimator – LayoutDecimator – Layout

Sinc2 FilterSinc2 Filter

PII FunctionPII Function256 Clock Divider256 Clock Divider

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Isolation RingsIsolation Rings

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Top Level Layout & Digital Top Level Layout & Digital VerificationVerificationAmar SharmaAmar Sharma

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Final Top Level LayoutFinal Top Level Layout

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Final FloorplanFinal Floorplan

ModulatorModulator

Low Pass Low Pass FilterFilter

Clock Clock DividDividerer

PIIPIISinc FilterSinc Filter

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Data Flow – Top Level Data Flow – Top Level LayoutLayout

Wait Period Wait Period

1-Bit Stream 1-Bit Stream

Min Min

16-Bits 16-Bits Out Out

Max Max

Low Pass Low Pass ComponentsComponents

Delta Sigma Delta Sigma Modulator Modulator ComponentsComponents

PIIPIISinc Sinc FilterFilter

CLK DividerCLK Divider

Analog InputAnalog Input

Filtered SignalFiltered Signal

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Poly & ActivePoly & Active

Poly density: Poly density: 23.92%23.92%

Active / Well density: Active / Well density: 1.01%1.01%

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Metal 1Metal 1

Metal 1 density: Metal 1 density: 25.33%25.33%

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Metal 2Metal 2

Metal 2 density: Metal 2 density: 23.89%23.89%

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Metal 3Metal 3

Metal 3 density: Metal 3 density: 22.53%22.53%

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Metal 4Metal 4

Metal 4 density: Metal 4 density: 0.68%0.68%

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Digital VerificationDigital Verification

All digital components functionally All digital components functionally verified previouslyverified previously

No timing analysis requiredNo timing analysis required Clocks domains are 5.12 MHz and 20 KHzClocks domains are 5.12 MHz and 20 KHz Critical path (two 16 bit adders) are Critical path (two 16 bit adders) are

located in 20 KHz domain located in 20 KHz domain Optimization - Main focus to ensure Optimization - Main focus to ensure

signal integritysignal integrity Initial layouts had outputs not reaching full-Initial layouts had outputs not reaching full-

railrail Optimizations widened Vdd and Gnd linesOptimizations widened Vdd and Gnd lines Outputs now swing full-railOutputs now swing full-rail

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High Output LevelsHigh Output Levels

BeforeBefore AfterAfter

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Sinc Filter extractedRC Sinc Filter extractedRC OutputOutput

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PII extractedRC Output PII extractedRC Output (Max)(Max)

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PII extractedRC Output PII extractedRC Output (Min)(Min)

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Analog/Overall Verification Analog/Overall Verification Specs & SummarySpecs & Summary

Huiyi LimHuiyi Lim

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Analog VerificationAnalog Verification

Analog half is simulated as Analog half is simulated as ExtractedRCExtractedRC

Input is a weighted sum of Input is a weighted sum of frequencies found in the human frequencies found in the human voicevoice

Output of analog half is a bitstreamOutput of analog half is a bitstream To make sense of it, behavioral To make sense of it, behavioral

decimator is useddecimator is used To get proper results, simulator must To get proper results, simulator must

be set to be as accurate as possiblebe set to be as accurate as possible Greatly increases running time of Greatly increases running time of

simulationsimulation

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Analog Verification Analog Verification (cont.)(cont.)

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Overall VerificationOverall Verification

Extracted the lowpass filter, Extracted the lowpass filter, modulator, and sinc filter modulator, and sinc filter together, then simulatedtogether, then simulated Used actual outputs from clock Used actual outputs from clock

divider in simulation without divider in simulation without including it in simulationincluding it in simulation

Input is a simple 2 KHz sine waveInput is a simple 2 KHz sine wave

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Overall Verification Overall Verification (cont.)(cont.)

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Chip SpecsChip Specs

ModuleModule PowerPower TransistorsTransistors AreaArea Transistor Transistor DensityDensity

ModulatorModulator Shares Shares 235.4 uW235.4 uW

3232 40,390 40,390 um^2um^2

.00079.00079

LowpassLowpass Shares Shares 235.4 uW235.4 uW

00 55,235 55,235 um^2um^2

N/AN/A

Clock Clock DividerDivider

7.138 uW7.138 uW 334334 1,728 um^21,728 um^2 .1932.1932

Sinc FilterSinc Filter Shares Shares 235.4 uW235.4 uW(consumes (consumes 15.33 uW 15.33 uW

itself)itself)

3,2963,296 18,686 18,686 um^2um^2

.1764.1764

PIIPII 292 nW292 nW 27822782 17,912 17,912 um^2um^2

.1553.1553

TotalTotal 242.8 uW242.8 uW 6,4446,444 187,500 187,500 um^2um^2

.0346.0346

•Aspect Ratio: 1.3

•Input Bandwidth: 0 – 10 KHz

•Oversampling rate:

256

•16 bit resolution

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Pin SpecsPin Specs

InputsInputs 2 Analog Inputs2 Analog Inputs 12 Wait Period Inputs12 Wait Period Inputs Oversampled Clock Oversampled Clock

InputInput OutputsOutputs

16bit Output Pins16bit Output Pins 16bit Min Pins16bit Min Pins 16bit Max Pins16bit Max Pins

OtherOther Vdd & Gnd PinsVdd & Gnd Pins

Wait <0>

Wait <11>

Max <0>

Max <15>

Y <0>Min <0>

Y <15>Min <15>

VddGnd

+Analog In-Analog In

OS Clock

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Product SummaryProduct Summary

Achieved first working mixed Achieved first working mixed signal design in 18-525 historysignal design in 18-525 history

Met course objectivesMet course objectives Low power design (242 Low power design (242 μμW)W) Small size (500 Small size (500 μμm x 370 m x 370 μμm)m) Under 100 pins (55 total pins)Under 100 pins (55 total pins)

Developed a practical & Developed a practical & marketable productmarketable product