uKeywords:

Low-noise amplier (LNA)

a h

d is

iase

n in

at t

matching and low noise gure (NF) while keeping high third-order input intercept point (IIP3)

improvement with the DS method. The new implementation has been used in a 0.18-mm CMOS highlinear LNA. The measured results show that the LNA achieves +11.92dBm IIP3 with 9.36 dB gain, 2.25 dB

& 2008 Elsevier Ltd. All rights reserved.

arameteneratulations. For t

the problem.

linearization techniques. It uses two transistors connected in

im-ationinputd DSIIP3,

In this paper, new implementation of a high linear LNA

ARTICLE IN PRESS

Contents lists availabl

.e

Microelectron

Microelectronics Journal 40 (2009) 197201thus allowing a feasible source degeneration inductance at theThis work was supported in part by the National Natural Science Foundation of

China (No. 90407006) and the Fok Ying Tung Education Foundation (No. 104028).parallel and biased in the weak inversion region and in the strong using the improved DS method is proposed. The inputstage is formed by two transistors connected in parallel.One transistor is biased in the strong inversion region andanother one is biased in the moderate inversion region,

sources of the two transistors while keeping high IIP3 improve-ment with the DS method. The new implementation has been

$

Corresponding author. Tel.: +8610 62795096; fax: +861062795104.

E-mail address: chibylxc@tsinghua.edu.cn (B. Chi).0026-26

doi:10.1The derivative superposition (DS) method [24], which fallsunder the category of feed forward, is one of the various

they need two source degeneration inductors and complicate thecircuit design.satised [1]. Considering that the power supply has beenlowered along with the scaling down of the feature size in theCMOS process, the high IIP3 requirement is a big design challengeand many linearization techniques are proposed to solve

(40.5 nH), the conventional DS method provides no IIP3provement at all. But, with a very small source degenerinductance, it is difcult to simultaneously achieve a goodimpedance matching and low NF. Although the modiemethod [1] or new circuit topology [5] is proposed to boost(LNA), high linearity should be achieved without lowering otherperformances, such as low noise gure (NF), high gain, goodimpedance matching and low power consumption. The linearityof the LNA is usually specied as an input-referred third-orderintercept point (IIP3). Many RF systems demand higher than+8dBm IIP3 LNAs while keeping the other performance

improvement using this method is only modest at RF (3dB, asreported in [3]). Ref. [4] boosts IIP3 in the DS method by 10dB byreducing the source degeneration inductance and using thecascode technique to reduce the drain load impedance. However,as reported in [1], for feasible values of the source degenerationinductance, which is limited by the downbond inductanceCMOS

Inter-modulation distortion

Derivative superposition (DS)

Third-order input intercept point (IIP3)

1. Introduction

Linearity is a key performance pnonlinearity may cause harmonic gdesensitization, blocking, cross moddistortion, and many other problem92/$ - see front matter & 2008 Elsevier Ltd. A

016/j.mejo.2008.09.007er for RF circuits sinceion, gain compression,and inter-modulation

he low-noise amplier

inversion region, respectively. The sizes and bias voltages of thetwo transistors are chosen such that the positive peak of the third-order nonlinear coefcient of the weak inversion transistor isaligned with the negative peak of that of the strong inversiontransistor. This results in an extended linear range over which thethird-order nonlinear coefcient is close to zero. However, the IIP3RFNF and 7.5mA at 1.8V power consumption.New implementation of high linear LNAsuperposition method$

Shuguang Han a, Baoyong Chi b,, Zhihua Wang b

a Department of Electronic Engineering, Tsinghua University, Beijing 100084, Chinab Institute of Microelectronics, Tsinghua University, Beijing 100084, China

a r t i c l e i n f o

Article history:

Received 4 October 2007

Received in revised form

16 September 2008

Accepted 16 September 2008Available online 20 November 2008

a b s t r a c t

New implementation of

superposition (DS) metho

parallel. One transistor is b

moderate inversion regio

degeneration inductance

journal homepage: wwwll rights reserved.sing derivative

igh linear low-noise amplier (LNA) using the improved derivative

proposed. The input stage is formed by two transistors connected in

d in the strong inversion region as usual and another one is biased in the

stead of the weak inversion region, thus allowing a feasible source

he sources of the two transistors to achieve a good input impedance

e at ScienceDirect

lsevier.com/locate/mejo

ics Journal

used in a 0.18-mm CMOS high linear LNA. The measured resultsverify the feasibility of the proposed implementation in improvingIIP3 of the LNA.

2. Circuit description

Fig. 1 shows the principle of the DS method [24]. Twotransistors are connected in parallel and their sources aredegenerated by the same inductance L. One transistor, MA, worksin the strong inversion region as usual and another one, MB, worksin the moderate inversion region instead of the weak inversionregion. Fig. 2 shows the DC IV curve of the transistors, thevertical axis is ln(ID) and sqrt(ID), respectively. The DC IV curvecould be divided into three regions: weak inversion, moderateinversion and strong inversion. The transistor shows differentIV characteristics in different regions. The IV curve in the weakinversion region shows exponential characteristics, while theIV curve in the strong inversion region shows square-lawcharacteristics. The transition region between these two regionsis the so-called moderate inversion region. From Fig. 2, it could beseen that the transistor works in the moderate inversion regionwhen VGS is between 0.3 and 0.5V.

Fig. 3 shows the third-order nonlinear coefcient G3A and G3Bof MA and MB versus the voltage source VGS. By setting thevoltage source VBD to 0.3V, MA is designed to work in the stronginversion region and MB is designed to work in the moderate

inversion region. G3 is dened as

G3 1

6

q3IDqV3GS

and controls the third-order inter-modulation distortion (IMD3)at low signal levels, thus determines IIP3. It could be seen that thethird-order nonlinear coefcient G3A of the transistor in the stronginversion region is negative and the third-order nonlinearcoefcient G3B of the transistor in the moderate inversion regionis positive. The negative G3A is aligned with the positive G3B, butthey have a similar mirror-image curvature, the resultingcomposite G3 will be close to zero and the theoretical IIP3will be signicantly improved in a relatively wide range of thegate biases.

Fig. 4 shows the schematic of the whole LNA. The input stage isthe same with Fig. 1, only the ESD protection circuit and the gateseries inductance are added. The gate series inductance is toresonate with the gate-source capacitance of the input transistorsto provide a real resistance for the input impedance matchingpurpose. MA and MB are biased by the off-chip bias voltages, VAand VB, to work in the strong inversion region and the moderateinversion region, respectively, so that their third-order nonlinearcoefcients G3A and G3B reach the negative peak and positivepeak. MA and MB could also be biased on-chip with a well-designed bias circuit. Since Fig. 3 shows that the theoretical IIP3will be signicantly improved in a relatively wide range of gatebiases (about 70mV), the accuracy requirements on VA and VB arenot high, so it should not be very challenging to design the on-chip bias circuit. In our work, the off-chip biases are applied forthe prototyping purpose.

ARTICLE IN PRESS

S. Han et al. / Microelectronics Journal 40 (2009) 197201198Fig. 1. Principle of the DS method.Fig. 2. The DC IV curve of the transistors,Fig. 3. The third-order nonlinear coefcient G3A and G3B of MA and MB versus thevoltage source VGS.the vertical axis is ln(ID) and sqrt(ID).

After the biases VA and VB are xed, the size of MA is chosenbased on the normal noise/power optimization procedure of theinductance source-degenerated common-source LNA. Then thesize of MB is adjusted to make the composite G3 close to zero in arelatively wide range of gate biases.

The cascode transistor is added to reduce the drain loadimpedance of the composite input transistors at the secondharmonic frequency, so that the effect of the second-orderharmonic response on IIP3 is reduced to a great extent [4].Another goal is to improve the isolation between the input andoutput of the LNA.

On-chip inductance Ld is resonated with the output nodeparasitic capacitance and on-chip capacitance Cd to provide theload for the LNA and also provide the output impedance matching.

The source degeneration inductance, provided by the bond-wire, is about 1.6nH to generate a real resistance at the input ofthe LNA, thus allowing simultaneously the input impedancematching and the noise matching. This inductance requirement isfeasible for the normal package. So the low source degenerationinductance requirement in Ref. [4] has been cancelled by makingone of the parallel transistors work in the moderate inversionregion instead of the weak inversion region.

3. Simulated results

The LNA has been implemented in the 0.18-mm CMOS process.Fig. 5 gives out the simulated S-parameters with Agilent ADSwhen VA 0.77V and VB 0.47V. The gure shows that theLNA has achieved good input impedance matching and output

ARTICLE IN PRESS

ole LNA using the DS method.

Fig. 6. The simulated stability factor k of the LNA as well as D factor.

S. Han et al. / Microelectronics Journal 40 (2009) 197201 199Fig. 4. Schematic of the whFig. 5. The simulated S parameters with Agilent ADS when VA 0.77V and VB 0.47V.

impedance matching with a 1.3GHz operating frequency, and itcould provide 12.3 dB power gain and 21.7dB reverse isolation.Since MB works in the moderate inversion region, the gate voltage

variation of MB has little effects on the S-parameter performanceof the LNA.

Fig. 6 gives out the simulated stability factor k of the LNA aswell as D factor (D |S11S22S12S21|). It could be seen that k isgreater than 1 and D factor is smaller than 1, so the LNA isunconditionally stable.

Fig. 7 gives out the simulated effective small-signal transcon-ductance Gm of the LNA and the contribution of MA and MB. Gm ismainly dependent on MA, and MB has little contribution to Gmsince MB works in the moderate inversion region. Here VGS isthe gate voltage of MA, and the gate voltage of MB is lower thanVGS by 0.3V.

4. Measured results

The LNA has been implemented in the 0.18-mm CMOS process.Fig. 8 shows its microphotograph. The die area is about 0.6mm2,most of which is occupied by the on-chip inductance, PADs andESD protection circuits. The bare die is directly bondwired into a

ARTICLE IN PRESS

Fig. 8. The microphotograph of the presented LNA.

Fig. 7. The simulated effective small-signal transconductance Gm of the LNA andthe contribution of MA and MB.

S. Han et al. / Microelectronics Journal 40 (2009) 197201200Fig. 9. The measured power gain and NF versus frePCB and all the measured results are calibrated with anotheridentical PCB without the die bondwired.

The measurements show that the power gain of the1.35GHz LNA is about 9.36dB with an NF of 2.25dB. Fig. 9shows the measured power gain and NF versus frequency withan Agilent noise gure analyzer. The gain is lower than thesimulated |S21| by about 3dB and NF is higher than the simulatedone by about 1.2 dB. The reason may be due to the inaccuracy inRF component models and the package parasitic effects whichcould not be predicted correctly since our package is completedby hand.

Two-tone test is used to obtain the IIP3 of the LNA. Two RFtones located in 1.35GHz750kHz are input into the LNA, and thetwo tones have the same power. Fig. 10 gives the measured IIP3 ofthe LNA at different gate voltages VB of MB, here the gate voltageVA of MA is xed at 0.767V. It could be seen that the IIP3 of theLNA achieves the highest value (11.92dBm) when MB works in themoderate inversion region, which is much higher than the casewhen MB works in the weak inversion region and in the stronginversion region. Consider that the power supply of the LNA isonly 1.8V, and the IIP3 of 11.92dBm is very superior.quency with an Agilent noise gure analyzer.

ARTICLE IN PRESS

-40

V-60

-80-25 -20 -15 -10 -5 0 5 10 15 20

Pin (dBm)

80

6060

40

20

0

-20

Pou

t (dB

m)

VB = 0.281 V

IIP3 = 4.17 dBm

S. Han et al. / MicroelectronThe LNA draws 7.5mA current from a 1.8V power supply. If wedene the gure of merit (FOM) of the LNA as follows:

FOM Gain IIP3 mW f GHzF 1 PDC mWwhere F is the noise factor; a summary of the measured results ofthe LNA is provided in Table 1 along with a comparison with thestate-of-the-art high linear CMOS LNA.

5. Conclusion

New implementation of a high linear LNA using the conventionalDS method is proposed. By making one transistor work in themoderate inversion region instead of the weak inversion region, afeasible source degeneration inductance is allowed to achieve agood input impedance matching and low NF while keeping highIIP3 improvement with the DS method. The LNA has beenimplemented in the 0.18-mm CMOS process and the measuredresults verify the feasibility of the proposed implementation.

40

20

0

-20

-40

-60

-80-25 -20 -15 -10

Pou

t (dB

m)

Fig. 10. The measured IIP3 of

Table 1Comparison of state-of-the-art highly linear CMOS LNA

Work Technology (mm) Freq. (GHz) Power gain (dB

[1] 0.25 0.9 15.5

[6] 0.25 2.2 14.9

[4] 0.35 0.9 10

[7] 0.35 0.9 2.5

[5] 0.35 0.9 1*[8] 0.18 2 6.7*

This work 0.18 1.35 9.36

Note: * means that the gain is deduced from the IIP3 measured gures.5040

2030

010

-20-30

-10

-40

-60-50

-80-90

-100

-70

-25 -20 -15 -10 -5 0 5 10 15 20Pin (dBm)

Pou

t (dB

m)

VB = 0.467 V

B = 0.767 V

IIP3 = 11.92 dBm

ournal 40 (2009) 197201 201ics JReferences

[1] V. Aparin, L.E. Larson, Modied derivative superposition method for linearizingFET low-noise ampliers, IEEE Trans. Microwave Theory Tech. 53 (2) (2005)571581.

[2] D. Webster, J. Scott, D. Haigh, Control of circuit distortion by the derivativesuperposition method, IEEE Microwave Guided Wave Lett. 6 (3) (1996)123125.

[3] B. Kim, J.-S. Ko, K. Lee, A new linearization technique for MOSFET RF amplierusing multiple gated transistors, IEEE Microwave Guided Wave Lett. 10 (9)(2000) 371373.

[4] T.W. Kim, B. Kim, K. Lee, Highly linear receiver front-end adopting MOSFETtransconductance linearization by multiple gated transistors, IEEE J. Solid-State Circuits 39 (1) (2004) 223229.

[5] S. Ganesan, E. Sanchez-Sinencio, J. Silva-Martinez, A highly linearlow-noise amplier, IEEE Trans. Microwave Theory Tech. 54 (12) (2006)40794085.

[6] Y.-S. Youn, J.-H. Chang, K.-J. Lee, et al., A 2GHz 16dBm IIP3 low noise amplierin 0.25mm CMOS technology, IEEE Int. Solid-State Circuits Conf. (2003)452453.

[7] Y. Ding, R. Harjani, A +18dBm IIP3 LNA in 0.35mm CMOS, IEEE Int. Solid-StateCircuits Conf. (2001) 162163.

[8] T.S. Kim, B.S. Kim, Post-linearization of cascode CMOS low noise amplierusing folded PMOS IMD sinker, IEEE Trans. Microwave Wireless ComponentsLett. 16 (4) (2006) 182184.

-5 0 5 10 15 20Pin (dBm)

IIP3 = 2.84 dBm

the LNA (VA 0.767V).

) NF (dB) IIP3 (dBm) PDC (mA atV) FOM

1.65 +22 9.3 at2.6 452.8

3 +16.1 9.4 at 2.5 118.4

2.85 +15.6 7.82 at 2.7 17.1

2.8 +18 15 at 3 2.5

2.95 +21 9 at 2.5 4.1

1.4 +13.3 8 at 1.8 34.9

2.25 +11.92 7.5 at 1.8 19.8