A broadband Low Noise Amplier with built-in linearizer in 0.13-mmCMOS process

Habib Rastegar 1, Jee-Youl RyuPukyong National University (PKNU), Department of Information and Communications Engineering, Republic of Korea

a r t i c l e i n f o

Article history:Received 20 April 2014Received in revised form23 February 2015Accepted 15 May 2015

Keywords:Low Noise Amplier (LNA)CMOSHigh linearityChebyshev lterInverter

a b s t r a c t

A linearized ultra-wideband (UWB) CMOS Low Noise Amplier (LNA) is presented in this paper. Thelinearity performance is enhanced by exploiting PMOSNMOS common-gate (CG) inverter as a built-inlinearizer which leads to cancel out both the second- and third-order distortions. Two inductors areplaced at the drain terminals of CG transistors in the built-in linearizer to adjust the phase andmagnitude of the third-order distortion. A second-order band-pass Chebyshev lter is utilized in theinput port of common-source (CS) conguration to provide broadband input matching at 3.110.6 GHzfrequency range to a 50- antenna. Series and shunt peaking techniques are employed to extend thebandwidth (BW) and to atten the gain response. Simulated in 0.13 mm CMOS technology, the CMOS LNAexhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features amaximum gain of 10.24 dB, 0.94.1 dB noise gure (NF), and a third-order input intercept point (IIP3) of6.8 dBm at 6.3 GHz.

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1. Introduction

The increasing demand for wireless communication hasresulted in many communication standards. In the broadbandsystems the receiver chain has to be able to minimize/cancel theadverse effects of large number in-band interferences and inter-modulation/cross-modulation caused by transmitter leakage orblockers. Such interference minimization/cancellation requiresdiligent design considerations.

Linearity is the most crucial design specication which plays animportant role in RF systems. Special attention has to be paid tothe linearity performance of the LNA in a wireless transceiverdesign. It is noteworthy to mention that the enhancement inlinearity performance should not compromise the desired power/voltage gain or noise gure performance. Various LNA topologiesare reported using different techniques to achieve high linearity.For instance [1] employed optimum biasing (OB) technique to nullthe main source of nonlinearity (i.e., third-order derivation oftransconductance (gm'' )) in common-source (CS) without anyadditional device and used device bias at point which its IIP3 ismaximum. The main bottleneck of OB technique is that thetransistor must be biased at sweet point; thus, limiting thetransconductance which leads to reduced gain and increased NF.

Feed-forward technique is based on splitting the input into twosignals amplied by two ampliers with different transfer char-acteristics such that, upon combining their output signals, theirdistortions cancel the other one.

In [2], feedforward technique was exploited in differential pairtransistors to improve IIP3 performance. This technique led toobtain high linearity, but consumed much power consumptionand also degraded the gain and hence, NF. The Derivative Super-position (DS) technique is a special case of the feedforwardtechnique [312]. DS method consists of two parallel transistors.Main transistor works in the strong inversion region and theauxiliary transistor works in the weak inversion region. In DSmethod, by tuning the sizes and bias conditions of the transistors,gm'' can be minimized or even canceled. The drawback of thistechnique is that it is not able to eliminate the second-ordernonlinearity coefcient (gm' ) which degrades the IIP3. In DStechnique the auxiliary transistor which is biased in the weakinversion region connected to the main transistor and hence,degrades the input matching (due to parasitic capacitances) andNF (due to the gate-induced noise) of whole LNA. To overcomethese shortcomings, the modied DS (MDS) was proposed in [1315]. Additionally, MDS method can eliminate the gm' in order toachieve high linearity.

In Post-Distortion (PD) method [1620], not only the auxiliarytransistor does not connect directly to the input of the maindevice, but also connects to the output of the main transistorwhich minimizes the degradation on the noise gure and inputimpedance matching.

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Microelectronics Journal

http://dx.doi.org/10.1016/j.mejo.2015.05.0060026-2692/& 2015 Elsevier Ltd. All rights reserved.

E-mail addresses: hrastegar@pknu.ac.kr (H. Rastegar),ryujy@pknu.ac.kr (J.-Y. Ryu).

1 Tel.: 82 51 629 6289; fax: 82 51 629 6229.

Microelectronics Journal 46 (2015) 698705

In this paper, a second-order Chebyshev lter is employed inthe input common-source transistor to achieve wideband BW forUWB applications. We propose a PMOSNMOS CG inverter tominimize/cancel both the second- and third-order distortions,simultaneously. Two inductors are also inserted in the drain ofCG transistors in the built-in linearizer to tune the magnitude andphase of gm'' in order to achieve high linearity. Shunt and seriestechniques are utilized to extend the BW, increase the gainresponse, and reduce the NF.

This paper is organized as follows. In Section 2, input impe-dance matching network will be described. Linearity analysiswill be presented in Section 3. In Section 4, the proposed circuitand design considerations are presented and the simulationresults and a comparison with other published works are shown.Section 5, summarizes and concludes this work.

2. Broadband input matching network

The lter design technique is employed for input impedancematching. The lter actually makes use of the parasitic gatesource capacitance (Cgs). The small-signal model of the inputmatching network is shown in Fig. 1.

The Ccoupling is used as a coupling capacitor. The values ofsecond-order Chebyshev lter elements are chosen to set thecorner frequencies in 3.1 GHz and 10.6 GHz. The combination ofM1 input parasitic capacitance (Cgs), external capacitance (Cex),source degeneration inductor (Ls), series-gate inductor (Lg), L1 andC1 form second-order Chebyshev ltering structure that canachieve a wideband input matching. The input impedance can beshown as follows:

Zin Z1Z2TLsZ1Z2TLs

1

where Z1 sL1 j j 1sC1; Z2 s LgLs 1sCt; Ct CgsCex ; T gmCt

The Ls results in a real resistive value equals to gmLs/Ct to matchthe source impedance to 50 (Rs50 ).

The parasitic capacitances Cgs1 and Cex must follow the requiredcomponent value in the lter design and the size of the transistorM1 must be selected carefully. It may be necessary to adjust thelter corner frequency and choose a reasonable size in order tomeet all the specications. Fig. 2 shows the simulated input returnloss (S11) of the proposed LNA for two conditions: (a) variable Ctwith constant W1 (b) variable W1 with constant Ct. As expected,the S11 improves by inserting external capacitance (Cex) in parallelwith gatesource capacitance (shown in Fig. 2(a)). This is due tothe fact that the Cex along with other parasitic capacitancesresonate with inductors in the input port to generate the real partof the input impedance (Zin). On the other hand, as shown in Fig. 2(b) the S11 degrades as W1 increases, because of non-zero imagin-ary part of Zin. In conclusion, there is a sever tradeoffs among S11,noise gure (NF) and gain of LNA about existence of Cex that willbe discussed in the next sections.

3. Linearity analysis

3.1. Linearity fundamentals and Derivative Superposition (DS)technique drawbacks

The non-linearity of a MOSFET transistor arises from itsvoltage-to-current (VI) conversion [13]:

iDS Idcgm1vgsgm2v2gsgm3v3gs 2

where gm1 is the main transconductance of the MOSFET, gm2 is thesecond-order non-linear coefcient obtained by the second-orderderivative of the DC transfer characteristic, and gm3 is the third-order non-linear coefcient obtained by the third-order derivativeof the DC transfer characteristic.

To determine IIP3 at low level signal, gm3 is the dominantcoefcient. The IIP3 of a non-linear device gives as follows:

IIP343j gm1gm3

js

3

The DS method (shown in Fig. 3) nulls the negative third-orderderivative of the main eld-effect transistor's (FET's) dc transfercharacteristic (gm3) by paralleling the auxiliary FET biased near theweak inversion region with the positive gm3 [14]. The DS methodFig. 1. Small-signal model of the input port of LNA.

0 2 4 6 8 10 12 14-20

-15

-10

-5

0

Frequency (GHz)

S11

(dB

)

Without CexCt=0.15 pFCt=0.3pF

0 2 4 6 8 10 12 14-20

-15

-10

-5

0

Frequency (GHz)

S11

(dB

)

W1=75umW1=82.5umW1=90um

Fig. 2. Input return loss for two conditions: (a) variable Ct with constant W1(b) variable W1 with constant Ct.

Fig. 3. The Derivative Superposition circuit [11].

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705 699

has the following drawbacks. First, it is valid only at low frequen-cies at which the effect of circuit reactance is negligible [15].Second, to obtain linearity in DS method, one transistor is biasedin weak inversion region so this transistor degrades noise gure ofthe LNA due to its high gate induced current noise getting added tothe input [16]. Third, the auxiliary transistor which is biased in theweak inversion region adds extra capacitance to the input nodeand changes the input matching of the whole LNA. The second-order non-linearity (gm2) (is generated through gatesource andgatedrain capacitances) get mixed with fundamental compo-nents and hence, degrades linearity performance and lessimprovement is obtained. To overcome these drawbacks, wepropose a CG PMOSNMOS inverter for the cascode LNA as abuilt-in linearizer. The proposed linearization technique adoptsPMOS and NMOS transistors in common-gate conguration tocancel out the second- and third-order nonlinearity simulta-neously in order to enhance the linearity performance.

3.2. Theoretical concept of the proposed linearization technique

In this section, the proposed built-in linearizer structure and itsoperating principle are presented. The analytical of the proposedLNA with linearity enhancement will be elaboratively presented inthe next section. To achieve very low third-order distortion, it isessential to consider both the second- and third-order non-linearities. Therefore, our analysis is concentrated on cancela-tion/minimization of gm2 and gm3 in order to increase IIP3 or toreduce the third-order intermodulation distortion (IMD3). Theinductors (LN and LP) and the parasitic capacitances at the drainof MN, MP and M2 form a broadband network. Proper choice of

inductor sizes leads to cancel the capacitive effects, yieldingeffectively a short circuit over the whole BW. Under this condition,non-linearity from M2 can be neglected. As shown in Fig. 5 thenon-linearity drain current of M1 moves toward the MN and MPtransistors which are utilized as CG conguration and hence,operate as a current buffer. The main responsibility of built-inlinearizer stage (MN and MP) is to absorb the non-linearity of M1drain current. Thus, the fundamental current component of M1 canbe delivered to output port. Fig. 6 illustrates the conceptual idea ofthe linearization technique. Fig. 6 depicts that the drain current ofM1 (id1) can be expressed as the sum of the drain current of MN(id,N) and MP (id,P) as follows:

id;N gm1;Nvgs;Ngm2;Nv2gs;Ngm3;Nv3gs;N 4

id;P gm1;Pvgs;Pgm2;Pvgs;P2gm3;Pvgs;P3 5

id1v1 id;N id;P gm1;Nvgs;Ngm2;Nv2gs;Ngm3;Nv3gs;N

gm1;Pvgs;Pgm2;Pvgs;P2gm3;Pvgs;P3

6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.002

0.004

0.006

0.008

0.01

0.012

gm1ngm1p

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.01

0.02

0.03

0.04gm2ngm2p

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

VGS(V)

gm3pgm3n

Fig. 4. (a) Simulated gm1n and gm1p. (b) Simulated gm2n and gm2p. (c) Simulatedgm3n and gm3p.

Fig. 5. The proposed LNA circuit with built-in linearizer (bias circuit not shown).

Fig. 6. Conceptual view of the proposed linearization technique.

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705700

Since vgs,P is a function of vgs,N, it can be expanded into powerseries of vgs,N as follows:

vgs;P c1vgs;Nc2v2gs;Nc3v3gs;N 7

where cis are in general frequency dependent. In practice, the -network cancels the effects of c2 and c3 at the frequency of interest[21].

To nd the coefcient cis, we should solve the equation afterexpanding id1 as a power series of vgs,P and replacing it with (7). Byusing power series and replacing (7) in (6), the drain current id1can be re-expressed as function of vgs,N as follows:

id1 id;N id;P gm1;Nc1gm1;P

vN gm2;Nc21gm2;P

v2Ngm3;Nc31gm3;Pv3N8

The gm3,N changes from positive to negative when the transis-tor moves fromweak to strong inversion region. In other words, bychanging gate-bias voltage of PMOS transistor, the parameter c1can be varied. It can be deduced from (8) that c1 has a positivevalue from the bias circuit theory. As shown in Fig. 4(b) and (c), byadjusting the gate-bias voltages and widths of main and auxiliarytransistors, both the gm2 and gm3 can be closed to zero and hence,the IIP3 can be enhanced.

3.3. High frequency analysis of PMOSNMOS common-gate inverterwith Volterra series

The circuit of the built-in linearizer for high frequency distor-tion analysis is shown in Fig. 14 ( see Appendix A). The parasiticcapacitance associated with the drain of M1 and M2 are notmodeled here, because they are absorbed by the LC network.We also neglect distortion due to nonlinear ro, because the passiveload resistance is much smaller than the transistor output resis-tance. The analysis is limited up to third order, assuming a weaklynonlinear circuit (Appendix A).

The fundamental and third-order distortion of the outputvoltage (Vo) can be expressed as follows:

Vo;fund A1 s o Vs gm1;N B1 s o Vs gm1;P ZL 9

Vo;thirdorder A1 s1; s2; s3 V3s

gm1;N B1 s1; s2; s3 oV3s

gm1;P A1 s1 A2 s2; s3 oV3s

gm2;N

B1s1B2s2; s3oV3s

gm2;P ZL 10

where ZL is the impedance that can be seen from the sourceterminal of M2 transistor and acts as load for built-inlinearizer block.

The rst term in (10) is due to MP's and MN's third-orderdistortions and cancels out by adjusting the phase and magnitudeof the third-order of non-linearity coefcients (gm3,N and gm3,P) asshown in Eq. (A.22) by varying the bias voltage and sizes of PMOSand NMOS transistors in built-in linearizer. The second term isdue to second-order interaction which mixes the rst- andsecond-order voltages at VN and VP by gm2,N and gm2,P. Based onEqs. (A. 17), (A. 18) and (10), if gm2,N and gm2,P have the samemagnitude and phase, the second-order interaction can bereduced or canceled. The linearity enhancement will be provedby the simulation results in the next section.

4. Results and discussions of UWB-LNA

The whole schematic of the proposed LNA is illustrated in Fig. 5which consists of two CG transistors to achieve high linearity and aCS transistor with second-order Chebyshev lter to achieve wide-band input matching with at power gain and low NF. Since the

proposed LNA aimed for wideband applications, a second-orderChebyshev lter is located in the input port of CS conguration toachieve wideband input impedance matching. The components oflter section are selected to resonate with parasitic capacitance ofM1 at 3 GHz to provide desired input return loss.

A built-in linearizer is placed at the second stage to eliminatethe distortions of M1 drain current and hence the current withfundamental components ow toward the output stage. The built-in linearizer incorporates NMOS (MN) and PMOS (MP) transistorsin CG conguration in order to realize the minimization/cancela-tion of second- and third-order nonlinearities. By stacking MN onthe top of MP, the DC current is reused and hence, the powerconsumption also can be saved. An AC capacitance (CNP) is utilizedto connect the drain of MP and MN. At high frequency (RF), CNP isshorted out and connects the two drain nodes. For much low RFfrequencies, CNP breaks due to its high impedance and separatedthe drain nodes. In Fig. 7(a), the variation of IIP3 is examinedversus different values of CNP capacitance. The result shows thatthe IIP3 variation is only 0.25 dBm which is very small and can bededuced that the built-in linearizer is robust against variations ofCNP. Two inductors are inserted in the drain nodes of main (LN) andauxiliary (LP) to adjust the phase and magnitude of the third-ordernonlinearity coefcient. The effect of LN on the IIP3 characteristic iscarried out in Fig. 7(b). As result shows the simulation is done forthree distinct inductor values which the 0.32 nH is the best one forhighest value of IIP3.

Since CG conguration is linear than CS; thus, built-in linear-izer is formed in CG conguration. The third stage is also used inCG topology to act as a buffer and does not degrade the linearityand BW.

The inductor Lx is placed as a load for rst stage for tworeasons. First, larger Lx is required to minimize NF and maximizegain response in the rst stage output. Second, smaller Lx isneeded in order not to degrade IIP3. In short, this inductor shouldbe chosen to satisfy a good tradeoff among gain, noise gure andlinearity. The following results illustrate the inuence of Lx on thegain, NF and IIP3. As shown in Fig. 8(a), by increasing the Lx, gainresponse of the proposed conguration boosts and simultaneouslythe NF response reduces. Meanwhile, large Lx degrades the IIP3

-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30-100

-80

-60

-40

-20

0

20

Pin (dBm)

Pout

(dBm

)

3 3.5 4 4.5 5 5.5 6

4.85

4.9

4.95

5

5.05

5.1

CNP (pF)

IIP3

(dB

m)

Fig. 7. IIP3 characteristic with respect to variation of (a) capacitor CNP and(b) inductor LN.

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705 701

performance (see Fig. 8(b)). Therefore, Lx is set to be 0.5 nH tominimize noise and to meet the at gain, high IIP2 and IIP3.

Due to the intrinsic high linearity of this LNA, adding aCommon-Drain (CD) output buffer for good output return losswould degrade the linearity performance. Therefore, resistor RLwas sized close to 30- and series LC tank (LL and CL) is adopted toachieve reasonable output return loss. Because of the low value ofRL, simulation shows negligible IIP3 difference when the output ischecked as it is without 30- resistance. Fig. 9 shows the effect ofRL variation on the IIP3, S22 and gain response. As implied fromFig. 9, the RL should be chosen in the marked area (28oRLo32) tosatisfy the tradeoffs among IIP3, gain and S22. Furthermore, asillustrated in Fig. 9, the gain response of the proposed LNA isidentical over the variation of RL and we can deduce that theselected load resistance is only designed to achieve acceptableoutput return loss for ultra-wideband frequency. Although, thevariation of IIP3 over entire RL is 11 dBm, but its variation in themarked zone is approximately zero. Therefore, this indicates thatover the dashed area in Fig. 9, the IIP3 is robust against loadresistance variations.

Ultimately, the effect of parasitic and external capacitances(Cex) is examined on the NF and gain responses. It should be notedthat CtCexCgs. Although, adding Cex causes to increase NF(Fig. 10(a)) and reduces gain from 2 GHz to 8 GHz (Fig. 10(b)),but these deteriorations are very small and thus, can be neglectedin comparison with the improvement of input return loss (see

Fig. 2(a)). Therefore, the Cex should be chosen 0.3 pF in order tosatisfy the tradeoffs between gain, noise gure (NF) and inputreturn loss.

The simulation results of the proposed LNA are shown inFig. 11. As can be seen, the well-matched input reection coef-cient (S11), below 8 dB at the designed frequency band, demon-strates a successful design of band pass lter as the input matchingnetwork. As shown in Fig. 11, a at power gain response withmaximum 10.24 dB from 3.1 to 10.6 GHz can be achieved. The atpower gain response is due to the series and shunt peakinginductor techniques. Fig. 12 depicts that the proposed designfeatures a NF of 0.94.1 dB after linearization in the 3-dB

-30 -20 -10 0 10 20 30

-80

-60

-40

-20

0

20

Pin (dBm)

Pou

t (dB

m)

0 2 4 6 8 10 12 140

2

4

6

8

10

Frequency (GHz)

NF

(dB

) / G

ain

(dB

)

Fig. 8. Effect of Lx variation on the (a) gain and noise gure (NF) and (b) IIP3.

20 22 24 26 28 30 32 34 36 38 40

-10

-6

-2

2

6

1012

RL (Ohm)

S22 (dB)Gain (dB)IIP3 (dBm) Desired area

Fig. 9. Gain, output return loss and IIP3 characteristics with varying RL.

0 2 4 6 8 10 12 14-20

-15

-10

-5

0

5

10

15

Frequency (GHz)G

ain

(dB

)

Without CexCt=0.15 pFCt=0.3 pF

0 2 4 6 8 10 12 140

2

4

6

8

Frequency (GHz)

NF

(dB

)

Without CexCt=0.15 pFCex=0.3 pF

Fig. 10. Effect of Ct on the (a) noise gure (NF) and (b) gain.

0 2 4 6 8 10 12 14-70

-55

-40

-25

-10

515

Frequency (GHz)

Sxx

(dB

)

S21(dB)S11(dB)S22(dB)S12(dB)

Fig. 11. Two-port S-parameters of the LNA.

0 2 4 6 8 10 12 140

1

2

3

4

5

6

Frequency (GHz)

NF

(dB

)

Fig. 12. Noise gure (NF) performance of the LNA.

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705702

bandwidth range. The stability factor (K) of the proposed LNA ismore than 4.6 and resulting in an unconditional stable amplier.The designed LNA power consumption is 17.92 mW from a 1.4 Vvoltage supply. The built-in linearizer is robust versus the varia-tions in the bias voltage of the common-gate transistors. It isworthy mentioned that the maximum IIP3 is 6.8 dBm at 6.3 GHzand is depicted in Fig. 13. In the end, the performance summary ofthe proposed LNA and comparison with other high-linear LNAs areshown in Table 1.

5. Conclusion

A highly linearized UWB LNA has been proposed. A second-order Chebyshev lter is utilized to achieve wideband inputmatching as well as good input return loss. At the second stage,a built-in linearizer which consists of two PMOS and NMOScommon-gate transistors is exploited to absorb both second- andthird-order non-linear currents of LNA over wide frequency range.The proposed built-in linearizer stage used two inductors in thedrain terminals of common-gate transistors to adjust magnitudeand phase of the third-order non-linearity coefcient. A common-gate transistor with shunt peaking inductor technique is utilizedas the third stage to extend the bandwidth, atten and improvethe power gain response in the band of interest. Due to widebandwidth and high linearity, the proposed LNA is a goodcandidate for high-linearity UWB applications.

Acknowledgement

This work was supported by the Basic Research of NRF, Korea(2010-0021768, Development of Dual-Band 24GHz/77GHz CMOSSystem-on-Chip for Advanced Safety Vehicle Radar).

Appendix A

In this section, we plan to nd the kernels of Volterra series ofbuilt-in linearizer circuit in order to explain the linearity

performance of the proposed LNA. The drain current of the CGtransistors shown in Fig. 14 can be expressed as the followingVolterra series:

VC A1 s1 V sA2 s1; s2 V s2A3 s1; s2; s3 V s3 A:1

VN B1 s1 V sB2 s1; s2 V s2B3 s1; s2; s3 V s3 A:2

VP C1 s1 V sC2 s1; s2 V s2C3 s1; s2; s3 V s3 A:3By applying KCL at VN, VP, and VC nodes, the equations are

established as follows:

idN idpVCVNrO;N

VCVPrO;P

VCVSZSs

VCZCs

0 A:4

idNVNVCrO;N

VNVPZNPs

VNZLs

0 A:5

idPVPVCrO;P

VPVNZNPs

VPZPs

0 A:6

where ZL rO;M2 sLL RL1gm;M2 rO;M2 sCgs;M2 rO;M2RL s2cgs;M2 LL LNZs rO 1L2Zs'

Zs' 1

sCgs;M1Cex 1

sC1sL2 J

1sC1

sL1

ZP LP J 1=sCp and Cp is the parasitic capacitances at source of thePMOS transistor.

Zc s 1=sCc and Cc is the parasitic capacitances at node VC.where id,N and id,P are the small-signal currents moving into the

common-gate transistor sources.

idN gm1;N VC gm2;N VC 2gm3;N VC 3

gm1;NVCgm2;NVC2gm3;NVC3

A:7

idP gm1;PVCgm2;PV2Cgm3;PV3C A:8The rst-order Volterra kernel can be derived by substituting id,

N and id,P with their gm polynomial.

gm1;NA1 s gm1;PA1 s A1sB1s

rO;NA1sC1s

rO;PA1s1

ZSsA1sZCs

0

A:9

gm1;NA1 s B1sA1s

rO;NB1sC1s

ZNPsB1sZLs

0 A:10

gm1;PA1 s C1sA1s

rO;PC1sB1s

ZNPsC1sZPs

0 A:11

At high frequency (band of interest, i.e. 3.110.6 GHz), theimpedance of ZNP(s) which includes capacitance CNP is negligible;

-30 -20 -10 0 10 20 30

-80

-60

-40

-20

0

20

Pin (dBm)

Pou

t (dB

m)

1st order3rd order

Fig. 13. IIP3 characteristic of the LNA.

Table 1Comparison of the simulation results of the proposed LNA and otherpublished works.

Ref. [10] [11] [16] [21] This work

Tech (mm) 0.18 0.13 0.13 0.18 0.13Freq (GHz) 0.9 3.110.6 3.66 310 3.110.6S21 (dB) 15 19.571.5 14 14.515.3 10.24S12 (dB) NA o70.6 o53.5 NA o31.7NF (dB) 1.76 13.9 2 NA 0.94.1Power (mW) 6.75 4.1 2.43 4.3 17.92IIP3 (dBm) 12.45 4.56 10.5 3.43 6.8

Fig. 14. Built-in linearizer circuit for high frequency Volterra series analysis.

H. Rastegar, J.-Y. Ryu / Microelectronics Journal 46 (2015) 698705 703

thus we can say that B1(s)C1(s). By utilizing the above-mentioned assumption and after complex calculation, the preciseA1 and B1 results are as follows:

A1 s ZL s JZP s rO;N JrO;P

Ks A:12

where

K s Zs s 1gm;Ngm;P

rO;N JrO;P ZL s JZP s rO;N JrO;P 1ZssZCs

B1 s ZL s JZP s

ZL s JZP s rO;N J rO;P 1gm;N gm;P rO;N J rO;P

A1s A:13

At the second step, we want to nd the second-order VolterraSeries Kernels as following procedure:

gm1;NA2 s1; s2 gm2;NA1 s1 A1 s2 gm1;PA2 s1; s2

gm2;PA1 s1 A1 s2 A2 s1; s2 B2 s1; s2

rO;NA2 s1; s2 C2 s1; s2

rO;P

A2 s1; s2 0ZS s1 s2

A2 s1; s2 ZC s1 s2

0 A:14

gm1;NA2 s1; s2 gm2;NA1 s1 A1 s2 B2 s1; s2 C2 s1; s2

ZNPs1 s2

B2 s1; s2 A2 s1; s2 rO;N

B2 s1; s2 ZL s1 s2

0 A:15

gm1;PA2 s1; s2 gm2;PA1 s1 A1 s2 C2 s1; s2 B2 s1; s2

ZNPs1 s2

C2 s1; s2 A2 s1; s2 rO;P

C s1; s2 ZP s1 s2

0 A:16

By the assumption that ZNP(s1s2) is negligible at the fre-quency band we nd the following results:

A2 s1; s2 1=2 gm2;Ngm2;P

rO;N JrO;P

ZS s1 s2 A1 s1 A1 s2 A2 s1; s2 K s1s2 K s1; s2

A:17

where

A2 s1; s2 1=2Z12 s1s2 A1 s1 A1 s2

ZS s1 s2 ZL s1 s2 ZP s1 s2 rO;NrO;P

gm2;Ngm2;P

rO;N JrO;P

gm2;NrO;NZP s1 s2 gm2;PrO;PZL s1 s2 rO;NrO;P

K s1; s2 ZNPs1 s2Zs s1; s2

Z1 s1; s2 Z2 s1; s2 rO;NrO;P

rO;NZL s1 s2

rO;PZP s1 s2

ZC s1s2 JZs s1s2 1gm1;NrO;N

rO;PZP s1 s2 1gm1;PrO;P rO;PZL s1 s2

where

B2 s1; s2 1=2Z12 s1s2 A1 s1 A1 s2

ZL s1 s2 ZL s1 s2 ZP s1 s2 rO;NrO;P

gm2;NrO;N ZP s1 s2 rO;P1 Zs s1 s2 ZC s1 s2

Zs s1 s2 gm2;PrO;P 1gm1;NrO;N gm2;NrO;N1gm1;PrO;P

It is noteworthy to mention that if we apply the assumption(ZNP(s1s2) is zero at high frequency) to equations (A. 17) and (A.18), then B2 (s1, s2), A2 (s1, s2) and K (s1, s2) parameters havenegligible value and hence, drop out. Due to the circuit duality, theC2 (s1,s2) can be found by interchanging the element notation in B2(s1,s2). By the above explanation and precise observation into Eq.(A. 18), we can understand that if gm2,N and gm2,P have the samemagnitude and phase, the second-order non-linearity of the circuitcan be canceled.

Finally, the third-order Volterra Series Kernels can be found asfollows:

gm1;NA3 s1; s2; s3 gm2;NA1 s1 A2 s2; s3 gm3;NA1 s1 A1 s2 A1 s3 gm1;PA3 s1; s2; s3 gm2;PA1 s1 A2 s2; s3 gm3;PA1 s1 A1 s2 A1 s3

A3 s1; s2; s3 B3 s1; s2; s3 rO;N

A3 s1; s2; s3 C3 s1; s2; s3 rO;P

A3 s1; s2; s3 Zs s1s2s3

A3 s1; s2; s3 Zc s1s2s3

0 A:19

gm1;NA3 s1; s2; s3 gm2;NA1 s1 A2 s2; s3 gm3;NA1 s1 A1 s2 A1 s3

B3 s1; s2; s3 C3 s1; s2; s3 ZNP s1s2s3

B3 s1; s2; s3 A3 s1; s2; s3 rO;N

B3 s1; s2; s3 ZL s1s2s3

0 A:20

gm1;PA3 s1; s2; s3 gm2;PA1 s1 A2 s2; s3

gm3;PA1 s1 A1 s2 A1 s3 C3 s1; s2; s3 B3 s1; s2; s3

ZNP s1s2s3

C3 s1; s2; s3 A3 s1; s2; s3 rO;P

C3 s1; s2; s3 ZP s1s2s3

0 A:21

We assume ZNP(s1s2s3)0 at RF frequency and then ndthe A3(s1s2s3) and B3(s1s2s3) as follows:

B3 s1; s2; s3 ZL s1s2s3

ZC s1s2s3 JZs s1s2s3 A3 s1; s2; s3 A:23

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B2 s1; s2 ZL s1 s2 JZP s1 s2 Zcs1 s2 JZs s1 s2 1=2 gm2;Ngm2;P

rO;N JrO;P

ZS s1 s2 A1 s1 A1 s2 B2 s1; s2 K s1s2 K s1; s2

A:18

A3 s1; s2; s3 Zs rO;N JrO;P

gm2;Ngm2;P A1 s1 A2 s2; s3 1=6 gm3;Ngm3;P A1 s1 A1 s2 A1 s3 K s1s2s3

A:22

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