1 san jose state university department of electrical engineering ee 166 project spring 2003 phase...
Post on 20-Dec-2015
218 views
TRANSCRIPT
1
San Jose State UniversityDepartment of Electrical Engineering
EE 166 ProjectSpring 2003
Phase Frequency Detector (PFD)
Prof. David Parent
Group Members: Marcella GrantRobert ShenHan DuongJeremiah Martin
2
OUTLINE
Introduction Specifications Design Flow Results Conclusion
3
What is a PFD?
Component used in a PLL that compares two signals.Evaluates Phase and Frequency The output voltage gives the information of the phase and frequency differences of two signals.
4
Specifications
Process: AMI06Frequency: ≥ 200 MHzPower: ≤ .25 WattsDuty Cycle: 50%VDD: 5 VInputs: 2Outputs: 2
5
Schematic of PFDPFD Charge
Pump/LPF VCO
%N
OUTPUTINPUT
PLL
Q
QSET
CLR
D
Q
QSET
CLR
D
UP
DOWN
INPUT
FEEDBACK
6
Design Flow
PostExtractionSimulation
Verification
DesignComplete
Testbench
HandCalculations
SchematicCapture
Layout
DRCCircuit
ExtractionLVS
7
Transistor Level of PFD
8
Test Bench
9
Layout View
10
LVS Report
11
Transient Analysis
12
DC Analysis
13
Results
Parameters Specifications Design Results Meet Specs.?
Frequency ≥ 200 MHz 333 MHz Power ≤ .25 Watts 2mW Duty Cycle 50% 50% VDD 5V 5V Prop. Delay ≤ 5ns .5ns
14
Conclusion
Successfully Designed and Implemented PFD for our PLL project.Met all Specifications.