1 sequential logic networks i. motivation & examples output depends on current input and past...

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Sequential logic networks

I. Motivation & Examples

Output depends on current input and past history of inputs. “State” embodies all the information about the past needed to predict

current output based on current input.

– State variables, one or more bits of information. If the current State of the circuit is known at time t, what is the state of

the circuit at time (t+1)

Answer: the next state depends on current state and input

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State table

– For each current-state, specify next-states as function of inputs

– For each current-state, specify outputs as function of inputs State diagram

– Graphical version of state table


Describing sequential circuit

Example 1: TV channel control •Let the channel # represent the state of the circuit•Input are up/down on the channel control

1 2 3 4 99…u u u u u

d d d d d

on

u: up d: down

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Example 2: A sequential process that inputs an n-bit binary string and outputs 1 if the string contains an even number of 1’s

1 (final output) 01111 SLN

0 (final output) 0111 SLN

What represents the state of the circuit?• Case1:

State as the number of 1’s read so far (possibly infinite # of states)

•Case 2: Two states E and O•E (even): if the # of 1’s read so far is even•O (odd) if the # of 1’s read so far is odd

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Example 2: State Diagram for Case 1

1 2 3 2n…01/0 1/1 1/0 1/1 1/0

41/1

0/0 0/00/1 0/1 0/1 0/1


Input Output

OE

1/0

0/11/1 0/0

Input Output

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OE

1/0

0/11/1 0/0

Input Output

•Better design•Has less states

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Example 3: Discuss sequential n-bits comparator•Compare two n-bits numbers X=[Xn-1, …, X0], Y=[Yn-1, …, Y0]•Output 1 if X>Y•Use the basic 1-bit comparator designed in class

Xn-1 Xn-2 Xn-3 X2 X1 X0

Shift right

1-bitComparator

Ci

Yn-1 Yn-2 Yn-3 Y2 Y1 Y0

Shift rightFi

Xi Fi-1

Yi

Operation controlled by a clock to decide:

.when to shift input data

.when output Fi is stable

...

...

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Example 4: Discuss sequential n-bits adder•Add two n-bits numbers X=[Xn-1, …, X0], Y=[Yn-1, …, Y0]•Output S=X+Y where [Sn,Sn-1,…,S0]•Use the basic 1-bit adder with carry in and carry out

Xn-1 Xn-2 Xn-3 X2 X1 X0

Shift right

1-bitFull adder Ci

Yn-1 Yn-2 Yn-3 Y2 Y1 Y0

Shift rightCi

Xi Ci-1

Yi

Operation controlled by a clock to decide:

.when to shift input data

.when output are ready

Shift rightSn-1 Sn-2 S2 S1 S0...

...

...

Sn

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Clock signals Sequential circuit are controlled by a clock signal Very important with most sequential circuits

– State variables change state at clock edge.

II. General Representation

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General diagram of sequential circuit Sequential circuit are controlled by a clock signal Very important with most sequential circuits

– State variables change state at clock edge.


SLN

Memory components

Inputi0i1…in

Outputo0o1…omCurrent states Next states

State variables: s0,s1, …sk

Feedback

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Some important questions How to represent the states of a sequential circuit? How to memorize the (current and next) states? How to determine the next of the circuit? How to determine the outputs

– as a function F(state) of current state only?

– as a function F(input,state) of both input and current state?

The concept of STATE is very important


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Memory component

How do we represent the states? Memory component are used as state variables

– Goal: Memorize the current state of the circuit

– How are memory components implemented? Latch, Flip-flop are 1-bit memory component


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Bistable element The simplest sequential circuit Two states

– One state variable, say, Q (QN or Q_L the complement of Q)

HIGH LOW

LOW HIGH

III. Basic memory component

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Bistable element

The simplest sequential circuit Two states

– One state variable, say, Q

LOW HIGH

HIGH LOW


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Bistable element: Analog analysis

Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V


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2.5 V 2.5 V

2.5 V 2.5 V


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2.5 V

2.5 V 2.5 V

2.0 V

2.0 V 4.8 V

2.5 V2.51 V4.8 V 0.0 V

0.0 V 5.0 V


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Bistable element: summary

If (Q=0), then input to Not gate 2 is 0

==> Output of Not gate 2 is 1 (Q_L =1)

==> The input of Not gate 1 is 1, so output of Not gate 1 is 0

==> Stable output (Q=0) and (Q_L = 1) If (Q=1), then input to Not gate 2 is 1

==> Output of Not gate 2 is 0 (Q_L =0)

==> The input of Not gate 1 is 0, so output Not gate 1 is

==> Stable output (Q=1) and (Q_L = 0)


1

2

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S-R Latch….

How to control it?

– Screwdriver

– Control inputs S-R latch


Contradiction!!!!

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S-R Latch….


Set operation: SR 00 ----> 10, set the device output to Q=1 regardless of current value of Q Reset operation: SR 00 ----> 01, set the device output to Q=0 regardless of current value of Q

Hold operation: SR 10 ----> 00 or 01 ----> 00, Device output are the same as last output values

•Only one input value changes •Possible input changes:

•SR: 00 ---> 01 ---> 00 ---> 10 ---> 00 ….•Input SR = 11 is not allowed ( Both NOR gates output 0, i.e Q=Q’=0 )

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S-R latch operation


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S-R latch timing parameters

Propagation delay Minimum pulse width


Progation delay Minimum time to maintain signal at 1

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S-R latch symbols

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S-R latch with enable


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Sequential network architecture (revisited)


Outputo1

omSLN

......

Inputi1

in

M1...

Mk

Components Mi are latches/Flip flops

Operation rules:•Memory components Mi must be in stable state before input changes•Only one input of the component Mi can change at a time

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Charcteristics equation of S-R latch


Definition: The characteristic equation specifies a flip-flop next state as a function of its current state and inputs

Notation: Let q represent the current state of the flip-flop and Q its next

S R q Q

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 10011 X

Q=q

Q=0

Q= 1

XNot allowed

Hold

ResetSet

Characteristics tableCharacteristics table

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Charcteristics table (other representation)


S R Q

0 00 11 01 1

q 01X

Q=qQ=0Q= 1Not allowed

HoldResetSet


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Charcteristics equation of S-R latch


Use the characteristics table to get an excitation map of the flip flop

S R q Q

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 10011 X

Q=q

Q=0

Q= 1

X


SRq

0

1

00 01 11 10X

X

1

11

Q

Use K-map method to derive the characteristics equation:

Q = S + R’q

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Excitation table of SR flip flop


The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> Q) from current to next state

Types of transitions: q --->Q 0 ---> 00 ---> 11 ---> 01 ---> 1

Excitation table of S R latch

q ---> Q S R0 ---> 00 ---> 11 ---> 01 ---> 1

0 X1 00 1X 0

0 0 to holdcurrent value

0 1 to resetQ=0

OR


1 0 to set Q=1

OR

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JK Flip- Flop


Recall: In SR flip flop, both input S, R cannot be 1 (SR=11)

This restriction is removed in a JK flip flop. The behavior of the JK flip flop is as follows:

J K q Q

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 10011 1

Q=q

Q=0

Q= 1

0Q = Q’ (Toggle)

Hold

ResetSet


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Charateristics of JK flip flop (other representation)


C J K Q

1 0 01 0 11 1 01 1 1

q 01q'

Q =qQ =0Q = 1Q = q’ (Toggle)

HoldResetSet


Characteristics table Characteristics table ( Clocked JK flip flop )

0 x x Disabled

J K Q

0 00 11 01 1

q 01q'

Q =qQ =0Q = 1Q = q’ (Toggle)

HoldResetSet

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Charcteristics equation of Jk Flip flop




JKq

0

1

00 01 11 101

0

1

11

Q

Use K-map method to derive the characteristics equation:

Q = Jq’ + Kq

J K q Q

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 10011 1

Q=q

Q=0

Q= 1

0Q = Q’

0

0 0

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Excitation table of JK flip flop





q ---> Q J K0 ---> 00 ---> 11 ---> 01 ---> 1

0 X1 XX 1X 0


0 1 to resetQ=0

OR


1 0 to set Q=1

OR

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q ---> Q J K0 ---> 00 ---> 11 ---> 01 ---> 1

0 X1 XX 1X 0


0 1 to resetQ=0

OR


1 0 to set Q=1

OR

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JK Flip flop Symbols


J

K

Q

QN

J

K

Q

Q

J

K

Q

QN

CK

J

K

Q

QN

CK

Clocked JK Flip flop

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D Flip- flop ( Delay flip flop)


This flip flop has only one control input. The D flip flop simply retains its input between clock pulses

D q Q

0 00 11 01 1

0 011

Q=d


C D Q

1 0 1 1

Characteristics table Characteristics table ( Clocked D flip flop )

0 x

0 1 Q=dDisabled

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Charcteristics equation of D Flip flop




Characteristics equation:

Q = D

D q Q

0 00 11 01 1

0 101

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D Flip flop Symbols


D Q

QN

D Q

Q

D Q

QN

CK

D Q

QN

CK

Clocked JK Flip flop

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D latch


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D-latch operation


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D-latch timing parameters Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge)


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Edge-triggered D flip-flop behavior

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Edge-triggered D flip-flop behavior


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D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK)


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IV. Counters

A counter is a sequential-circuit that generates a predetermined number sequence over and over again

A counter can be used as

– a digital clock

– special sequence generator

– program counter

– pulse counter

Definitions

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Examples

IV. Counters

0 1 2 3 4 5 6 7 8 9

0 1 2 3 4 5 6

00 01 11 10

0000 0001 0011 0010 0110 0100

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IV. Counters

Counters are often implemented by Flip flops. They are – synchronous if all flip flops are clocked by the same signal– ripple (asynchronous) individual flip flop are clocked at different

times Counters may be classified by other characteristics:

– mod N counter or divide-by- N counter, if counter has N distinct states (State = a number of the counted sequence)

– by the number of fli flops in the counter: n bit counter– Other types of counter:

binary up (or down) counter : successive states represent an increasing binary count

00 --> 01 --> 10 --> 11 --> 00 …….. gray code binary counter

00 --> 01 ---> 11 ---> 10 ---> 00

Types of counters

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IV. Counters

Problem Statement

Design a sequential device to generate the sequence 0, 1, 2, 3 over and over again

There are 4 distinct states (divide-by-4) counter Encode the four states as follows;

0 encoded by 00

1 encoded by 01

2 encoded by 10

3 encoded by 11 Represent each binary bit of a code by a flip flop (in this example, let

us use JK flip flops to design the counter)

Intuitive Design of a counter

00 01 10 11

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IV. Counters

Flip flop 0 changes state at every clock pulse

Flip flop 1 changes states every two clock pulses

Intuitive Design of a counter00

01

10

11

00

00

01

10

11

Flip flop 1 Flip flop 0

State transition flip flop 0 State transition flip flop 0

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IV. Counters

Design using JK flip flops for states 0 and 1 of the counterIntuitive Design of a counter

J

K

Q

QN

CK

J

K

Q

QN

CK

1

1

EN

S0S1

S1S0 : 00 --> 01 --> 10 --> 11 --> 00 …….

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IV. Counters

Design using JK flip flopsIntuitive Design of a 4 bit binary counter

S3S2S1S0 : 0000 --> 0001 --> 0010 --> 0011 --> 0100 --> 0101 … --> 1111 --> 0000

There are 16 states design requires four flip flops Synchronous design, all flip flops clocked by the same signal

S0 Changes state (toggles) every clock pulse S1 Changes state (toggles) when S0 = 1 S2 Changes state (toggles) when S1=1 and S0 = 1 S3 Changes state (toggles) when S2=1, S1=1 and S0=1

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IV. Counters

Design using JK flip flopsIntuitive Design of a 4 bit binary counter

J

K

Q

QN

CK

J

K

Q

QN

CK

J

K

Q

QN

CK

J

K

Q

QN

CK

EN

S3 S2 S1 S0

1

1

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State-machine structure (Mealy)

typically edge-triggered D flip-flops

output depends onstate and input

V. Sequential network design

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State-machine structure (Moore)

output dependson state only

typically edge-triggered D flip-flops


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Q

Q’C

D Q

Q’C

S

R

Q

Q’C

J

K

Characteristic Table

S R q Q0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 1 0 0 1 1 -- --

J K q Q0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 1 0 0 1 1 1 0

D q Q0 0 0 1 1 0 1 1

0 0 1 1

Characteristic Equation Q = D

SRq 00 01 11 10

0

1 1

d

d 1

1

Q = S + R’q

JKq 00 01 11 10

0

1 1

1

1

1

Q = Jq’ + K’q

Transition Table(Excitation Table)

q Q D0 0 0 1 1 0 1 1

0 1 0 1

q Q S R0 0 0 1 1 0 1 1

0 d 1 0 0 1d 0

q Q J K0 0 0 1 1 0 1 1

0 d 1 d d 1d 0

D Flip flop S-R Flip flop J-K Flip flop

q : Current state

Q : Next state


Flip Flop : summary

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Characteristic table : For each input and state combination, define the next state of the flip flopCharacteristic equation: Define the next state (Q) as a function of current state and input to the flip flopTransition table (excitation table): For each transition type, define the inputs that cause the transition

V. Sequential network designFlip Flop : summary

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Synchronous state machine : Major design steps

Step 1: Start from state diagram or word description

Step 2: Construct a State/Output table

Moore machine: one output per state (one output column)

Mealy machine: One output per state and for each input combination (one output column per input combination)

Step 3: Reduce the number of states in State/output table by removing redundant states (a state is redundant if for the same input combinations) it has the same next state and output as another state.

Step4: Encode the states in binary (for n states, log2n bits are required). Each bit in the code represents a flip flop.

Step5: Substitute corresponding binary codes to states in the State/Output table

Step6: Separate the state table into flip flop next state maps (one map for each bit or flip flop)

Step7: Use the flip flop next state map to derive flip flop excitation maps (this step depends on the type of flip flop used in the design)

Step8: Use the flip flop excitation maps to determine excitation equations for the flip flop (these equations define the input logic of the flip flop)

Step 9: Use the State/Output table to define the output logic circuit

Step10: Draw the circuit, including flip flop, flip flop input circuits and output circuit.

V. Sequential network designMajor design steps

1 sequential logic networks i. motivation & examples output depends on current input and past...

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