1 STATIC pre-CDR Peer Review, May STATIC pre-CDR Peer Review 2011 May11 Instrument Lead: James McFadden Electrical: Ken Hatch, Rick Sterling, Dorothy Gordon, Chris Tiu, Peter Berg, Selda Heavner Mechanical: Greg Dalton, Greg Johnson, Paul Turin Testing: Onno Kortmann, Mario Markwordt 2 STATIC pre-CDR Peer Review, May Overview IntroductionMcFadden Requirements Status at PDR Design Changes Front End ElectronicsHatch Digital ElectronicsSterling FPGAGordon Carbon FoilsKortmann Mechanical Design Dalton Schedule/Wrap UpMcFadden 3 STATIC pre-CDR Peer Review, May Summary of Science Requirements STATIC Science Objectives and Requirements Thermal Ionospheric Ions ( eV) - >1 eV due to RAM velocity (~4 km/s), peak flux at ~4-5 eV - densities of 10 5 /cm 3 require both attenuators - densities of /cm 3 require single attenuator - resolve 3D angle distribution requires ~10-20 deg sensor resolution - resolve parallel temperature down to ~0.1 eV requires ~1 eV Suprathermal Ion Tail Conics (5-100 eV) - >5 eV ions with escape velocity - expected fluxes similar to Earths aurora - as RAM ions drop below ~10 2 /cm 3, switch off attenuators Pick-up Ions (100 20,000 eV) - tenuous flux may require long integrations - flux generally maximum perpendicular to solar wind V and B - optimal measurements may require rotation of APP - instrument should not saturate in magnetosheath 4 STATIC pre-CDR Peer Review, May STATIC Characteristics STATIC Geometric Factor Nominal analyzer cm 2 -sr-eV/eV With grid and TOF efficiencies : ~0.2 x = 3x10 -3 cm 2 -sr-eV/eV With electrostatic attenuator only 3x10 -4 cm 2 -sr-eV/eV With mechanical attenuator only 3x10 -5 cm 2 -sr-eV/eV With both attenuators 3x10 -6 cm 2 -sr-eV/eV STATIC Dynamic Range Energy flux range 32 in preamp dynamic range (>30 dB) where signals are not saturated above the noise threshold. A minimum dynamic range would be ~20, and would introduce some timing errors for the largest signals. 0 1e7 4e7 Gain Pulse Height Dist. H+O+ 14 STATIC pre-CDR Peer Review, May Preamp Dynamic Range Prototype preamp had inadequate dynamic range (~8) to maintain timing accuracy over the range of input pulse amplitudes. It also had an incorrect gain, and was non- linear at small signals due to minimal idle current. 1)Preamp-TDC noise threshold is ~30 mV (tests with digital board indicate ~15 mV) 2)Maximum preamp output pulse voltage w/o saturation is ~3 V Therefore a preamp linear dynamic range of ~100 is possible 3)To keep the preamp power low, the DC transistor CE current should be minimized. 4) However, event signal currents can be much larger than the DC current. 5) Since the transistors frequency dependent gain depends strongly on CE current, gain changes with input signal size will change the shape of the output pulse 7) CFD timing accuracy depends on maintaining constant shape for the preamp output A trade was needed between minimizing DC current (power) and preamp linearity Two preamp solutions are being evaluated. The first solution involves only changes to the first transistor stage to make it more linear and shape the pulse. This provides a factor of ~20 in dynamic range. The second solution involves a more extensive preamp redesign and should provide an additional factor of 2 in dynamic range and less timing drift w/ amplitude. 15 STATIC pre-CDR Peer Review, May EM Preamp Test Data 1 16 STATIC pre-CDR Peer Review, May EM Preamp Test Data 1 17 STATIC pre-CDR Peer Review, May Changes to Preamp Change bias current in 1 st stage to higher value to improve linearity. Add input filter to obtain better input stage response. Improve dynamic range of output stage. 18 STATIC pre-CDR Peer Review, May Original preamp design Limited dynamic range Huge current swing in Q1 New Input Stage Design (for better linearity) 20 STATIC pre-CDR Peer Review, May Alternate preamp design Need temperature compensation, possibly series diodes for V_Tcomp (feeds all 4 stages) Input slowing network Wide dynamic range gain stage (for improved dynamic range) 21 STATIC pre-CDR Peer Review, May EM TDC Development TDC modifications from prototype to EM 1)New Layout in PADS 2)Inter-board coaxial connections with Huber-Suhner MMBX connectors 3)New 21 pin TDC to digital board connectors selected 4)Part changes to accommodate NASA specs. 22 STATIC pre-CDR Peer Review, May EM TDC-CFD Modified Schematic Testing uncovered . 1)ADC inputs and reset lines floating when not hooked up to digital board 2)Timing comparator in unknown state when latched (made testing difficult) 3)Race condition was marginal for threshold enable of timing comparator latch 4)Start/Stop timing jitter (~1ns) when Stop signal was ~15-17 ns after Start. 5)Inconsistent TDC timing capacitor discharge circuit design Fixes 1)Pull down resistors will be added to flight TDC layout 2)Threshold voltage introduced into timing comparators to assure latched signal is low 3)Timing comparators 2 ns delay line chips replaced with 3 ns delay line chips 4)Will move threshold flip-flop closer to threshold comparator, add power line filtering, change the ground plane 5)Determined the proper discharge RC circuit for holding timing capacitor at ground. Other Testing 1)Linearity of TOF timing 2)Preamp-TDC timing drift with input signal amplitude (1-1.5 ns over dB) 3)Delay requirements between pulse and ADC latch as a function of TOF time. 23 STATIC pre-CDR Peer Review, May TIMED schematic 24 STATIC pre-CDR Peer Review, May TDC original design 25 STATIC pre-CDR Peer Review, May EM TDC Test Data 1 26 STATIC pre-CDR Peer Review, May EM TDC Test Data 15 ns delay 27 STATIC pre-CDR Peer Review, May EM TDC Test Data 17 ns delay 28 STATIC pre-CDR Peer Review, May EM TDC Test Data 18 ns delay 29 STATIC pre-CDR Peer Review, May EM TDC Test Data 20 ns delay 30 STATIC pre-CDR Peer Review, May EM TDC Test Data 40 ns delay 31 STATIC pre-CDR Peer Review, May Changes to TDC Board Add pull-ups and pull-downs for easier testing (Establishes high or low for open pin). Copy best reset circuit to all resets. (resets charge on integrating capacitors.) Change CFD delay chips to 3 ns to provide margin on race condition for threshold enable of timing comparator latch Make changes to stop timing discriminators to isolate noise. Redo layout to isolate ground and power associated with stop discriminator. Added resistors R636 through R644 (places board in known state when pin is disconnected) 33 STATIC pre-CDR Peer Review, May Use this circuit for all resets 34 STATIC pre-CDR Peer Review, May TIMED schematic U212 U203-2 U203-1 Replace 2 ns delay chips with 3 ns 35 STATIC pre-CDR Peer Review, May TDC EM Layout (U212 traces cross start section to get to U203) 36 STATIC pre-CDR Peer Review, May Added part Moved connection Changes to stop timing discriminato r 3 ns delay chips 37 STATIC pre-CDR Peer Review, May New Layout U203U212 (U203 and U212 are close) 38 STATIC pre-CDR Peer Review, May Isolated ground New Layout 39 STATIC pre-CDR Peer Review, May EM Digital Board Development Modifications from prototype to EM 1) Daughter Card Added for FPGA 2) A few part changes for reduced power consumption or part consistency. 3) Flight mating connectors: MDM21 mating to TDC, HDLP connectors for daughter card., Huber+Suhner test pulse connectors. 40 STATIC pre-CDR Peer Review, May EM Digital Board Tests Completed 41 STATIC pre-CDR Peer Review, May Static Digital Board Testing Anode/PreAmp-TDC-Digital--MISG GSEOS End to end testing on the bench. 42 STATIC pre-CDR Peer Review, May Test Setup End to End Testing with Controllable Test Pulses Pulses generated on command at FPGA in Digital Board Pulses can be controlled in frequency, amplitude and delay Pulses Sensed at Anode and results sent through entire chain 43 STATIC pre-CDR Peer Review, May Test Pulse Design Modifications Modified circuit design to minimize ringing, minimize over/undershoot, yet have fast (1 ns) fall time. Trimming resistors, added diode. 44 STATIC pre-CDR Peer Review, May Issue: Missing Signal Discovered missing signal. Pulse clearly seen at input to Digital Board and via on backside of FPGA. Not being received at FPGA. Jumpered to another pin to move forward. Will replace FPGA and retest. Flight boards use CCGA. 45 STATIC pre-CDR Peer Review, May Sample Test Data 1 Sample screen shot with counts which are checked against Test Pulse settings. Example: Start-Stop Time. 46 STATIC pre-CDR Peer Review, May Sample Test Data: Rates Display of pulse count rates. Easily compared with Test Pulse frequency. 47 STATIC pre-CDR Peer Review, May EM Digital Board Testing TBD EM Digital Board Tests To Be Done: * Voltage Margin Test. Vary voltages +/- 10% at ambient, hot (+65C) and cold (- 35C). * Parts Stress Analysis. Use GSFC spreadsheet/analysis to determine stress on each individual component in design. 48 STATIC pre-CDR Peer Review, May Clean Room for sensor assembly 49 STATIC pre-CDR Peer Review, May Sink for Carbon Foil Mounting 50 STATIC pre-CDR Peer Review, May New Cal Chamber being constructed 51 STATIC pre-CDR Peer Review, May Maintaining old Cal Chamber