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Terminations

Chris Allen (callen@eecs.ku.edu)

Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm

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Termination resistorsPurpose

Reduce transmission-line reflectionsComplete circuit for ECL and GaAs outputs

IssuesReflection characteristicsCurrent / power loadingComponent placement / routing issuesResistor type, packaging

OptionsEnd termination (L 0)

Source termination (S 0)

Other termination schemesDifferential line termination

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End termination

ECL output driver can sink/source 50 mA

GaAs (GigaBit Logic) can sink/source 60 mA

both could drive two 50- loads

driverofcurrentoutputmaximumexceednotmust

R

VVI

R

VVI

T

TTLOLO

T

TTHIHI

mA4I,mA24

50

28.0I LOHI

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End terminationFanout – How many inputs can one driver support?

not limited by the input current ( 500 A) per input current available is 50 mA – 24 mA = 26 mA

driver output term available

based on this analysis ECL or GaAs could drive over 50 inputs

26 mA / 0.5 mA = 52 inputs

instead fanout is limited by the capacitance (3 pF to 5 pF per input)maximum fanout is about 10 inputs

capacitance slow the signal rise time (RC circuit)

rise time of RC circuit is, CZ1.1T oRCr

2r

2RCrr TTtotalT

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End terminationDaisy-chain layout – one termination (only) at the far end

Issues – stub connections to inputs must be short (> l / 6)so that each gate input appears as an open circuit

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End terminationDaisy-chain layout

termination resistor should be at the far end of the transmission line to minimize reflections

or

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End terminationAlternative layout option with end terminationThe driver ‘sees’ a single

50- transmission line that is properly terminated

The challenge is fabricating 100- lines

For CMOS and TTL technologyA 50- termination may exceed the driver’s current capacity

To accommodate CMOS and TTL, can increase Zo and R so that the

current required is within the driver’s ability

Also, can reduce power dissipation in termination resistor with AC coupling

During transient (Tr), capacitor looks like

short circuit Xc = Tr/C

if Xc << RT, then reflection is small

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End terminationSimilar approach could also be used with ECL / GaAs

Reduce power dissipation in termination resistor with AC coupling

For differential lines in CMOS and TTL technologyThe termination pair could be capacitively coupled, taking advantage

of the inherent DC-balance

R1 = 50

R1 + R2 >> 50

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Source terminationSource (or series) termination (S = 0)

Another approach to reduce reflections is to focus on the source endAssumption – far end impedance, ZL >> Zo (~ open circuit) L ~ 1

For RO + RS = Zo, S = 0

RO is driver resistance

Issues –

Only valid for driving far-endload (intermediate positionsdo not see full transitionin single step) no daisy chaining

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Source terminationWhat is the driver’s output impedance? (CMOS, TTL, ECL, GaAs)

Digital circuit output stages have output resistances that depend on logic state

Family Ro(HI) Ro(LO) Rin Cin Fanout

CMOS 28 10 5 M 10 pF ~ 5

TTL 50 8 10 k 5 pF 20 to 30

ECL 6 8 50 k3 pF to

5 pF~ 10

GaAs 8 to 12 200 10 k1.5 pF to

5 pF~ 10

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Source terminationWhy aren’t Ro(LO) higher for ECL and GaAs?

Output transistor is not biased to cutoff mode

Ro ~ 1/slope

~ 60

~ 600

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Source terminationEquivalent circuit for analyzing output

For RO(HI) RO(LO)

cannot find RS that

Satisfy

RO + RS = ZO for

both HI and LO cases

For Zo = 50 , CMOS Rs ~ 30 ECL Rs ~ 40 GaAs Rs ~ 40 (but a big S when LO)

However to pull down the output for ECL and GaAs, a pull-down resistor is needed as well

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Source terminationHow to determine value for Rpd?

First, find the current, Ipd, required to

pull the voltage level down on the transmission line when the output goes low

V ~ 1 V 1 V/(2 50 ) = 10 mA Ipd 10 mA

Second, during HI to LO transition, think of the trace as a charged capacitor

Enforce these two conditionsfor VOH = -0.8 V, VEE = -5 V

Rs = 40 , Zo = 50

OLOHo

pd VVVwhere,Z2

VI

2 Zo due to open transmission line (L = +1)

ospd

EEOHpd ZRR

VVI

42090RmA1090R

2.4

Z

5.0

ZRR

VV

pdpd

oospd

EEOH

Rpd 330

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Source terminationDisadvantages of source termination

The source termination scheme produces the desired output voltage only at the far end of the transmission line

Therefore daisy-chaining is not permittedsince gates attached midline will see irregular waveforms

Therefore all receiving gates must be clustered at the end of the line

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Source terminationCan drive more than one series terminated line, however must not exceed the max output current limit

Driving two or more lines required a lower pull-down resistor value

Drawing more quiescent current through the termination (IOH) reduces

VOH (due to the gate’s internal resistance) resulting in a decreased

noise margin

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Source terminationAlternatively could use a circuit with multiple outputs, e.g., a fanout buffer, to drive more than one series terminated line

Each output treated individuallyLoad distribution

Line impedance

Pull-down resistor value

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Other termination challengesWhen there are several signal drivers on a given transmission line and they are not located together, where should the termination be located ?

Example, TTL or CMOS tri-state outputs on bus, or ECL (or GaAs) gates connected in Wired-OR configuration on a transmission line

Possible solutions include:1. Adding a source termination to each driver

2. Adding an end termination to each receiver

3. Adding a series resistance between every junction of branches

4. Adding a shunt termination in the middle of the network

IssuesOption 1 well defined, requires little power, provides damping, reduces settling time

Option 2 requires a lot of drive power but works in star configuration

Options 1 and 2 provides a perfect solution except it wastes power and attenuates the signal

Option 3 attenuates the signal at each junction Option 4 is the middle termination

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Other termination challengesDriving multiple lines with single source, single termination

Can drive a mix of terminatedand unterminated lines

Distorted waveforms result as the unterminated stub length increases

The ripple following the LO HI transition is a result of inadequate quiescent IOH level to cause a full

signal level on all lines

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Other termination challengesData busing involves connecting two or more outputs and one or more inputs to the same signal line

Any driver can be enabled to apply data to the line

Termination resistors matching the line impedance connected to both ends to prevent reflections

In analyzing such a configuration, the capacitance of a disabled (unactive) driver should be taken as 2 pF for ECL

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Other termination challengesExamples of how to terminate twisted pair cables

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Other termination challengesExamples of how to terminate coaxial cables

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Termination resistor specificationsAccuracy

R = Rnom R (%), R is the tolerance

Impacts the reflection coefficient,

Variations in R and Zo affect

Ideally R = 0

Typical choices are 10%, 5%, 1%

Recall noise marginfor ECL, NM ~ 15%

for R 10% Zo +22% or -19%

for R 5% Zo +28% or -22%

for R 1% Zo +34% or -25%

for R 0% Zo +35% or -26%

o

o

ZR

ZR

1

1

Z

R

o

74.0Z

R35.1

o

Zo impacts board manufacturing tolerances

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Termination resistor specificationsPower rating

Found using worst case condition (steady state)

for ECL or GaAs,

VHI ~ -0.8 V, VTT = -2 V, RT = 50 P = 29 mW

1/8-W resistors appropriate

Resistor composition & package optionsIdeally the resistor should be purely resistive

ZR = R + jXR , XR 0

However real resistors have reactance

T

2TTHI

R

VVP

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Termination resistor specificationsResistor composition & package options

High-frequency circuit model for resistor

Wire-wound resistors have a large inductive compontent

Carbon-film or printed resistors have lower inductance

Leaded resistors have lead inductance

Surface-mount (leadless) resistors have much less inductance

For high-frequency applications (low Tr) systems

inductance is a significant issue

Use leadless, chip resistors

Added benefit, doesn’t require vias for mountingvias cost money and restrict routing areas

Printed resistors

Laser trimmed to obtain precise resistance values

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Termination resistor specificationsResistor composition & package options

Surface-mounted chip resistors also have less inductive crosstalk than leaded parts when placed close together

Multi-resistor packs (packages containing multiple resistors, oftenin a single in-line package – SIP or dual in-line package – DIP)have unacceptable crosstalk due to proximity and due to a common current path

DO NOT USE THESE IN HIGH SPEED DESIGNS