1 the nseu sensitivity of static latch based fpgas and flash storage cplds joseph fabula jason moore...

1

The NSEU Sensitivity of Static Latch Based FPGAs and

Flash Storage CPLDs

Joseph FabulaJason MooreAustin LeseaSaar Drimer

MAPLD2004This work has benefited from the use of the Los Alamos Neutron Science Center

at the Los Alamos National Laboratory. This facility is funded by the US Department of Energy under Contract W-7405-ENG-36.

Fabula_139 MAPLD20042

Objectives of this Study

• Measure the neutron single event upset cross section of various current CMOS processes- Utilizing accelerated neutron beams to:

• Test the upset potential of the static latches in FPGAs and CPLDs• Test the upset potential of the flash storage cells in CPLDs

- Utilizing applications atmospheric based tests to• Test the upset potential of the static latches in FPGAs• Calibrate the results of accelerated beam testing

• Compare findings with other independent researchers


Test Facilities Used

• Accelerated Testing– Los Alamos Neutron Science Center– Hess spectrum accelerated neutron beam– Energy levels 1.5 to 600 MeV

• Applications Testing (natural flux)– Xilinx San Jose – sea level– Xilinx Albuquerque – 5,200 feet– White Mountain Research Center – 12,000 feet– Mauna Kea Observatory – 13,500 feet


Devices Tested

• Virtex II FPGA– XC2V6000– 150 nM CMOS Static-Latch based technology

• Virtex II-Pro FPGA– XC2VP4 and XC2VP7– 130 nM CMOS Static-Latch based technology

• Spartan 3 FPGA– XC3S100– 90 nM CMOS Static-Latch based technology

• XPLA3 (CoolRunner I) CPLD– XCR3256XL– 350 nM CMOS FLASH based technology

• CoolRunner II CPLD– XC2C256– 150 nM CMOS FLASH based technology


FPGA Test Fixtures

Virtex II

Virtex II-Pro Spartan 3


CPLD Test Fixtures


How we tested NSEU Sensitivity

• Accelerated Testing vs Atmospheric Testing– Accelerated

• Testing with Spallation Neutron sources– LANSCE spallation spectrum matches atmospheric neutrons– LANSCE source gives ~ 105 to 106 acceleration

– Atmospheric• We can use the natural radiation environment around us• Due to low rates, a very large number of devices are required • Testing times can be very long (many month to years)

– Acceleration (up to 10X) is achievable by testing at altitude(s)• However, this test is the ultimate correlation for all accelerated tests

– references • JEDEC Standard (JESD89) “Measurement and Reporting of Alpha Particles and

Terrestrial Cosmic Ray- Induced Soft Errors in Semiconductor Devices”• IEC TC107-AR-8 (draft currently) Avionics Processes


Virtex II Accelerated Data

Run Vdd Count Fluence Fluence>10 MeV >1.5 MeV Errors >10 MeV

Neutron SEU Test Sept 1, 2003 (2V6000)14 1.50 74975 1.33E+09 2.55E+09 650 2.95E-14

Neutron SEU Test, December 2002 (2V6000)1 1.50 126013 2.14E+09 4.08E+09 1213 3.42E-14

1.50 126013 2.14E+09 4.08E+09 1137 3.20E-145 1.50 98091 1.67E+09 3.17E+09 894 3.24E-14

1.50 98091 1.67E+09 3.17E+09 858 3.11E-146 (60deg angle) 1.50 90780 1.54E+09 2.94E+09 906 3.54E-14

1.50 90780 1.54E+09 2.94E+09 880 3.44E-147 (30deg angle) 1.50 95821 1.63E+09 3.10E+09 913 3.38E-14

1.50 95821 1.63E+09 3.10E+09 873 3.24E-14

CLB Cross-section


Virtex II-Pro Accelerated Data

Run # Experiment Pulse Count Counts Run Fluence Fluence Cross-section

Configuration per Minute Time >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV1 A 156,697 3,561 44 2.62E+09 5.13E+09 142 2.19E-14 1.12E-142 A 466,852 3,112 150 7.82E+09 1.53E+10 367 1.90E-14 9.71E-153 A 1,293,428 3,804 340 2.17E+10 4.23E+10 1749604 A 562,097 3,386 166 9.41E+09 1.84E+10 515 2.21E-14 1.13E-145 A 1,953,857 3,428 570 3.27E+10 6.39E+10 1840 2.27E-14 1.16E-146 B 311,031 2,592 120 5.21E+09 1.02E+10 331 2.57E-14 1.31E-147 B 996,496 3,163 315 1.67E+10 3.26E+10 978 2.37E-14 1.21E-148 B 468,256 3,345 140 7.84E+09 1.53E+10 502 2.59E-14 1.32E-149 B 1,799,424 3,395 530 3.01E+10 5.89E+10 1844 2.47E-14 1.27E-14

A= part behind 2V6000sB= part in front of beam

Run # Vdd Counts Fluence Fluence Cross-section

per Minute Run Time >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV15 1.50 72826 30 1.29E+09 2.48E+09 150 4.06E-14 2.11E-1416 1.50 354730 120 6.28E+09 1.21E+10 737 4.10E-14 2.13E-14

18b 1.50 49929 15 8.84E+08 1.70E+09 110 4.34E-14 2.26E-1425 1.50 374224 105 6.62E+09 1.28E+10 715 3.77E-14 1.96E-1426 1.50 176636 60 3.13E+09 6.02E+09 347 3.87E-14 2.01E-14

2VP4

2VP7


Spartan 3 Accelerated Data

Run Vdd Count Time Fluence Fluence(min) >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV

S-3 Testing (Sept 1, 2003) 3S10001 1.20 73206 25 1.30E+09 2.49E+09 106 3.08E-14 1.60E-14 28 4.89E-14 2.54E-142 1.20 39755 15 7.04E+08 1.35E+09 57 3.05E-14 1.58E-14 18 5.78E-14 3.00E-143 1.20 78584 30 1.39E+09 2.68E+09 96 2.60E-14 1.35E-14 35 5.69E-14 2.95E-144 1.20 120305 45 2.13E+09 4.10E+09 160 2.83E-14 1.47E-14 47 4.99E-14 2.59E-145 1.20 160103 60 2.83E+09 5.46E+09 202 2.68E-14 1.39E-14 65 5.19E-14 2.69E-146 1.20 311946 120 5.52E+09 1.06E+10 412 2.81E-14 1.46E-14 126 5.16E-14 2.68E-147 1.20 300332 120 5.32E+09 1.02E+10 417 2.95E-14 1.53E-14 111 4.72E-14 2.45E-148 1.20 160020 85 2.83E+09 5.45E+09 213 2.83E-14 1.47E-14 54 4.31E-14 2.24E-149 1.20 161337 6010 1.20 30743 14 5.44E+08 1.05E+09 31 2.15E-14 1.11E-14 10 4.15E-14 2.16E-1411 1.20 211320 90 3.74E+09 7.20E+09 254 2.56E-14 1.33E-14 87 5.26E-14 2.73E-1412 1.20 87320 30 1.55E+09 2.98E+09 112 2.73E-14 1.42E-14 40 5.85E-14 3.04E-1413 1.20 233173 90 4.13E+09 7.94E+09 356 3.25E-14 1.69E-14 100 5.48E-14 2.85E-1427 1.20 201972 100 3.57E+09 6.88E+09 235 2.48E-14 1.29E-14 75 4.74E-14 2.46E-1428 1.20 132054 50 2.34E+09 4.50E+09 173 2.79E-14 1.45E-14 43 4.16E-14 2.16E-1429 1.20 97026 25 1.72E+09 3.31E+09 111 2.43E-14 1.26E-14 43 5.66E-14 2.94E-14

S-3 Testing (Nov 11, 2003) 3S100010A 1.20 157176 60 2.78E+09 5.36E+09 244 3.30E-14 1.72E-14 59 4.79E-14 2.49E-1411A 1.20 157473 60 2.79E+09 5.37E+09 253 3.42E-14 1.78E-14 76 6.16E-14 3.20E-1417A 1.20 2031744 725 3.60E+10 6.92E+10 3537 3.70E-14 1.92E-14 539 3.39E-14 1.76E-14

CLB Cross-section BRAM Cross-Section


CPLD (Flash) Accelerated Data

Run Unit Config Vdd Count CpM Time Software Initial Final Fluence Fluence SRAM EEPROM desk (min) ma ma >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV

Cool Runner II - XC2C256 180 nM

6A 1 front 1.80 37601 2507 15 CPLD Engineering <10 <10 6.32E+08 1.22E+09 2 2.57E-14 1.33E-14 0 N/A N/A7A 1 front 1.80 334613 2788 120 CPLD Engineering <10 <10 5.62E+09 1.08E+10 20 2.89E-14 1.50E-14 0 N/A N/A8A 1 front 1.80 150656 2511 60 CPLD Engineering <10 <10 2.53E+09 4.88E+09 10 3.21E-14 1.66E-14 0 N/A N/A9A 1 front 1.80 1442215 2487 580 CPLD Engineering <10 <10 2.42E+10 4.67E+10 107 3.58E-14 1.86E-14 0 N/A N/A

XC2C256 weighted average 3.30E+10 6.36E+10 139 3.42E-14 1.77E-14

XCR3256XL (350 nM)

XC2C256 (150 nM)

Run UnitConfigVdd Count CpM Time Software Initial Final Fluence Fluence SRAM EEPROM desk (min) ma ma >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV Errors >10 MeV >1.5 MeV

2A 58front 3.30 34957 2330 15 CPLD Engineering <10 <10 5.87E+08 1.13E+09 0 0.00E+00 0.00E+00 0 N/A N/A4A 58front 3.30 38059 2537 15 CPLD Engineering <10 <10 6.39E+08 1.23E+09 0 0 N/A N/A4B 58front 3.30 80162 2672 30 CPLD Engineering <10 <10 1.35E+09 2.60E+09 0 0 N/A N/A4C 58front 3.30 129773 2884 45 CPLD Engineering <10 <10 2.18E+09 4.20E+09 0 0 N/A N/A4D 58front 3.30 202343 2529 80 CPLD Engineering <10 <10 3.40E+09 6.55E+09 2 5.08E-15 2.63E-15 0 N/A N/A5A 58front 3.30 296405 2470 120 CPLD Engineering <10 <10 4.98E+09 9.60E+09 0 0 N/A N/A


Summary Accelerated Test Results

TECHNOLOGY DEVICE CROSS SECTION

150 nM CoolRunner II 3.42 E -14150 nM Virtex II 3.05 E -14130 nM Virtex II-Pro 2.98 E -1490 nM Spartan 3 2.85 E -14

Static Latch Upset Results

TECHNOLOGY DEVICE CROSS SECTION

350 nM CoolRunner 0150 nM CoolRunner II 0

Flash Storage Upset Results

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

1E+08

1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 1E+02 1E+03 1E+04

Neutron Energy (MeV)

Dif

fere

ntia

l Neu

tron

Flu

x (n

/cm

^2-s

ec-M

eV)

Reactor

Atmospheric - (Hess)

Comparison of Neutron Spectra

Tungsten Spallation

This work has benefited from the use of the Los Alamos Neutron Science Center at the Los Alamos National Laboratory.

This facility is funded by the US Department of Energy under

Contract W-7405-ENG-36.


Rosetta NSEU Testing

• What is Rosetta?– Atmospheric Test started in 7/2002– Rosetta stone provided correlation between

languages/scripts. Rosetta experiment provides correlation to LANSCE test results

– System of 100 2V6000s• Runs 24/7/365 – Internet Monitored• Read back and error logging 12 times a day• Each test contains >1.9 Gbits of config latches

– Test operating at 4 altitudes• Sea Level – San Jose• 5,200 feet – Albuquerque• 12,000 feet – White Mountain Research Center• 13,500 feet – Mauna Kea Observatory

– Additional testing started for VII-Pro (130 nM) and for Spartan-III (90 nM)


Rosetta Board100 XC2V6000

1.9 Gbits


Rosetta Test Results

• Data shown is accurate as of 5/6/04– 3.18e6 total device hours– Rosetta/LANSCE correlation factor is 1.51

• LANSCE is predicting worse results by a factor of 1.51

San Jose 443 10632 6 1.06E+06 1.96E+09 14.40 153,101 2.00E-14ABQ 564 13536 34 1.35E+06 1.96E+09 53.28 721,198 2.41E-14WM 229 5496 66 5.50E+05 1.96E+09 338.40 1,859,846 1.81E-14MK 90 2160 18 2.16E+05 1.96E+09 229.57 495,880 1.85E-14

Average Cross-Section 2.02E-14LANSCE 2V6000 3.05E-14

Rosetta Factor 1.51

Location Days Hours Upsets>10MeV Cross-

SectionDevice Hours Bits>10MeV Flux

(n/cm2-hr) >10MeV Fluence

16

Appendix


Logic Failures vs SEUs(SEUPI)

• Is there a difference? YES– An SEU does not necessarily cause a functional failure

• Many Configuration Bits are not used– 90% of the FPGA is routing!

– Example• Proton test of a V300• Two methods to evaluate:• Method 1:

– Total Upsets / # 1 bit failures– 437/8 = 54.6

• Method 2:– Total Upsets / # failures– 437 / 69 = 6.3

– Conservatively, we use a factor of 10 (SEUPI factor)

0 5 10 15 20 25 30 35 0

1

2

3

4

5

6

7

8

9

Feq

uenc

y (6

9 T

rial

s)

# of Configuration bit Upsets


Logic Failures vs SEUs(SEUPI)

• Independent Confirmation– Work by BYU and LANL indicated that the logic upset multiplier can be

as high as 25 - 100 for specific designs in a V1000– By logical extension, the larger the FPGA the higher the multiplier for

any given logic implementation– BYU and LANL have developed a bit flip logic impact simulator for the

V1000 that has been verified in Proton testing– Xilinx has extensive data on PIP utilization from the many EasyPath

applications that we are supporting– Xilinx laboratories are developing software algorithms (SEUPI) to

identify “critical” bits which may affect user logic– SEUPI analysis of specific customer applications has shown SEUPI

factors from 10 to 80 with an mean of 42


Comparison with Independent Data

• Actel commissioned IROC to independently test various FPGAs for NSEU Effects

• IROC tested Xilinx, Altera and Actel products– Test design was “n” 16x16 bit multipliers whose

values were muxed to a common output. Mux line was 7 bits -> up to 128 multipliers supported

– Pure combinatorial logic – no FFs!• “Focus was on configuration memory only”


IROC Analysis

• Results– IROC unquivocally stated that Xilinx FPGAs do not exhibit

NSEL (Neutron Single Event Latch), a potentially destructive effect seen in some recent ASICs and RAMs

– IROC confirmed the existence of the SEUPI factor in Xilinx FPGAs – even though it was only in one design:

– VII (14MeV test) = 6.67– VII (LANSCE) = 10– S3 (LANSCE) = 4.54

– Reverse engineering of the IROC data confirmed Xilinx contention that the per-bit cross-section was improved by Xilinx in their 90nm technology vs their 150nm technology (see next slide)


IROC Analysis

• 150nm (V-II) vs 90nm (S-3)– Using IROCs data for the Number of SEUs and the

Fluence (n/cm2) we can calculate the per-bit cross-section difference between technologies

• Conclusion: S-3 (90 nM) cross-section is smaller!

Run # Chip1 Chip2 Chip3 Chip4 Chip5 Chip61 0 0 0 0 0 02 6.15E-14 4.37E-14 6.63E-14 5.16E-14 6.13E-14 6.96E-143 7.28E-14 6.05E-14 5.46E-14 5.89E-14 5.29E-14 6.80E-144 5.35E-14 5.68E-14 5.76E-14 5.64E-14 5.26E-14 5.41E-145 6.52E-14 6.09E-14 7.43E-14 5.18E-14 5.18E-14 5.83E-14

Per-bit Cross-Section (Virtex-II)Run # Chip1 Chip2 Chip3 Chip4 Chip5 Chip6

1 0 0 0 0 0 02 1.09E-14 8.70E-15 6.88E-15 8.89E-15 1.09E-14 1.06E-143 8.91E-15 7.17E-15 8.46E-15 5.40E-15 8.39E-15 8.93E-154 9.32E-15 6.46E-15 6.60E-15 9.18E-15 8.15E-15 7.60E-155 2.02E-14 2.03E-14 1.86E-14 2.01E-14 2.02E-14 1.77E-14

Per-bit Cross-Section (Spartan-III)


Conclusions• LANSCE data provides good correlation with atmospheric testing when the

correct energy model(s) are used• ROSETTA data indicates clear support for using the >10.0 MeV model for

current process technology• Independent IROC data confirmed three of Xilinx key assertions, namely:

– The sky is not falling as technology continues to shrink below 220 nM (Moore’s law still lives and our designers are smart)

– Xilinx logic upset rates are greatly improved due to the documented SEUPI factor

– Xilinx FPGAs do not exhibit Neutron Single Event Latch-up• The neutron cross sections have been stabilized as technology shrinks

(compensating a sensitivity increase by a probability decrease function)• Xilinx designers are increasing the robustness of our state of the art static

latches to the effects of atmospheric neutron flux• Current generations of Flash storage cells continue to be immune to neutron

upset


Virtex II MTBF Calculations

• Failure defined as incorrect operation of the FPGA– Time to Configuration Upset (Config Upset) =

1 / (# bits * Neutron Cross-Section (LANSCE) * Neutron Flux)

– Config Upset Rosetta = Rosetta factor applied– Logic Upset = SEUPI factor applied

• Ignoring the SEUPI factor is inaccurate! – you don’t use every configuration memory cell in an FPGA.

Config UpsetNeutron Config Upset Config Upset Rosetta Logic Upset

Device # Config Bits Cross-Section (Hrs) (Yrs) (Yrs) (Yrs)2V40 3.60E+05 3.05E-14 6.32E+06 721.3 1090.7 109072V80 6.35E+05 3.05E-14 3.58E+06 408.9 618.3 61832V250 1.70E+06 3.05E-14 1.34E+06 153.0 231.4 23142V500 2.76E+06 3.05E-14 8.24E+05 94.0 142.2 1422

2V1000 4.08E+06 3.05E-14 5.57E+05 63.6 96.2 9622V1500 5.66E+06 3.05E-14 4.02E+05 45.9 69.4 6942V2000 7.49E+06 3.05E-14 3.04E+05 34.7 52.4 5242V3000 1.05E+07 3.05E-14 2.17E+05 24.8 37.4 3742V4000 1.57E+07 3.05E-14 1.45E+05 16.6 25.1 2512V6000 1.66E+07 3.05E-14 1.37E+05 15.7 23.7 2372V8000 2.91E+07 3.05E-14 7.83E+04 8.9 13.5 135

Calculations are at sea level = 14.4n-cm2/hr flux; Rosetta Factor = 1.5, SEUPI Factor = 10


Effects of Altitude

• Virtex-II MTBF Calculations at 40K feet– Assumptions:

• Neutron Flux of 3060 n-cm2/hr@ 40,000 feet• Rosetta Factor of 1.5• SEUPI Factor of 10

Config UpsetNeutron Config Upset Config Upset Rosetta Logic Upset

Device # Config Bits Cross-Section (Hrs) (Yrs) (Yrs) (Yrs)2V40 3.60E+05 3.05E-14 2.97E+04 3.394 5.133 51.3292V80 6.35E+05 3.05E-14 1.69E+04 1.924 2.909 29.0942V250 1.70E+06 3.05E-14 6.31E+03 0.720 1.089 10.8912V500 2.76E+06 3.05E-14 3.88E+03 0.443 0.669 6.692

2V1000 4.08E+06 3.05E-14 2.62E+03 0.299 0.453 4.5272V1500 5.66E+06 3.05E-14 1.89E+03 0.216 0.327 3.2662V2000 7.49E+06 3.05E-14 1.43E+03 0.163 0.247 2.4672V3000 1.05E+07 3.05E-14 1.02E+03 0.116 0.176 1.7612V4000 1.57E+07 3.05E-14 6.84E+02 0.078 0.118 1.1802V6000 1.66E+07 3.05E-14 6.46E+02 0.074 0.111 1.1152V8000 2.91E+07 3.05E-14 3.68E+02 0.042 0.064 0.636


Spartan 3 MTBF Calculations

• Failure defined as incorrect operation of the FPGA– Time to Configuration Upset (Config Upset) =

1 / (# bits * Neutron Cross-Section (LANSCE) * Neutron Flux)

– Config Upset Rosetta = Rosetta factor applied– Logic Upset = SEUPI factor applied

• Ignoring the SEUPI factor is inaccurate! – you don’t use every configuration memory cell in an FPGA.

Calculations are at sea level = 14.4n-cm2/hr flux; Rosetta Factor = 1.5, SEUPI Factor = 10

Neutron Config Upset Config Upset Logic Upset

Device # Config Bits Cross-Section (Hrs) (Yrs)

Config Upset

Rosetta (Yrs)

(Yrs)

XC3S50 4.39E+05 2.87E-14 5.51E+06 629 1019 10187 XC3S200 1.05E+06 2.87E-14 2.31E+06 264 427 4271 XC3S400 1.70E+06 2.87E-14 1.42E+06 163 263 2634 XC3S1000 2.66E+06 2.87E-14 9.11E+05 104 169 1685 XC3S1500 5.21E+06 2.87E-14 4.64E+05 53 86 858 XC3S2000 7.67E+06 2.87E-14 3.15E+05 36 58 583 XC3S4000 1.13E+07 2.87E-14 2.14E+05 24 40 395 XC3S5000 1.33E+07 2.87E-14 1.82E+05 21 34 337


Effects of Altitude

• Spartan 3 MTBF Calculations at altitude– Assumptions:

• Neutron Flux of 3060 n-cm2/hr @ 40,000 feet• Rosetta Factor of 1.5• SEUPI Factor of 10

Logic Upset Logic Upset1 Logic Upset2 Logic Upset3 Sea Level 5K ft 10K ft 40K ft

Device (Yrs) (Yrs) (Yrs) (Yrs)

XC3S50 10187 2845 1047 33.96 XC3S200 4271 1193 439 14.24 XC3S400 2634 736 271 8.78 XC3S1000 1685 471 173 5.62 XC3S1500 858 240 88 2.86 XC3S2000 583 163 60 1.94 XC3S4000 395 110 41 1.32 XC3S5000 337 94 35 1.12

1 5K feet reduction factor of 3.58 applied per IBM-Method, JEDEC-89 2 10K feet reduction factor of 9.73 applied per IBM-Method, JEDEC-89 3 40K foot reduction factor of 300 applied per JEDEC-89

1 the nseu sensitivity of static latch based fpgas and flash storage cplds joseph fabula jason moore...

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