1

Thermal Via Placement in 3D ICsThermal Via Placement in 3D ICs

Brent Goplen, Sachin SapatnekarBrent Goplen, Sachin SapatnekarDepartment of Electrical and Computer EngineeringDepartment of Electrical and Computer Engineering

University of MinnesotaUniversity of Minnesota

2

OverviewOverview

IntroductionIntroduction Simplified ExampleSimplified Example FormulationFormulation ResultsResults ConclusionsConclusions

3

3D IC Using Wafer Bonding3D IC Using Wafer Bonding

SOI wafers with bulk substrate removed

Adapted from [Das et al., ISVLSI, 2003]

Generalized view

Bulk waferMetal levelof wafer 1 Layer 1

Layer 2

Layer 3

Layer 4

Layer 5

Bulk Substrate

Detailed view

Inter-layerbonds

Devicelevel 1

500m

10m

1m

4

Improvements and Improvements and ObstaclesObstacles of 3D ICs of 3D ICs

BenefitsBenefits Reduced wirelengthReduced wirelength Lower power per transistorLower power per transistor Decreased delayDecreased delay Higher packing densitiesHigher packing densities Smaller chip areasSmaller chip areas

ObstaclesObstacles Processing technologyProcessing technology Thermal issuesThermal issues

Higher power densitiesHigher power densities Increased thicknessIncreased thickness Insulating materials Insulating materials

3D design tools3D design tools

0

200

400

600

800

1000

1200

1400

0 5 10 15 20 25 30 35

Length (mm)

Net

De

ns

ity

(#

/mm

)

4 Strata

2 Strata

1 Stratum

3D Global Net Distributions

[Joyner, Zarkesh-Ha and Meindl, ASIC/SOC ’01]

from Intel

5

Methods of Mitigating Thermal ProblemsMethods of Mitigating Thermal Problems

Rearrange heat sources Rearrange heat sources Manually fix hot spotsManually fix hot spots Thermal placementThermal placement

Improved heat sinkingImproved heat sinking Improved packagingImproved packaging More efficient heat removalMore efficient heat removal

Improved thermal conduitsImproved thermal conduits Internal heat sinkingInternal heat sinking Thermal via placementThermal via placement

Minimize power usageMinimize power usage Low-power designLow-power design Minimize wirelengthMinimize wirelength

6

Thermal Via RegionsThermal Via Regions

Substrate

Thermal Via

Thermal viasThermal vias Electrically isolated viasElectrically isolated vias Used for heat conductionUsed for heat conduction

Thermal via regionsThermal via regions Only region where thermal vias are allowedOnly region where thermal vias are allowed Predictable obstacle for routingPredictable obstacle for routing Variable density of thermal viasVariable density of thermal vias

7

Thermal Vias in 3D ICsThermal Vias in 3D ICs

Thermal Via Region

Inter-Row Region

Row Region

Standard cells (heat sources) Bulk substrate elements

Layer elements

Inter-layer elements

8

Benefits and ChallengesBenefits and Challenges BenefitsBenefits

Reduced temperaturesReduced temperatures Uses existing via fabricationUses existing via fabrication Benefits 3D ICs moreBenefits 3D ICs more

ChallengesChallenges Creates obstacles to routingCreates obstacles to routing Where to put them? Where to put them? CAD tools neededCAD tools needed

9

OverviewOverview

IntroductionIntroduction Simplified ExampleSimplified Example FormulationFormulation ResultsResults ConclusionsConclusions

10

Simplified ExampleSimplified Example

Layers and inter-layers

Bulk Substrate

{Thermal Via Regions

Heat Sources(standard cells)

11

Simplified ExampleSimplified Example

12

Simplified ExampleSimplified Example

4 5 6

7 8 9

10

10W

1 2 3

10oC/W

10oC/W

10oC/W10oC/W 10oC/W

10oC/W10oC/W10oC/W

10oC/W

10oC/W

10oC/W

10oC/W10oC/W10oC/W

10oC/W

13

Simplified ExampleSimplified Example

10W

59oC 81oC 59oC

32oC 36oC 32oC

0oC

65oC 70oC 65oC

10oC/W

10oC/W

10oC/W10oC/W 10oC/W

10oC/W10oC/W10oC/W

10oC/W

10oC/W

10oC/W

10oC/W10oC/W10oC/W

10oC/W

14

Simplified ExampleSimplified Example

59oC 81oC 59oC

32oC 36oC 32oC

0oC

10W

10oC/W10oC/W

65oC 70oC 65oC

10oC/W10oC/W 6oC 6oC

27oC 27oC

High Temps

High temp drop

15

Simplified ExampleSimplified Example

59oC 81oC 59oC

32oC 36oC 32oC

0oC

65oC 70oC 65oC

10oC/W10oC/W

1 1

60

60 67 60

60

16

Simplified ExampleSimplified Example

59oC 81oC 59oC

32oC 36oC 32oC

0oC

65oC 70oC 65oC

10oC/W10oC/W

11

37

34 34

64

33

44 51 44

37

Use thermal gradientnot temperature!

17

High Temperatures

Place Thermal Vias

18

High Thermal Gradients

Place Thermal Vias

19

Thermal Via Region

High Thermal Via Density

High Effective Thermal Conductivities

Impractical to place thermal vias individuallyImpractical to place thermal vias individually Use arrangement of thermal vias insteadUse arrangement of thermal vias instead

Gives thermal via density valueGives thermal via density value Changes the effective thermal conductivityChanges the effective thermal conductivity

20

High Thermal Conductivity

High Thermal Via Density

High Thermal Gradients

21

Thermal GradientsThermal

Conductivities

Old Temperatures

New Temperatures

22

Thermal GradientsThermal

Conductivities

Initial Temperatures

New TemperaturesThermal Via

Densities

23

Mathematical FormulationMathematical Formulation Heat transfer within an element (region)

K ∆T=P

Assume P doesn’t change between iterations Knew

∆Tnew = Kold ∆Told

Knew = Kold

(∆Told / ∆Tnew)

Using the thermal gradient, g = ∆T /d, Knew

= Kold (gold / gnew)

Let gnew slowly approach an ideal value, gideal

gnew = gideal (gold / gideal )α, 0 ≤ α ≤ 1

Knew= Kold (gold / gideal )1-

α

Update gideal using maximum temperature gideal

= gideal (Tmaxideal / Tmax)

∆∆TT

PP

KK

24

Thermal Via Placement AlgorithmThermal Via Placement Algorithm

GIVEN IDEAL MAXIMUM TEMPERATURE: Tmaxideal

Main loop

SET K’s TO MINIMUM AND CALCULATE THERMAL PROFILE

UPDATE Kz= Kz (g / gideal )1- α

UPDATE m and Klateral

UPDATE gideal = gideal Tmaxideal /Tmax

YESNO

DONE

CONVERGED?

FOR EACH THERMAL VIA REGION

CALCULATE THERMAL PROFILE

25

Thermal Conductivities of Thermal Via RegionsThermal Conductivities of Thermal Via Regions

Layer Interlayer

Thermal Conductivity Percent Thermal Via

Thermal Conductivity Percent

Thermal ViaLateral Vertical Lateral Vertical

Minimum 2.15 1.11 0 1.10 1.10 0

Midrange 3.21 100.33 25 1.31 50.71 12.5

Maximum 5.75 199.55 50 1.65 100.33 25

The Relationship between Thermal Via Density and Thermal Conductivity

0

1

2

3

4

5

6

0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50%

Percent Metallization

La

tera

l th

erm

al co

nd

uctivity

0.00

50.00

100.00

150.00

200.00

250.00

300.00

Ve

rtic

al th

erm

al co

nd

uctivity

26

Range of Temperature ValuesRange of Temperature ValuesBenchmark Circuit

Thermal Via Density of Thermal Vias Regions

Minimum (0%) Midrange (23.9%) Maximum (47.9%)

name cells Tave Tmax Tave Tmax Tave Tmax

struct 1888 15.4 58.9 10.9 35.0 10.4 31.3

biomed 6417 14.6 46.0 10.5 24.1 10.0 20.2

ibm01 12282 14.2 45.1 10.1 26.2 9.6 22.7

ibm04 26633 13.5 54.0 10.0 26.5 9.6 21.4

ibm09 51746 13.8 53.0 10.2 26.8 9.8 21.4

ibm13 81508 14.6 47.3 10.3 23.6 9.7 19.3

ibm15 158244 15.1 52.8 10.5 26.5 9.9 20.6

Midrange thermal via densities produceMidrange thermal via densities produce 47.1% lower maximum temperatures47.1% lower maximum temperatures 28.3% lower average temperatures28.3% lower average temperatures

27

Range of Temperature ValuesRange of Temperature ValuesBenchmark Circuit

Thermal Via Density of Thermal Vias Regions

Minimum (0%) Midrange (23.9%) Maximum (47.9%)

name cells Tave Tmax Tave Tmax Tave Tmax

struct 1888 15.4 58.9 10.9 35.0 10.4 31.3

biomed 6417 14.6 46.0 10.5 24.1 10.0 20.2

ibm01 12282 14.2 45.1 10.1 26.2 9.6 22.7

ibm04 26633 13.5 54.0 10.0 26.5 9.6 21.4

ibm09 51746 13.8 53.0 10.2 26.8 9.8 21.4

ibm13 81508 14.6 47.3 10.3 23.6 9.7 19.3

ibm15 158244 15.1 52.8 10.5 26.5 9.9 20.6

Midrange thermal via densities produceMidrange thermal via densities produce 47.1% lower maximum temperatures47.1% lower maximum temperatures 28.3% lower average temperatures28.3% lower average temperatures

28

ResultsResults

Benchmark Circuit

Thermal Via RegionsTave Tmax

Run Time (sec)Kave % thermal via

struct 34.9 8.5% 11.4 35.0 3.9

biomed 50.1 9.2% 10.9 24.1 18.2

ibm01 57.1 14.1% 10.1 26.2 19.1

ibm04 51.6 12.7% 10.1 26.5 43.1

ibm09 51.1 12.6% 10.3 26.8 61.5

ibm13 59.8 14.8% 10.3 23.6 134.0

ibm15 45.9 11.3% 10.8 26.5 191.5

Same maximum temperatures as with midrange via densitiesSame maximum temperatures as with midrange via densities 1.8% higher average temperatures1.8% higher average temperatures

11.9% thermal via density in thermal via regions (1.2% in chip)11.9% thermal via density in thermal via regions (1.2% in chip) 50.3% lower than the midrange value50.3% lower than the midrange value

29

ResultsResults

Benchmark Circuit

Thermal Via RegionsTave Tmax

Run Time (sec)Kave % thermal via

struct 34.98.5%(-64.4%)

11.4(4.6%)

35.0(0.02%)

3.9

biomed 50.1 9.2% 10.9 24.1 18.2

ibm01 57.1 14.1% 10.1 26.2 19.1

ibm04 51.6 12.7% 10.1 26.5 43.1

ibm09 51.1 12.6% 10.3 26.8 61.5

ibm13 59.8 14.8% 10.3 23.6 134.0

ibm15 45.9 11.3% 10.8 26.5 191.5 Same maximum temperatures as with midrange via densitiesSame maximum temperatures as with midrange via densities 1.8% higher average temperatures1.8% higher average temperatures

11.9% thermal via density in thermal via regions (1.2% in chip)11.9% thermal via density in thermal via regions (1.2% in chip) 50.3% lower than the midrange value50.3% lower than the midrange value

30

Before Thermal Via PlacementBefore Thermal Via Placement

31

After Thermal Via PlacementAfter Thermal Via Placement

32

ConclusionsConclusions Thermal vias have a greater effect in 3D ICsThermal vias have a greater effect in 3D ICs

Thermal via regions provide regularity Thermal via regions provide regularity

Efficient iterative methodEfficient iterative method

Uses thermal gradients to adjust thermal conductivitiesUses thermal gradients to adjust thermal conductivities

Ideal maximum temperatureIdeal maximum temperature

Use lowered value as an objectiveUse lowered value as an objective

Minimizes use of thermal viasMinimizes use of thermal vias

Vias are put where they make the most impact Vias are put where they make the most impact

Reduces thermal resistance on heat conduction pathsReduces thermal resistance on heat conduction paths