1

TWEPP – Aachen – September 21th 2010

Wideband pulse amplifier for the integrated camera of the Cherenkov

Telescope ArrayE. Delagnesa, A. Sanuyb, D. Gascónb

on behalf of the NECTAr collaboration

Irfu /CEA/Saclay a

LPNHE / Paris

LPTA / Montpellier

ICC / Universitat Barcelona (ICC-UB) b

1

2

I. IntroductionII. Basic building blocks

III. First prototype: ACTA

IV. Second prototype: ACTA3

V. Summary

Outlook

~ 10 kmAir shower

~ 1o

Che

renk

ov li

ght

~ 120 m

Gamma ray

I. Introduction: Cherenkov telescopes

3.5o FOV càmera 577 PMTs3.5o FOV càmera 577 PMTs

MAGICCamera by IFAE

M. Martinez

Stereoscopy provides better:• Angular resolution.• Energy resolution (height).• Background rejection.• Sensitivity.

I. Introduction: the Cherenkov Telescope Array (CTA) observatory

HESSHESS

CANGAROOCANGAROO

MAGICMAGICCurrent Instrumentation

10-14

10-13

10-12

10-11

10 100 1000 104 105

E x

F(>

E)

[Te

V/c

m2s]

E [GeV]

Crab

10% Crab

1% Crab

GLAST

MAGIC

H.E.S.S.

CTA

Exploring the cutoff regime of cosmic

accelerators

Population studies, extended sources and,

precision measurements

High redshift AGNand pulsars

10-14

10-13

10-12

10-11

10 100 1000 104 105

E x

F(>

E)

[Te

V/c

m2s]

E [GeV]

Crab

10% Crab

1% Crab

GLAST

MAGIC

H.E.S.S.

CTA

10-14

10-13

10-12

10-11

10 100 1000 104 105

E x

F(>

E)

[Te

V/c

m2s]

E [GeV]

Crab

10% Crab

1% Crab

GLAST

MAGIC

H.E.S.S.

CTA

Exploring the cutoff regime of cosmic

accelerators

Population studies, extended sources and,

precision measurements

High redshift AGNand pulsars

Artist view of CTA-NorthKari Nilsson

How CTA aims to extend energy range and increase sensitivity? Large array (>1 km2)of Cherenkov telescopes (50-100)Different sizes: dish from 6 to 24 m

Camera and electronics must be optimized in terms ofPerformanceCost and reliability: integration

I. Introduction: the camera

Front end electronics: Pixel: fast phototosenrors

High QE PMTs // SiPM Modularity: cluster of 7/8 pixels Front end electronics in the

camera Digitization & trigger

Huge dynamic range: 16 bits

Signals up to 6 Kphe Single phe resolution for

calibration: Series noise < 3 nV/Hz

PM tube

Voltage dividerDC-DC converter

HV control cable

HESS cluster

5

Preamplifier

High gainPhotoSensor

Digitization

Camera Pixel

Front end electronics

Read-out

Low gain

DigitizationRead-out

Dual gain (12 bit) channelsGain 20 (25 dB)BW > 300 MHzLinearity < 1 %

High BW (>300 MHz):Night Sky Background:

Up to 100 MHz Minimize integration time

Simulation (S. Vorobiov)

I. Introduction: readout electronics

Analogue memory + slow digitization Sample and hold in a capacitor array

High speed: up to 3 GS/s (> 300 MHz analogue BW) Slow digitization for selected events

Trigger system Custom ASICs developed in the community

Domino Ring Sampler (DRS) by PSI For CTA: DRAGON poject

Sampling Analogue Memory (SAM) by Irfu For CTA: NECTAr project

Flash ADCs Commercial component Limited to 500 MS/s

High Cost and power consumption For CTA: FlashCam collaboration

No trigger needed

6

I. Introduction: NECTAr (Irfu/Saclay, LPNHE, LPTA and ICC-UB)

From HESS chip (SAM: only analogue memory) to a single chip integrating full acquisition channel:

NECTAr chip: COST & RELIABILITY

Chip 2: Integrated local trigger:- 8 or 16 fast comparators.- Coincidences in < 1 ns

FE board HESS-2

Chip 1 = full integrated acquisition channel

- Input signal amplif. (2 gains),- Analog memory (depth adapted

to CTA trigger latency) - ADC Wilky (already exists), - FIFO- Sérializer ~300Mb/s.

E. Delagnes

7

Accuracy 1-3 %

Bandwidth 400 MHz

Output range 1.5 to 2 Vpp

Gain 20

Temp. Coeff. < 0.05 %/K

Power < 50 mW

Slew rate 1500 V/µs

Series noise < 3 nV/Hz

Fully differential

AMS CMOS 0.35 um SAM technology

8

I. Introduction

II. The circuitIII. First prototype: ACTA

IV. Second prototype: ACTA3

V. Summary

Outlook

9II. The circuit: classical topologies for linear voltage amplifiers

Global feedback

Good linearity OpAmp with GBW > 8

GHz !! Reported: < 1 GHz in 0.35

um

Very difficult even with VDSM

Bipolar style “open loop”

Limited linearity Dynamic of 2 V impossible @ 3.3

V

Vi

Ibias1a/2

RE1a

Q1a

VtH

Ibias1b/2

RE1b

Q1b

VtL

RC1a RC1b

VCC

D1bD1a

V’oL V’oH

10II. The circuit: new approach

Dedicated CMOS topologies Local feedback

Linearized HF CMOS transconductor Used in continous time filters (GmC Filters)

Large swing I to V conversion

Ibias1a/2

RE1a

Q1a

VtH

Ibias1b/2

RE1b

Q1b

VtL

RC1a RC1b

VCC

D1bD1a

V’oL V’oH

LinearizedTransconducor

Large swing I to V conversion

11II. The circuit: bias-offset cross coupled differential pair

Completely linear First order:

• Linear using square law MOS: saturation

Tuneable gain

Second order effects on linearity Channel length modulation Mismatch Mobility reduction Body effect

M1 M2 M3 M4

Ibias

Vb

ViH ViL

23

4 2bias b

in b

I VV V

K

oD b iDI KV V 12 ox

WK C L

Control VDS variations: next slides

Large WL and common centroid

Scaling M1-4 vs M2-3 (for a given Gm)

Cannot use PMOS (large K needed)

GBW & Noise

5m bG KV mS

LinearizedTransconducor

Large swing I to V conversion

• L minimal (0.35 um)• Maximize GBW• Vds must be stable!

• W about 150 um• GBW and noise• Saturation

12II. The circuit: floating voltage source

A floating voltage source is needed (Vb) Bias voltage is offset in Vgs of two matched PMOS (M5 – M6)

Offset by different drain currents: Ib (fixed) vs Icf (control)

In closed loop (negative feedback) to decrease rout of Vb Must be independent of M2/M3 (Id23) drain current

Vgs of MP3 increases if Id23 increases Error amplifier changes VfbB to stabilize Vb

M1 M2 M3 M4

Ibias

Vb

ViH ViL

LinearizedTransconducor

Large swing I to V conversion

M1 M2

M4

IbiasVb

M4

M5

M3

IS

ISICF

M6

Vb+

Vb-

VfbB

13II. The circuit: folded regulated cascode common gate

Regulated cascode Folded: large voltage swing Low input impedance

– BW– Linearity

» Channel length modulation in input pair

RC < 1.5 K BW

Gm > 5 mS Gain (noise)

Ib 4 – 6 mA Linearity

Vb < 300 mV Range

LinearizedTransconducor

Large swing I to V conversion

M1 M2 M3 M4

Ibias

Vb

ViH ViL

2/3Ibias2/3Ibias

RC

M6

RFRC

M8

RF

M7M5

VoL VoH

14

I. Introduction

II. The circuit

III. First prototype: ACTAIV. Second prototype: ACTA3

V. Summary

Outlook

15III. First prototype: ACTA chip

First prototype (ACTA chip) Voltage buffer

Source follower

Gain tunable from 5 to 20

NLC NLC

Linear amplifiers

Degeneration CrossCoupled

CMOS 0.35umAMS 3 mm2

Submitted: July 20th 2009Received: October 26th

LinearizedTransconducor

Large swing I to V conversion

Voltage buffer

0

5

10

15

20

25

0 100 200 300

Gai

n

Floating supply control current [uA]

40 mV

700 mVRise time: 650 ps

GBW > 8 GHz in CMOS 0.35um !

Results of the first prototype

40 mV

700 mVRise time: 650 ps

GBW > 8 GHz in CMOS 0.35um !

40 mV

700 mVRise time: 650 ps

GBW > 8 GHz in CMOS 0.35um !

Results of the first prototype

16

III. First prototype: ACTA chip

• Working• No ringing

• Gain: 5 to 20

• Fast input pulse• Rise: 300 ps

• Output pulse• Rise time:

• Small signal (< 1V)• 550 ps

• High signal (> 1V)• 1.2 ns

Large Large signalsignal

Small Small signalsignal

17

-30

-20

-10

0

10

20

30

0 200 400 600 800 1000 1200 1400 1600 1800Output peak voltage [mV]

Res

idue

[m

V]

III. ACTA chip: linearity

• Gain:• Tunnable

• Linear range• About 1.4 V

0

200

400

600

800

1000

1200

1400

1600

1800

2000

0 50 100 150 200

Out

put p

eak

volta

ge [

mV

]

Input peak voltage [mV]

Gain: 20Gain: 20

1% error (F.S.)

18III. ACTA chip: frequency response

Cut-off (3dB) About 300 MHz

Non-linearity For VoD>1 Vpp

CL aboout 5pF < 1 pF when driving on-chip analogue memory input buffers

Gain for different Peak ot Peak VoD (GmVb@ACTA)

0,00

5,00

10,00

15,00

20,00

25,00

30,00

10,00 100,00 1000,00

Frequency [MHz]

Ga

in [

dB

]

150mV

300mV

600mV

1 V

1.5 V

1.8 V

19

I. Introduction

II. The circuit

III. First prototype: ACTA

IV. Second prototype: ACTA3

V. Summary

Outlook

20

IV. Second prototype: ACTA3

• Closed loop buffer to replace source followers Better linearity & higher range Lower power consumption: class AB amplifier

Good slew rate with low quiescent current !

New version of a SAM OpAmp• Developed in collaboration with Irfu/Saclay

20

Amplifier core

Floating voltagesupply Closed loop output drivers

• Closed loop buffer: Miller OpAmp

• Double current boost of output nMOSLinear boostClass B with nonlinear ctrl: off @ small signal x6 boost with 750 uA (DC) total bias current

• Series resistor at the output (Rd) for CL pole compensation

Limits BW

1/10 of total bias current

GBW > 400 MHzPM > 60 degSR > 1.5 V/ns @ 5 pFPower < 3mW

21

IV. ACTA3: 4 configurations21

Same gain block as in ACTA

Not tested, only to “debug”

Already in ACTA

LinearTransconducor

Resitive Load with regulated

cascode input

+

-

+

-

Rd

Rd

GmB5

Rd for compensation84 for 4-5 pF (aprox)

New buffer(same OpAmp NECTAr0)

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd

Rd

GmBO5

New buffer(same OpAmp NECTAr0)

Rd for compensation84 for 4-5 pF (aprox)

As GmB5 but gain stage is modified to generate the DC offset required by ADC

As GmBO5 but the amplifier (Rd1) adjusted to

drive a smaller CL (analogue memory input)

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd1

Rd1

GmBO1

Rd1 300 for 1 pF (aprox) Rd2 84 for 4-5 pF (aprox) New buffer

(same OpAmp NECTAr0)

+

-

+

-

Rd2

Rd2

Emulation of the NECTAr0 input buffer

As GmBO1 but buffer replaced by diff. amp:Subtract common mode signals (CMRR, PSRR)

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd1

Rd1

GmBOs1

Rd1 300 for 1 pF (aprox) Rd2 84 for 4-5 pF (aprox)

Differemtial amplifier

+

-

+

-

Rd2

Rd2

Emulation of the NECTAr0 input buffer

CMOS 0.35umAMS 3 mm2

Submitted: April 2010Received: end July 2010

Produced in Irfu/Saclay engineering run with first prototype of the analogue memory chip for CTA: NETCAr0

22

IV. ACTA3: pulse shape

• Good uniformity between small and large signal

22

1

1,2

1,4

1,6

1,8

2

2,2

2,4

0 500 1000 1500 2000 2500

VoD [mV]

Ris

e t

ime

[n

s]

GmO5GmBO1GmBOs1

45 mVpp 696 mVpp 1.848 Vpp

23

IV. ACTA3: frequency response

• Negligible non-linearity linearity performance for VoD < 2 Vpp

• BW bit smaller than expected (300 MHz): 250 MHz

BW given by Rd·CL

Underestimation of CL?

Process variation of Rd?

23

Gain for different Peak to Peak VoD (GmBO5)

0,00

5,00

10,00

15,00

20,00

25,00

30,00

10,00 100,00 1000,00

Frequency [MHz]

Ga

in [

dB

]

150 mVpp

300 mVpp

600 mVpp

1 Vpp

1.5 Vpp

2 Vpp

24

IV. ACTA3: frequency response

BW of GmBO1 is even larger Additional buffer !

300 MHz BW for ACTA3 + NECTAR0 input buffer Need a very careful Rd

tuning BW vs stability

Environment more controlled Same die Postlayout simulation

24

GmBO5 vs GmBO1 (600 mVpp)

0,00

5,00

10,00

15,00

20,00

25,00

30,00

10,00 100,00 1000,00

Frequency [MHz]

Gai

n [

dB

]

BO5

B01

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd1

Rd1

GmBO1

Rd1 300 for 1 pF (aprox) Rd2 84 for 4-5 pF (aprox) New buffer

(same OpAmp NECTAr0)

+

-

+

-

Rd2

Rd2

Emulation of the NECTAr0 input buffer

Voltage Gain

0,0E+0

5,0E-1

1,0E+0

1,5E+0

2,0E+0

2,5E+0

0,0E+0 5,0E-2 1,0E-1 1,5E-1

Vin

Vo

ut

Charge Gain

0E+0

1E-9

2E-9

3E-9

4E-9

5E-9

6E-9

7E-9

8E-9

9E-9

0,0E+0 5,0E-1 1,0E+0 1,5E+0 2,0E+0 2,5E+0

Vpcal

Qo

ut

25

IV. ACTA3: linearity

• Good linearity performance (< 1% for > 1 Vpp, < 5% up to 2 Vpp)

• Trade-off between linearity and power consumption

25

Relative charge error for different transconductor tail current

-5,0

-4,0

-3,0

-2,0

-1,0

0,0

1,0

2,0

3,0

4,0

5,0

0,0 0,5 1,0 1,5 2,0

Vout [Vpp]

Re

lativ

e r

esi

du

es

[%]

6 mA

4.8 mA

3.6 mA

30 mW

25 mW

20 mW

26

DC offset is controlled by the current “Ibof”

IV. ACTA3: Offset generation: GmBO5

VoD as function of Ibof

-1,6

-1,1

-0,6

-0,1

0,4

0E+0 1E-8 2E-8 3E-8 4E-8 5E-8

t [S]

Vo

D [

V]

10u

50u

99u

149u

197u

249u

304u

366u

398u

462u

VoL & VoH as function of Ibof

0

0,5

1

1,5

2

2,5

0E+0 1E-8 2E-8 3E-8 4E-8 5E-8

t [S]

Vo

L &

Vo

H [

V]

VoH 10u 50u

99u 149u

197u 249u

304u 366u

398u 462u

VoL 10u 50u

99u 149u

197u 249u

304u 366u

398u 462u

27IV. ACTA3: Offset generation: transfer function

Voffset vs. Ibof

-1600

-1400

-1200

-1000

-800

-600

-400

-200

0

0 100 200 300 400 500

Ibof (uA)

Vof

fset

(m

V)

BO5

BO1

BOs1

Similar behaviour for GmBO1 and GmBOs1

Pulse Gain

15

16

17

18

19

20

21

0 10 20 30 40 50 60 70 80

Temperature [C]

No compensation

Compensation

28

IV. ACTA3: temperature compensation

• Controlling temperature dependence of the gain Transconductor TC is about -0.2%/C Compensated by adjusting the TC of the current (Icf) controlling

floating voltage source Final TC -0.05 %/C (1% for 20 C variation in one night)

• Band gap current reference (Ib) with TC + 180 ppm/C

28

-0.24%/C

-0.06%/C

100

110

120

130

140

150

160

170

180

190

200

0 10 20 30 40 50 60 70 80

Temperature [C]

Icf

[uA

]

105

106

107

108

109

110

111

Ib [

uA

]

Icf

Ib

29

IV. ACTA3: noise

• Channel thermal noise of the input differential pair dominates Wideband amplifier: 1/f noise not relevant: use NMOS

Cross-coupling degrades noise performance: gm subtraction

• For input referred series noise < 3 nV/Hz Gm > 5 mS : large K (W) and/or bias offset Vb Tradeoff between noise and large signal handling

• Noise increases with differential pair bias current

29

0,4

0,6

0,8

1

1,2

1,4

3500 4500 5500 6500 7500

Ibias [uA]

Noi

se [

mV

rm

s]

30

IV. ACTA3: single photoelectron response

• Single photoelectron response at PM nominal gain (2·105)– With R5900 PM, not optimal for SPE resolution

– To be done with PM developed for CTA

30

31

I. Introduction

II. The circuit

III. First prototype: ACTA

IV. Second prototype: ACTA3

V. Summary

Outlook

32

V. Summary

• Alternative solution for wideband pulse amplifiers Gain: 20

Bandwidth > 400 MHz for CL < 1 pF

> 300 MHz for CL < 5 pF

Linearity < 1% for 1Vpp and < 3% for 2 Vpp For fast “closed loop” amplifiers, linearity is usually limited by slew rate

• Intrinsic BW of the core amplifier (without buffer) > 600 MHz BW > 1 GHz in 130 nm technology ?

• Tuneable: Gain DC offset : ADC interface Linearity vs power conssumption

32

GBW > 6 GHz in 0.35 um CMOS

technology

33

Thank you !

34II. The circuit: HF transconductors

HF transconductors with linearisation by local feedback

Lin. Err. [%]

BW[MHz]

Noise[nV /Hz]

Bias current [mA]

Comments

Simple dif. Pair 2 1000 2.2 4.5 W/L limited by linearity

Dif. Pair with degeneration 1 1000 2.7 4.5 Limited range

Cross coupled (XC) mismatched 3 2000 5.7 4.5 Low Gm/Ibias

XC with offsetWang-Guggenbuhl 0.5 850 3.2 8 High consumption

XC with bias offsetSzczepanski 0.5 1000 2.5 4.5

Accurate control of Gm with bias offset voltage

Adaptative Nedungadi-Viswanathan

Small range

1000 2.5 7.5Small linear range even for

high bias current

LinearizedTransconducor

Large swing I to V conversion

35Linear amplifier: diff. pair with degeneration

Three stages:

– HF transconductor: source degenerated MOS diff. pair: V to I

– Cascoded common gate amplifier: I to V

– Source follower: low impedance driver (up to 3pF cap. load)Post-layout simulation: 5 GHz GBW and 3% lin error (VoD 1.7 V)

36

Results: linear amplifier: degenerated transconductor

• Working• Blue: input

• Yellow: output

• No ringing

• Fast input pulse• Rise: 300 ps

• Output pulse• Rise time:

• Small signal (< 1V)• 574 ps

• High signal (> 1V)• 1.2 ns

Large Large signalsignal

Small Small signalsignal

37Preliminary results: linear amplifier: degenerated transconductor

• Gain • About 13,5

• Slightly tunnable

• Linear range• About 1.5 V

0

200

400

600

800

1000

1200

1400

1600

1800

0 50 100 150 200

Out

put p

eak

volta

ge [

mV

]

Input peak voltage [mV]

38

III. First prototype: test set-up

• Two test cards• General charact

• Fast pulse generation

• Bias current though stable ref

• S-parameter• Minimal components

• Acquisition• Scope:

• 1.7 GHz

• 20 GS/s

• Probe: diff. 4 GHz

• Test just started• < 1 week

I. Introduction: ACTA3

• Second prototype (ACTA3)– Better linearity

– Low power output driver: – Class AB amplifier

– New version of a SAM OpAmp

– Collaboration with Eric

– Temperature compensation

– Control of DC offset as needed for ADC

39

Amplifier core

Floating voltagesupply Closed loop output drivers

Second prototype (submitted on April)

150

um

300 um

CMOS 0.35umAMS 3 mm2

Submitted: April 2010Received: end July 2010

40

Same gain block as in ACTA New buffer

Based on the same OpAmp used for NECTAR0 input buffers Colaboration with Saclay

Compensation resistor sized to drive outptut pads (4-5 pF load) Not tested for the moment, only to “debug”

II. Blocks in ACTA3: GmB5

Already in ACTA

LinearTransconducor

Resitive Load with regulated

cascode input

+

-

+

-

Rd

Rd

GmB5

Rd for compensation84 for 4-5 pF (aprox)

New buffer(same OpAmp NECTAr0)

41

As GmB5 but gain stage is modified to generate the DC offset required by ADC

Compensation resistor sized to drive outptut pads (4-5 pF load)

II. Blocks in ACTA3: GmBO5

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd

Rd

GmBO5

New buffer(same OpAmp NECTAr0)

Rd for compensation84 for 4-5 pF (aprox)

42

As GmBO5 but the amplifier (Rd1) is adjusted to drive a smaller capacitance:

It should be the case if it is integrated in the analogue memory chip An additional buffer is added to emulate the NECTAr0 input stage and test the chain

II. Blocks in ACTA3: GmBO1

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd1

Rd1

GmBO1

Rd1 300 for 1 pF (aprox) Rd2 84 for 4-5 pF (aprox) New buffer

(same OpAmp NECTAr0)

+

-

+

-

Rd2

Rd2

Emulation of the NECTAr0 input buffer

43

As GmBO1 but the buffer is replaced by a fully differential amplifier: Subtract common mode signals as soon as possible (CMRR, PSRR)

II. Blocks in ACTA3: GmBOs1

LinearTransconducor

+ Offset circuit

Resitive Load with regulated

cascode input

+

-

+

-

Rd1

Rd1

GmBOs1

Rd1 300 for 1 pF (aprox) Rd2 84 for 4-5 pF (aprox)

Differemtial amplifier

+

-

+

-

Rd2

Rd2

Emulation of the NECTAr0 input buffer

44

Second order response effects in the shape? (small…)

III. Pulse shape: GmBO1

45

Second order response effects in the shape? (small…)

III. Pulse shape: GmBOs1

46III. Pulse shape: rise time vs amplitude

1

1,2

1,4

1,6

1,8

2

2,2

2,4

0 500 1000 1500 2000 2500

VoD [mV]

Ris

e t

ime

[n

s]

GmO5GmBO1GmBOs1

47

A current control Ibfol has to be set to > 30 uA to be sure that the class B current boost is off at the quiescent state

IV. Behaviour of the new buffer: class B boost control

48IV. Behaviour of the new buffer: bias current (buffer driving 5 pF)

Ibb=10uA

Ibb=33 uA

Ibb=66uA

Ibb=104uA

Ibb=152uA

Ibb=195uA

Ibb=264uA

Bias current (4*Ibbpp):If too low (< 75uA for 5pF, <45uA for 1 pF) GBW is too lowIf too high (>200uA) phase margin too low

49

Nice first order response with little non-linearity up to 2 V, but… However BW is only 200 MHZ

Rd was adjusted to have 300 MHz !!! With an external Cload of 3 pF + extracted capacitances including pads

V. Bandwidth: GmBO5

Gain for different Peak to Peak VoD (GmBO5)

0,00

5,00

10,00

15,00

20,00

25,00

30,00

10,00 100,00 1000,00

Frequency [MHz]

Ga

in [

dB

]

150mV

300mV

600mV

1 V

1.5 V

2 V

50

It seems that the BW is dominated by the pole Rd*Cload After some surgery it was possible to measure the BW with shorter PCB traces: increases to 250 MHz The response looks like a first order response (up to 500 MHz)

Possible explanation External Cload is larger than expected Process variation effects in R and C

V. Bandwidth: GmBO5

Gain for short and long traces (300 mVpp)

5,00

10,00

15,00

20,00

25,00

30,00

10,00 100,00 1000,00

Frequency [MHz]

Ga

in [

dB

]

Long

Short

51

Additional confirmation that the BW is limited by the Rd*Cload The BW of GmBO1 is even larger

It has an additional buffer ! Should be possible to achieve > 300 MHz BW for the full amplification

ACTA3 + NECTAR0 input buffer Need a very careful tuning of Rd

BW vs stability Environment more controlled

ACTA3 in NECTAR silicon Postlayout simulation with Eric

Side effect: Underestimation of lin error ? Seems to be enough margin…

V. Bandwidth: GmBO5 vs GmB01

GmBO5 vs GmBO1 (600 mVpp)

0,00

5,00

10,00

15,00

20,00

25,00

30,00

10,00 100,00 1000,00

Frequency [MHz]

Gai

n [

dB

]

BO5

B01

52

Remember that gain depends on two bias current: Ibgm: linearized transconducor differential pair tail current Icf: current controlling floating voltage supply current

“Nominal” condition is Ibgm=1500 uA and Icf=150uA (pulse gain = 16, DC gain = 20)

Results will be shown for this condition Tested for other conditions, results available for other conditions:

Trade-off conssumption / linearty Nominal conssumption is 10 mA

VI. Linearity

53

Amplitude measurement Linearity residue:

< 1 % of the Full Scale (F.S.) for outputs < 1.3 Vpp < 3 % F.S. for output < 1.6 Vpp

VI. Linearity: GmB05

Guany

0,00E+00

5,00E-01

1,00E+00

1,50E+00

2,00E+00

2,50E+00

3,00E+00

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01 3,00E-01

Vin

Vo

ut

Error

-1,50E-001

-1,30E-001

-1,10E-001

-9,00E-002

-7,00E-002

-5,00E-002

-3,00E-002

-1,00E-002

1,00E-002

3,00E-002

5,00E-002

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00

Vout

Err

or

Am

plit

ud

1 % F.S.

Error

-3,00E-01

-2,50E-01

-2,00E-01

-1,50E-01

-1,00E-01

-5,00E-02

0,00E+00

5,00E-02

1,00E-01

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00

Vout

Err

or

Q

Error

-3,00E-01

-2,50E-01

-2,00E-01

-1,50E-01

-1,00E-01

-5,00E-02

0,00E+00

5,00E-02

1,00E-01

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00

Vout

Err

or

Q54

Charge (area) measurement Linearity residue:

< 1 % of the Full Scale (F.S.) for outputs < 1.3 Vpp < 3 % F.S. for output < 1.6 Vpp

VI. Linearity: GmB05

1 % F.S. 1 % F.S.

Differential excitation

Single Ended excitation

Error

-3,00E-01

-2,50E-01

-2,00E-01

-1,50E-01

-1,00E-01

-5,00E-02

0,00E+00

5,00E-02

1,00E-01

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00

Vout

Err

or

Q

55VI. Linearity: GmB01

1 % F.S.

ChargeError

-1,50E-001

-1,30E-001

-1,10E-001

-9,00E-002

-7,00E-002

-5,00E-002

-3,00E-002

-1,00E-002

1,00E-002

3,00E-002

5,00E-002

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00

Vout

Err

or

Am

plit

ud

1 % F.S.

Amplitude

Guany

0,00E+00

5,00E-01

1,00E+00

1,50E+00

2,00E+00

2,50E+00

3,00E+00

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01 3,00E-01

Vin

Vo

utSimilar to GmBO5

Error

-3,00E-01

-2,50E-01

-2,00E-01

-1,50E-01

-1,00E-01

-5,00E-02

0,00E+00

5,00E-02

1,00E-01

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00

Vout

Err

or

Q

Error

-1,50E-001

-1,30E-001

-1,10E-001

-9,00E-002

-7,00E-002

-5,00E-002

-3,00E-002

-1,00E-002

1,00E-002

3,00E-002

5,00E-002

0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00

Vout

Err

or

Am

plit

ud

56VI. Linearity: GmB0s1

1 % F.S.

Charge

1 % F.S.

Amplitude

Slightly worstGain is 10 % higher

Guany

0,00E+00

5,00E-01

1,00E+00

1,50E+00

2,00E+00

2,50E+00

3,00E+00

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01 3,00E-01

Vin

Vo

ut

57IV. ACTA3: Offset generation: effect on linearity and gain

Guany vs. Ibof

4

6

8

10

12

14

16

0 100 200 300 400 500

Ibof (uA)

Gua

ny

BO5

BO1

BOs1

Linearity is ok at the gain plateauOptimal region around Ibof 300 uA