1 vlsi cad flow: logic synthesis, 6.375 lecture 13 by ajay joshi (slides by s. devadas)
TRANSCRIPT
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VLSI CAD Flow: Logic Synthesis,
6.375 Lecture 13
by Ajay Joshi
(Slides by S. Devadas)
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RTL Design Flow
RTLSynthesis
HDL
netlist
logicoptimization
netlist
Library/modulegenerators
physicaldesign
layout
manualdesign
a
b
s
q0
1
d
clk
a
b
s
q0
1
d
clk
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Logic optimization flow
LOGIC EQUATIONS
TECHNOLOGY-INDEPENDENTOPTIMIZATION
FactoringCommonality Extraction
LIBRARYTECH-DEPENDENT OPTIMIZATION (MAPPING, TIMING)
OPTIMIZED LOGIC NETWORK
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Logic optimization flow
LOGIC EQUATIONS
TECHNOLOGY-INDEPENDENTOPTIMIZATION
FactoringCommonality Extraction
LIBRARYTECH-DEPENDENT OPTIMIZATION (MAPPING, TIMING)
OPTIMIZED LOGIC NETWORK
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Why logic optimization?
Transistor count redution AREA
Circuit count redutionPOWER
Gate count (fanout) reductionDELAY
(Speed)
Area reduction, power reduction and delay reduction improves design
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Boolean Optimizations
Find common expressions
Extract and substitute common expression
F =f1= AB + AC + AD + AE + A BC D E
f2= AB+ AC + AD + AF + A BC D F
F =f1= A B+C + D + E( ) + ABC DE
f2= A B+C + D + F( ) + ABC DF
G g1
= B + C + D
f1= A g1
+ E( ) + A E g1
f2= A g1
+ F( ) + A F g1
Involves:Finding common subexpressions.Substituting one expression into another.Factoring single functions.
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Algebraic Optimizations
• Algebraic techniques view equations as polynomials
• Rules of polynomial algebra are used
• For e.g. in algebraic substitution (or division) if a function f = f(a, b, c) is divided by g = g(a, b), a and b will not appear in f / g
• Boolean algebra rules are not applied
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Logic optimization flow
LOGIC EQUATIONS
TECHNOLOGY-INDEPENDENTOPTIMIZATION
FactoringCommonality Extraction
LIBRARYTECH-DEPENDENT OPTIMIZATION (MAPPING, TIMING)
OPTIMIZED LOGIC NETWORK
![Page 9: 1 VLSI CAD Flow: Logic Synthesis, 6.375 Lecture 13 by Ajay Joshi (Slides by S. Devadas)](https://reader036.vdocument.in/reader036/viewer/2022070323/56649dc65503460f94ab9cb7/html5/thumbnails/9.jpg)
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“Closed Book” Technologies
A standard cell technology or library is typically restricted to a few tens of gatese.g., MSU library: 31 cells
Gates may be NAND, NOR, NOT, AOIs.
A
A
A
C
A
B
AB+C
B
C
A
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Standard cell library
• For each cell
• Functional information
• Timing information
• Input slew
• Intrinsic delay
• Output capacitance
• Physical footprint
• Power characteristics
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Sample Library
INVERTER 2
NAND2 3
NAND3 4
NAND4 5
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Sample Library - 2
AOI21 4
AOI22 5
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Mapping via DAG* Covering
• Represent network in canonical form subject DAG
• Represent each library gate with canonical forms for the logic function primitive DAGs
• Each primitive DAG has a cost
• Goal: Find a minimum cost covering of the subject DAG by the primitive DAGs
* Directed Acyclic Graph
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Trivial Covering
Reduce netlist into ND2 gates → subject DAG
7 NAND2 = 215 INV = 10
31 (area cost)
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Covering #1
2 INV = 42 NAND2 = 61 NAND3 = 41 NAND4 = 5
19 (area cost)
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Covering #2
1 INV = 21 NAND2 = 32 NAND3 = 81 AOI21 = 4
17 (area cost)
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Multiple fan-out
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Partitioning a Graph
• Partition input netlist into a forest of trees• Solve each tree optimally• Stitch trees back together
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Optimum Tree Covering
NAND2 3
AOI214 + 3 = 7
INV11 + 2 = 13
NAND22 + 6 + 3 = 11
NAND23 + 3 = 6
NAND2 3
INV 2
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• Partition DAG into a forest of trees
• Normalize the netlist
• Optimally cover each tree
• Generate all candidate matches
• Find optimal match using dynamic programming
DAG Covering steps
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Summary
• Logic optimization is an important step in the design flow
• Two-step flow
• Technology independent optimization
• Technology dependent optimization
• Advantages of logic optimization
• Reduce area
• Reduce power
• Reduce delay
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For more details…
http://csg.csail.mit.edu/u/d/devadas/public_html/6.373/lectures/
Refer to Srinivas Devadas’ slides for 6.373