10 continuous assign v8

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2006 Xilinx, Inc. All Rights Reserved

Data Flow-Level

Modeling


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Data Flow-Level Modeling - 10 - 3 2006 Xilinx, Inc. All Rights Reserved

Objectives

After completing this module, you will be able to:

Combine operators and operands within expressions

Use assign statement to model combinatorial logic

Specify when to use wire (net) data types Specify delay and timing parameters


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Outline

Continuous Assignment

Delay Specification

Summary

Appendix: Gate-LevelModeling


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Behavioral

Data Flow

and Gate

RTL

Switch

f

ORAND_

Levels of Abstraction


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assign Out1 = ((A & Sel[0] & Sel[1]) |

(B & ~Sel[0] & Sel[1]) |(C & Sel[0] & ~Sel[1]) |

(D & ~Sel[0] & ~Sel[1])) ;

Out1

A

B

D

C

Sel[0]Sel[1]

Sel[0]Sel[1]

Sel[0]Sel[1]

Sel[0]Sel[1]

Continuous Assignments

The continuous assignment is re-evaluated whenever any of the

operands (inputs) change value

This code modelsa 4:1 multiplexer


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Implicit Assignment

Statements An implicit, continuous assignment offers a more concise coding

method

module LOGIC_1 (port listing) ;

...wire OUT1 =A & B ;

...

module LOGIC_1 (port listing) ;

...

wire OUT1;...

assign OUT1 = A & B ;

alternatively


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Outline


Delay Specification

Summary



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rise

turn off

fall

1

0

Z

0,x,z

1,x,z

0,1,x

Gate Delays

There are three delay parameters that can be specified to model

gate propagation


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Simulating Delays

Gate delays are listed immediately after the gate instantiation,

preceded by the # symbol

If only one delay is listed, it will apply to all transitions

nand # 4 N1 ( OUT, IN_1, IN_2 ) ;

IN_1

IN_2

OUT

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Simulation Time


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Gate delays are listed immediately after the gate instantiation,

preceded by the # symbol

If three are listed, they will apply to

rise, fall, and turn-off respectively

Modeling Delays

nand # (2, 3, 5) N1 (OUT, IN_1, IN_2) ;

FYI: Any delayspecificationisignoredinsynthesis


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wire # 5 OUT1 =A & B ;

wire # 5 OUT1;. . .

assign OUT1 =A & B ;

alternatively

wire OUT1 ;

assign # 5 OUT1 =A & B ;

or

A

B OUT1

5 ns

Delay Specification

Both regular and implicit assignment statements can include a

delay specification

This models the propagation delay for the gate; ignored during

synthesis


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module COUNT3 ( inputCLK, RST, output[2:0] Q) ;

wire N1, N2 ;

assign N1 = ( Q[0] ^ Q[1] ) ;

assign N2 = ( Q[2] ^ (Q[0] & Q[1])) ;

DFF DFF0 (~Q[0], CLK, RST, Q[0] ) ;

DFF DFF1 ( N1, CLK, RST, Q[1] ) ;

DFF DFF2 ( N2, CLK, RST, Q[2] ) ;

endmodule

module DFF ( inputD, CLK, RST,

outputregQ ) ;

...

Structural and Data Flow Code

Example


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DFF2

DFF1

DFF

0

N1

N2

Q0

Rst

Q2

assign N2 = ( Q[2] ^ (Q[0] & Q[1])) ;

assign N1 = ( Q[0] ^ Q[1] ) ;

Q1

Clk

Rst

Rst

Clk

Clk

COUNT3 Implementation


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Outline


Delay Specification

Summary



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Knowledge Check

What is wrong with the following example and how would you fix it?

Is it synthesizable?

reg CS, RD, WR;

assign #2 CS


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Answer

The previous example contained incorrect usage of wire and reg

wire CS;

reg RD, WR;

assign #2 CS = ADDR[10] & ADDR[9] & ~ADDR[8] & ~ADDR[7];

always @ ( posedge CLK )

begin

RD


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Knowledge Check

Which of the following operators can be used in an assignstatement?

(A) Logical and ( && )

(B) Bitwise and ( & )

(C) Reduction xor ( )

(D) All of the above

When will a continuous assignment be evaluated or re-evaluated? (A) At the start of simulation only

(B) Whenever an input signal changes value

(C) When the target is re-assigned

(D) On the leading edge of the clock signal

Are data flow constructs with delay specifications synthesizable?


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Answers

Which of the following operators can be used in an assignstatement?

(A) Logical and ( && )

(B) Bitwise and ( & )

(C) Reduction xor ( )

(D) All of the above

When will a continuous assignment be evaluated or re-evaluated? (A) At the start of simulation only

(B) Whenever an input signal changes value

(C) When the target is re-assigned

(D) On the leading edge of the clock signal

Are data flow constructs with delay specifications synthesizable? Yes, the construct itself can be synthesized, but the delay specifications

will be ignored for synthesis


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Summary

Data flow modeling describes combinatorial logic

Continuous assignment statements are evaluated whenever a

signal in the expression changes value

The implicit assignment statement combines an internal signaldeclaration and a continuous assignment

Assignment statements can include a delay specification for

behavioral simulation


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Where Can I Learn More?

Application Notes at www.xilinx.com/support/mysupport.htm

Select the Documentation tab

Information at www.accellera.org

Standards group for VHDL and Verilog

Multimedia HDL training at www.technically-speaking.com

Verilog and VHDL multimedia training products

Verilog textbooks and references Starters Guide to Verilog 2001, Mike Cilletti, Prentice Hall, ISBN 0-13-141556-5

Verilog 2001, A Guide, Stuart Sutherland, KLUWER, ISBN 0-7981-2806-6

Verilog HDL by Samir Palnitkar, Prentice Hall ISBN: 0-13-451675-3

Verilog Designers Library by Bob Ziedman, Prentice Hall ISBN:0-13-081154-8

HDL Chip Design by Douglas J. Smith, Doone Publications, ISBN:0-9651934-3-8


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Outline


Delay Specification

Summary



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FYI: Anygate-level model can be synthesized, but the actualgates used

depend on the available primitivesand macrosin the target technology

library

Gate-Level Modeling

Gate-level modeling in Verilog uses predefined primitives. It is

straightforward and intuitive

It is also very detailed in nature, and thus only suitable for small

modules


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and nand

or nor

xor xnor

Gate Types

Verilog predefines the following n-input gate-level primitives:


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buf not

Buffers and Inverters

For buf, not, and most standard gates, inputs of unknown x

or high impedance z usually produce an unknown output in

simulation


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notif1bufif1

bufif0 notif0

FYI: Should be codedformutual exclusivity; forexample, ensuringthat only

one driveris enabledata time

Buffer and Inverter with Enable

Used for driving onto common outputs


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module AND_OR ( inputA, B, C,D, outputZ );

wire SIG1, SIG2 ;

and A1 ( SIG1, A, B ) ;

and A2 ( SIG2, C, D ) ;

or O1 ( Z, SIG1, SIG2 ) ;

....

endmoduleSIG1

ZB

A

D

C

SIG2

Gate Coding

Instance names are optional

Gate output

must be listed first!


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bufif0

bufif0 B1 ( OUT_1, IN_1, CTRL ) ;

IN_1

CTRL

OUT_1

Coding Gates

Gate primitives are referenced by their keyword identifiers, along

with the output and input signals


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Other Considerations

Gates can be described with more than two inputs

Buffer and inverters can have multiple outputs

buf B1 ( OUT_1, OUT_2, IN1 ) ;

and A0 ( OUT_1, IN1, IN2, IN3... ) ;

10 continuous assign v8

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