11 1 university of michigan 1 phoenix: an ultra-low power processor for cubic millimeter sensor...

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1 1 University of Michigan 1 Phoenix: An Ultra-Low Power Processor for Cubic Millimeter Sensor System Motivations Sensor application requires small form factor and long lifetime Both limited by battery - A 1mm 2 zinc/silver battery with 100µAh/cm 2 can provides 177pW for 1 year lifetime Either improve battery or power consumption Minimize standby power (dominating portion of total power) via comprehensive standby strategy Bravo® pH Monitoring System VeriChip TM RFID Tag VeriChip Previous Platform [1]Zhai,etal. [2]H anson,etal. This w ork Com prehensive Sleep Strategy Subthreshold O peration ~pJ PerInst. E active P sleep 34pW ~100nW ~2500X Zhai,etal.[1] H anson,etal.[2] This w ork Tech 0.18um 0.13um 0.18um E/cycle 2.6pJ 3.5pJ 2.8pJ P standby 238nW 154nW 34pW

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11

1

University of Michigan 1

Phoenix: An Ultra-Low Power Processor for Cubic Millimeter Sensor System

Motivations

Sensor application requires small form factor and long lifetime

Both limited by battery - A 1mm2 zinc/silver battery with 100µAh/cm2 can provides 177pW for 1 year lifetime

Either improve battery or power consumption

Minimize standby power (dominating portion of total power) via comprehensive standby strategy

Bravo® pH Monitoring System

VeriChipTM RFID Tag

VeriChip

Previous Platform[1] Zhai, et al.

[2] Hanson, et al.

This work

Co

mp

reh

ens

ive

Sle

ep

Str

ate

gy

Subthreshold Operation~pJ Per Inst.

Eactive

Ps

lee

p3

4pW

~1

00nW

~2

500X

Zhai, et al. [1]

Hanson, et al. [2]

This work

Tech

0.18um

0.13um

0.18um

E/cycle

2.6pJ

3.5pJ

2.8pJ

Pstandby

238nW

154nW

34pW

22

2

University of Michigan 2

CPU52x40DMEM

64x10IMEM

128x10IROM

PowerManagement

I/OClock

Generator

Com

press/D

ecom

press

TimerTemperature

Sensor

System Bus

Power gated

Partially gated Not gated

...

...

915um

915u

mComprehensive standby strategy

Optimum technology selection L=0.18µm, Vdd=0.5V given performance, duty

cycle and memory requirements

Unique power gating approach SVT MOSFET with W=0.66µm L=0.5µm

Tradeoff performance with standby power

Ultra-low leakage sub-VTH SRAM design 7.1fW/bit custom SRAM cell

Adaptive power gating for dynamic standby power management

Power gating for peripherals

Robust ultra-low Vdd ROM design full static NAND ROM design for robustness

Simple ISA with compression support Narrow instruction for small IMEM footprint

Ultra-low power peripheral unit design Slow watchdog timer

Low power temperature sensor

33

3

University of Michigan 3

Active Mode Sleep Mode0

20

40

60

80

100

CPU

IROM

IMEM

DMEM

2.8pJ/cycle, 297nW 29.6pW

Timer

IROM

IMEM

DMEM

CPU[%]

time

297nW

29.6pW

Pow

er C

onsu

mpt

ion

1 9 m s1 0 m i n

2 0 0 0

i n s t

Results

29.6pW for standby mode and 2.8pJ/cycle for active mode

100kHz at Vdd=0.5V

1mm2 in 0.18µm CMOS technology

2000 instructions for every 10min gives Eactive=5.6nJ, Estandby=17.8nJ

Theoretically 15 year lifetime with a 1mm2 thin film lithium battery

Future works – designing more low power sub-modules including communication link, improve existing modules, variation compensation method, and system-level integration

Thank you!