115 december 2003luciano musa radiation tests of the tpc fee cern, 30 august 2004 luciano musa –...

115 December 2003 Luciano Musa

Radiation tests of the TPC FEE

CERN, 30 August 2004

Luciano Musa – CERN / PH - ED

Content

• System overview

• Radiation Levels at the TPC

• Radiation Facilities and Test Setup

• Characterization (TID and SEE) of the FEC components

• Custom (ALTRO and PASA)

• COTS (LDO, VREF, AMPLIFIERS, TRANSCEIVERS, BUFFERS, CAP., etc.)

• FPGA (ALTERA ACEX1K30)

• Characterization of RCU see the talks of D. Röhrich and C. Soos


Lo

cal M

onito

ra

nd

Co

ntr

ol BOARD

Controller

RCU

DCS ( 1 MB/s )

DDL ( 200 MB/s )

COUNTING ROOM

Each of the 36 TPC Sectors contains 6 Readout Partitions

COTS, FPGA

ON DETECTOR

Overall TPC: 4356 Front End Card 216 RCUs

Bu

s c

on

tro

ller

( c

on

f. &

R/O

)

FEC128 ch

1

1

2

2

12

13

DCS int.(Ethernet)

DAQ int.(DDL-SIU)

Trigger int.(TTC-RX)

FEC128 ch

FEC128 ch

FEC128 ch

FEC128 ch

FEC128 ch

CUSTOM, COTS, FPGA

DE

TE

CT

OR

TTC optical Link

(Clock, L1 and L2 )

Data Proc.and Memory

System Overview

PASSIVE COMPONENTScapacitors and resistors


Sum Flux with Ekin > 10MeV (cm-2 s-1)

Layers 1 2 3 4

absorber side 384 268 187 129

Non-absorber side 245 149 112 81

TID

@ TPCin 1.6 krad

@ TPCout 0.22 krad

Georgios Tsiledakis, GSI

Simulation with 4 scoring regions

Radiation Levels at the TPC

Agreement with A, Morsch and B. Pastircak

ALICE-INT-2002-28 Version 1.0


Radiation Facilities and Test Setup

Test (I)

2002

DUT Collimator

Beam Type: 65 MeV protons

Proton Flux: 1·108 , 5·108 p cm-2 s-1

100 krad in 30 min at this flux

Labview ServerX Server with Labview

2 m

EthernetLine

Labview Monitor

Test Bench

Scintillator

Attenuator

Test at UCL, Louvain-la-Neuve, Belgium


Test Setup for ALTRO and LDOPC Monitors

status and

errors

Continuous current

monitoring

Analog card

Regulator test

on daughtercard


Test (I)

2002


CollimatorALTRO chip

Regulator Test

Fixture

Test (I)

2002



PASA 0.35 µm CMOS

EPROM (CMOS)

Clock Driver0.18 µm CMOS

Analog BufferCMOS


Test (I)

2002

FRONT END CARD


GTL Transceivers(BiCMOS)

VoltageReference(Bipolar)


Test (I)

2002

FRONT END CARD


Collimator

Test Card usedto monitor

current


Test (I)

2002



Test (II)

2003 - 2004

• Oslo Cyclotron

25 and 28 MeV external proton beam flux ~ 107 – 108 protons/s cm² Beam profile: spot 1.5cm x 1.5cm

Test (III)

2004

• TSL (Uppsala)

38 and 180 MeV external proton beam flux ~ 107 – 108 protons/s cm² Beam profile:

• spot 3cm



Test Setup for COTS and FPGA

Test (II) and TEST (III)

2003 - 2004


Tested Parts (1/2)

Name Type Technology No. Parts TID (krad)

ALTRO-16 ADC + DP CMOS 4 312

PASA Shaping/Amp CMOS 4 96

MIC39151 Volt. Reg. Bipolar 12 30

MIC29371 Volt. Reg. Bipolar 10 30

TC1173 Volt. Reg. Bipolar 6 40

LP3962/61 Volt. Reg. CMOS 3 30

TI757 Volt. Reg. CMOS 2 30

OPA4364 OpAmp Bipolar 5 30

AD8604 OpAmp CMOS 8 30

MAX4254 OpAmp CMOS 1 30

TC1265 Ref. Volt. CMOS 2 84

LM4140 Ref. Volt. Bipolar 10 30


Tested Parts (2/2)

Name Type Technology No. Parts TID (krad)

LM4040 / 41 Ref. Volt. Bipolar 10 30

LM385 Ref. Volt. Bipolar 10 30

STM-TS821 / 2 Ref. Volt. CMOS 4 30

GTL16612 Transceiver Bi-CMOS 8 48

MPC9109 Buffer CMOS 6 100

BAT54 Diode Bipolar 4 30

MMBT2222A BJT Bipolar 4 30

Electrolytic Cap Capacitors Tantalum 20 100

EPC1441 EPROM CMOS 10

ACEX1K30 FPGA CMOS 5 100

TOTAL NUMBER OF TESTED PARTS 146


Custom Components - ALTRO

Register Check

2004 bits

PM Check

163840 bits

DM Check

655360 bits

Write Pattern

in Regs and Mem

Reset ALTRO

ALTRO Status

Register Check

Current Check

ADC Signal

Check

Resetrequested

Y

N

Start

ALTRO Test Loop


analog current

standbydigital current

register errors

PM errors

DM errors

SEU errorsand other

protocol errors

ADC spikesand SEU

error counters

test phase

power status


ALTRO Test Program


Memory Error Cross Section: 1.10·10-14 cm2 bit-1

Register Error Cross Section: 7.02·10-14 cm2 bit-1

Hamming Error Cross Section: 7.50·10-14 cm2 bit-1

47%53% 1 > 0 0 > 1

Error Cross Section

• Slightly more flips from 1 to 0 than from 0 to 1

• Digital current increases with dose (leakage

increases)

• Analog current stays the same

• ADC bit flips very rare

• Small spikes in analog part of ADC above 160 krad

Observations

Digital current vs Dose

0

20

40

60

80

100

120

140

160

180

0 100 200 300

Dose (krad)

curr

en

t (m

A)

total current

digital standby current

bit-flip ratioTest Results



• After 2 weeks at room temperature: 43 mA standby current (+13.5% over total)

• After 3 months at room temperature: back to normal

• At a low flux, annealing and damage may compensate

Annealing

All 4 irradiated chips continue to work today


Test Results


RegistersPedestalMemory

DataMemory

HammingMachines

SEU per hour

MTBF

0.023 0.36 1.43 0.0007

36 hours 168 minutes 42 minutes 58 days

For a sub-sector equipped with 200 ALTROS (1 RCU)

Worst-case figure

Innermost Readout Partition @ absorber side

System Level Consequences



PASA Test Results

• No variations in current consumption

• No variations in baseline level

• No variations in gain

• Negative spikes observed frequently (due to high flux)

Test Procedure

• Monitoring of current consumption

• Repetitive acquisition of output of 16 ch.

• Monitoring of baseline value

• Monitoring of gain

• Automatic spike detection

Test Results (TID = 96 krad)Negative spikes in the baseline

0

70

AD

C

CO

UN

TS


COTS – Voltage Regulators

beamstopped

Switch-offstill works

MIC39151

8 krad

MIC39151 died after 30 krad (switch-off still possible)

MIC39151 still usable for the TPC. Batch dispersion might be an issue

50 krad25 krad


COTS – Reference Voltage Generators

2.44

2.46

2.48

2.5

2.52

2.54

2.56

2.58

2.6

2.62

0:0

0:0

0

0:0

0:1

6

0:0

0:3

2

0:0

0:4

8

0:0

1:0

4

0:0

1:2

0

0:0

1:3

6

0:0

1:5

2

0:0

2:0

8

0:0

2:2

4

0:0

2:4

0

0:0

2:5

7

0:0

3:1

3

0:0

3:2

9

0:0

3:4

5

0:0

4:0

1

0:0

4:1

7

0:0

4:3

3

0:0

4:4

9

0:0

5:0

6

0:0

5:2

3

0:0

5:3

9

0:0

5:5

4

0:0

6:1

1

0:0

6:2

8

0:0

6:4

4

0:0

7:0

0

0:0

7:1

7

0:0

7:3

3

0:0

7:4

9

0:0

8:0

7

0:0

8:2

5

0:0

8:4

2

0:0

8:5

8

0:0

9:1

4

Series1

1.225

1.226

1.227

1.228

1.229

1.23

1.231

1.2320:0

0:0

0

0:0

0:2

7

0:0

0:5

4

0:0

1:2

1

0:0

1:4

8

0:0

2:3

1

0:0

2:5

9

0:0

3:2

6

0:0

3:5

3

0:0

4:2

0

0:0

4:4

7

0:0

5:1

5

0:0

5:4

4

0:0

6:1

1

0:0

6:3

8

0:0

7:0

5

0:0

7:3

3

0.0

056

0:0

8:2

8

0:0

8:5

5

0:0

9:3

5

0:1

0:0

2

0:1

0:3

1

0:1

0:5

8

0:1

1:2

5

0:1

1:5

3

0:1

2:2

0

0:1

2:4

8

0:1

3:1

6

0:1

3:4

3

0:1

4:1

1

0:1

4:3

8

Series1

(1% output variation @ 45Krad)

(~21KRad/min)

(output stable within 0.3 %)

LM4041 (1.2V)

LM4040 (2.5V)

Vo

lta

ge

Vo

lta

ge

Time (hh:mm:ss)


COTS – Operational Amplifier

TI OPA4364

0

0.5

1

1.5

2

2.5

0:00

:00

0:00

:21

0:00

:42

0:01

:03

0:01

:24

0:01

:45

0:02

:06

0:02

:27

0:02

:48

0:03

:08

0:03

:29

0:03

:50

0:04

:11

0:04

:32

0:04

:53

0:05

:14

0:05

:35

0:05

:56

0:06

:17

0:06

:38

0:06

:59

0:07

:20

0:07

:41

Exposition Time ( ~21 KRad/min)

Ou

tpu

t V

olt

age

Series1

(Output stable ‘till ~140 Krad)


BJT MMBT2222ALT1

0

0.020.04

0.060.08

0.10.12

0.14

0:00

:00

0:00

:51

0:01

:41

0:02

:32

0:03

:22

0:04

:13

0:05

:03

0:05

:54

0:06

:44

0:07

:35

0:08

:26

0:09

:16

0:10

:07

0:10

:57

0:11

:48

0:12

:39

0:13

:29

0:14

:21

0:15

:12

0:16

:04

0:16

:55

0:17

:46

0:18

:40

0:19

:34

Exposition Time ( ~ 21KRad/min)

Vce

-sat

Series1(variations of 10 % in Vce-sat every ~140KRad)

COTS – Bipolar Transistor


AVX 15 / 10

0

0.5

1

1.5

2

2.5

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

Before irrad

After irrad

AVX 15 / 10

0

0.5

1

1.5

2

2.5

1 4 7 10

13

16

19

22

25

28

31

34

37

40

43

46

49

52

55

58

61

64

67

70

73

76

79

82

85

88

91

Before irrad

After irrad

(up to 120KRad)

COTS – Tantalum Capacitors

Vo

lta

ge

Vo

lta

ge

Time (ms)

Time (ms)

15uF / 10 V


COTS – Other Results

• GTL16612 max TID > 80 krad SEU cross section 1.15·10-12 cm2 bit-1

• MPC9109 max TID > 50 krad SEU cross section 1.3·10-12 cm-2 bit-1

• EPC1441 preserves configuration at TID > 20krad


COTS – FPGA (ACEX1K30)

TID is not a problem at the TPC levels

Two types of concern● Upsets in configuration SRAM cells● Single bit-flips in register elements (can be avoided by design)

The ACEX1K30 offers no direct readout of configuration SRAM● Indirectly detection of configuration upset through the internal logic


11001

11101 01001

10001

11000

1101100111

10111 00011

00101

00110

01111

Finite State Machine (FSM) protected by Hamming encoding

Basic principle

00000

10000 01000

00100

00010

00001

State A

State BState C

X

Returns to the associatedstate if there is no external signal

producing a state transition

The arrival of Xproduces the

transition from A to B

1Bit-flip (SEU)

The signal Y producesThe transition form B to C,

Y

01100

Doble Bit-flip

Error

Arquitectura del Chip ALTRO

SEU Protection


Serial Slow Control Network

SCSN

FPGA

Data in Data out

Serial Slow Control Network

SCSN

0000000100000001000000010000000100000001000000010000000100000000000000...0000000

0000000100000001000000010000000100000001000000010001000100000000000000...0000000

A fixed pattern is shifted through and compared for setups when read out.


Upset detection in ACEX devices



Device Conf. Bits Cross Sec

ACEX1K30 470 000 4•10-11 cm2

Error rate per run (4 hours) Error rate per run

per device per system

FEC 1.15*10-4 0.52

Detection of configuration loss by BIST

FPGA reconfigured by on board EPROM

115 december 2003luciano musa radiation tests of the tpc fee cern, 30 august 2004 luciano musa –...

Documents