12-bit 32 channel 500msps low latency adc

Pacific MicroCHIP Corp.1

12-bit 32 Channel 500MSps

Low Latency ADC

Dalius Baranauskas

Anton Karnitski

Award Number: DE-SC0017213

Summary of year 1 progress, Ph II project


Presentation Outline

• The Company, its Specialization/Expertise

• A List of Successful Projects

• Used IC Fabrication Technologies

• Current Project - 12-bit 32 Channel 500MSps

Low Latency ADC:

• Relevance to the NP Program

• Project Goals

• Chip Description

• Project Schedules and Milestones

• Plans for the Future


The Company

• Pacific MicroCHIP Corp. was incorporated in 2006.

• It is headquartered in Culver City, California.

• Main focus of the company – providing IC/ASIC design

services and turnkey solutions.

Office in Culver City, CA


Our OfferingsIC/ASIC Design Services:

• Circuit Design (analog, RF/mixed, digital)

• Simulation

• Physical Design

• Chip Assembly

Turnkey Solutions:

• IC Design

• Chip Fabrication Logistics

• Package Development (involving a 3rd party)

• Chip Packaging (involving a 3rd party)

• PCB Development for Testing/Eval. (involving a 3rd party)

• Testing/Characterization (an in-house lab)

• Delivery of Chips, Parts and Board Level Solutions


Core Expertise

• Analog (ADC/DAC, CTF, VGA, BG, LDO)

• Mixed Signal (PLL, CDR, SerDes, MDrv, TIA)

• RF (LNA, Mixer/Modulator, PA)

• Digital (Verilog, RTL, P&R, Timing Closure,

DFT, Verifications)

• Layout (SiGe/CMOS) down to 7nm


A List of Successful Projects• 12-bit 32 Channel 500MSps Low Latency ADC Being presented.

• A spectrometer ASIC 4GHz BW, 6-bit@8GSps, 8K frequency bins.

• A correlation radiometer ASIC 2xI/Q inputs, 2-bit@20GSps, cross-correlation within 16 bands.

• 20GS/s 6-bit ADC ASIC.

• An 8-bit up to 56GS/s ADC.

• A fiber-optic TRx ASIC for 200Gbps. Includes 4xADC/DAC (8-bit@56GSps).

• An 8-bit up to 64GS/s DAC for fiber optic >400Gb/s Tx.

• A laser controller ASIC for 100-400Gbps fiber optic modules. Includes 12-14-bit DACs, ADCs, TIAs,

PIDs, PWM, etc.

• A low power RF TRx ASIC for medical pill endoscopes. Tx 433.8MHz (1mA), Rx 13.56MHz (2mA).

• A low Power Rx front end (TIA) for up to 4x28Gb/s NRZ realized in 130nm SiGe.

• A low power up to 4x32Gb/s NRZ MZ modulator driver realized in 180nm SiGe.

• A low power up to 2x56Gb/s PAM4 MZ modulator driver realized? in 180nm SiGe.

• A cross-correlator ASIC including 128 2-bit 1GSps ADCs and a 64x64 cross-correlator matrix.

• A dual transceiver ASIC with eFEC/FEC (5M gates) for 8.5Gb/s to 11.3Gb/s fiber optic networks.

• An EDC receiver with an analog Viterbi for fiber optic networks from 8Gb/s up to 11.3Gb/s.

• A UWB transceiver in 180nm SiGe.

Pacific MicroCHIP Corp.

IC Technologies Used – down to 7nm node

7

- indicates previously used node

Mixed Signal


Relevance to the NP Program

8

NP detectors require thousands of signal processing channels => need for

digitizers to:

• Shrink in size - our ASIC combines independent 32 ADCs per chip.

• Reduce power consumption - we offer 25mW per ADC.

Upgrades in these systems demand for:

• Digitizing accuracy - our ADC features 12-bit resolution.

• Adequate sampling speed - our ADC features 0.5GS/s.

• Low conversion latency - we offer 8ns.

Targeted specific applications:

• Low latency particle beams control systems.

• Imaging and spectroscopy systems for gamma-ray detectors.

• Multichannel detectors based on tube and silicon photo multipliers.


Project Goals for Phase II

9

• Design circuits and layout for the ADC ASIC.

• Fabricate the chip.

• Develop a special chip carrier.

• Package the chips.

• Develop a test PCB and a DUT socket.

• Develop a GUI and a test bench.

• Test and characterize the ADC ASIC.

• Prepare a datasheet for marketing.

• Submit deliverables to the DoE.

Within this project we will:



Low Latency ADC

10

• 32 independently operated ADC

channels

• 500 MS/s sampling rate

• 0.6Vpp differential input swing

• 10-bit ENOB

• 250MHz Input signal bandwidth

• -40C..+125C temperature range

• 25mW/channel power consumption

(with interface)

• JESD204B output data interface

• 8ns latency (direct ADC data output mode)

• 32x8Gb/s output data rate

• I2C interface for ASIC control

• 8.7mm2 estimated ASIC layout footprint

• Solder bumped die in a BGA package

• 28nm CMOS technology

Specifications Include:



Low Latency ADC

11

SAR 5b

1GS/s

SAR 8b

0.5GS/sAmp

Clock generator

Up to

250MHz

100Ω Diff

SERIALIZER 16:1

SERIALIZER 10:1

500MS/s 12b ADC [0]

500MS/s 12b ADC [1]

...

500MS/s 12b ADC [31]

JESD204B

Frame

8b/10b Encoder

DATA

MUX

Digital correction

5b 8b

4b Header

12b

DRV

Data Interface [0]

Data Interface [1]

Data Interface [31]

...

CP

PFD

LPFOSC

MUX4GHz

100Ω Diff

OSC

/R

[1..15]

/N

[2..63]

16GHz

16GHz PLL

Fref=[1GHz/2GHz]

/5/8

0.8GHz0.5GHz

/R

[1..15]

4GHz

I2C Interface

Control Registers

8Gbit/s

8Gbit/s

8Gbit/s

8Gbit/s

Reference

voltages and

currents

generator

CL

K

Dis

trib

uti

on

CPU

Temperature

sensor/4

ASIC Block Diagram


12-bit 500MSps ADC Core Block Diagram

• Two-times time-interleaved ADC core

• Sampling clock skew adjustment

• Two-stage pipelined SAR architecture

• Programmable residue Amp gain

• Programmable ADC FS range

• Bootstrapped input switches

• 1-bit redundancy between ADC stages

SAR

logic

dout[12:8]CDAC

5b

INp

cmp1_p

cmp1_n

+

-

CMP

c1[4:0]

clk1_cmp

8x

5bit

SAR ADC

SAR

logic

dout[7:0]CDAC

8b

cmp2_p

cmp2_n

+

-

CMP

c2[7:0]

clk2_cmp8bit

SAR ADC

DIGITAL

CORRECTION

CLOCK

GENERATOR

REFERENCE

VOTLAGE

GENERATOR

SubADC1: 12bit 250Ms/s Two-stage Pipelined SAR ADC

D[11:0]RESIDUE

AMP

INn

SubADC 2: 12bit 250Ms/s Two-stage Pipelined SAR ADC

4ns

TRACK CONVERSION RESIDUE TRANSFER

OFF AMPLIFICATION

CONVERSION TRACKING

STAGE1 (5b)

RESIDUE AMP

STAGE2 (8b)

2ns

TRACK CONVERSIONRESIDUE TRANSFER

OFFAMPLIFICATION

CONVERSIONTRACKING

STAGE1 (5b)

RESIDUE AMP

STAGE2 (8b)

Sub-ADC 1

Sub-ADC 2

0.5ns 1.5nsPing-Pong


ASIC Top-level Layout

Chip’s periphery:

32 independent ADC channels

located in 2 circles

Central part:

• PLL with a clock tree

• Temperature sensor

• CPU for calibration

• I2C control interface

Single ADC channel

Digital

registers

Sync stage

Output data

interface


ASIC Bump Map

0.15

mm

0.20

mm

2.95 mm

2.9

5 m

m

LEGEND:

ANALOG SIGNAL INPUTS( 100 Ω

DIFFERENTIAL, BANDWIDTH > 1GHz)

SAMPLING FREQUENCY CLOCK INPUTS, 2GHz,

100 Ω DIFFERENTIAL, BANDWIDTH >2GHz

JESD OUTPUT INTERFACE TX SUPPLY 1.2V

ADC CORE SUPPLY 0.9V

DIGITAL IO PAD SUPPLY 1.8V

VSS GROUND

REXTOUTPUT FOR EXTERNAL RESISTOR

(DC CURRENT <1mA)

ANALOG TEST OUTPUT

(DC CURRENT <1mA / DC VOLTAGE)

DO_NCML DATA OUTPUT (UP TO 8GBit/s,

BANDWIDTH >6GHz, 100 Ω DIFFERENTIAL)

SYSREF_PSYSREF_N JESD204B INTERFACE RELATED SIGNALS

100Ω DIFFERENTIAL LVDS <1GHz)

SDAI2C INTERFACE RELATED SIGNALS

SCLADDR0

NO BUMP

VDDPAD

VSSPAD

DO_P

SYNCJESD204B INTERFACE RELATED SIGNAL

(SINGLE ENDED CMOS PULSE)

RST SE TCK

REFCLK_PREFCLK_N

IN_NIN_P

CLK_P CLK_N

VDD_IO

VDD

ATEST_PATEST_N

FREF PLL REFERENCE FREQUENCY INPUT

VCO_NVCO_P

FS_NFS_P

DIVIDED VCO FREQUENCY OUTPUT

EXTERNAL SAMPLING FREQUENCY

(BYPASS PLL)

VDD_PLL PLL SUPPLY VOLTAGE

FS_N

FS_P

ADDR0

ADDR1 RST

TM

SESCL

TCK

SDA

SYNC

ADDR2REFCLK

P

REFCLKN

SYSREFP

SYSREFN

REXT

ATEST_P

ATEST_N VSS

VDDGNDVDDPAD

VSSPAD

BIAS/TEST PLL

VCO_NVCO_PVDD_VCO

FREF

VDD_PLLVSS

VDD_PLL

VSS

GND

IN_NIN_P VDD

GND VDD_IOGND

IN_N IN_P

DO_PDO_N

VDD

GNDVDD_IO GND

GND

IN_NIN_P

GNDGND

GND

IN_N IN_P

DO_PDO_N

GNDGND

VDD

VDD_IO

VDD

VDD_IO

DO_P DO_N

DO_P DO_N

CH1

CH2

CH7

CH8

GND

IN_NIN_P VDD

GND VDD_IOGND

IN_N IN_P

DO_PDO_N

VDD

GNDVDD_IO GND

GND

IN_NIN_P

GNDGND

GND

IN_N IN_P

DO_PDO_N

GNDGND

VDD

VDD_IO

VDD

VDD_IO

DO_P DO_N

DO_P DO_N

CH3

CH4

CH9

CH10

GND

GND

IN_NIN_P VDD

GND VDD_IOGND

IN_N IN_P

DO_PDO_N

VDD

GNDVDD_IO GND

GND

IN_NIN_P

GNDGND

GND

IN_N IN_P

DO_PDO_N

GNDGND

VDD

VDD_IO

VDD

VDD_IO

DO_P DO_N

DO_P DO_N

CH5

CH6

CH11

CH12

GND

IN_NIN_P VDD

GND VDD_IOGND

IN_N IN_P

DO_PDO_N

VDD

GNDVDD_IO GND

GND

IN_NIN_P

GNDGND

GND

IN_N IN_P

DO_PDO_N

GNDGND

VDD

VDD_IO

VDD

VDD_IO

DO_P DO_N

DO_P DO_N

CH13

CH14

CH17

CH18

GND

GND

IN_NIN_P VDD

GND VDD_IOGND

IN_N IN_P

DO_PDO_N

VDD

GNDVDD_IO GND

GND

IN_NIN_P

GNDGND

GND

IN_N IN_P

DO_PDO_N

GNDGND

VDD

VDD_IO

VDD

VDD_IO

DO_P DO_N

DO_P DO_N

CH15

CH16

CH19

CH20

GND

GND

IN_N IN_PVDD

GNDVDD_IO GND

IN_NIN_P

DO_P DO_N

VDD

GND VDD_IOGND

GND

IN_N IN_P

GND GND

GND

IN_NIN_P

DO_P DO_N

GND GND

VDD

VDD_IO

VDD

VDD_IO

DO_PDO_N

DO_PDO_N

CH27

CH28

CH21

CH22

GND

IN_N IN_PVDD

GNDVDD_IO GND

IN_NIN_P

DO_P DO_N

VDD

GND VDD_IOGND

GND

IN_N IN_P

GND GND

GND

IN_NIN_P

DO_P DO_N

GND GND

VDD

VDD_IO

VDD

VDD_IO

DO_PDO_N

DO_PDO_N

CH29

CH30

CH23

CH24

GND

GND

IN_N IN_PVDD

GNDVDD_IO GND

IN_NIN_P

DO_P DO_N

VDD

GND VDD_IOGND

GND

IN_N IN_P

GND GND

GND

IN_NIN_P

DO_P DO_N

GND GND

VDD

VDD_IO

VDD

VDD_IO

DO_PDO_N

DO_PDO_N

CH31

CH32

CH25

CH26

INTERFACE / CPU

Clock distribution network

Clock arrival time to ADC channels is matched to support data alignment



Low Latency ADC Power Budget

15

ADC STAGE1 [5bit 250MS/s]

1.1

RESIDUE AMPLIFIER4.2

ADC STAGE2 [8bit 250MS/s]

0.9

Sub-ADC powerbudget, 6.2mW

SUB-ADC1 [12bit 250MS/s]

6.2

DATA SYNC0.17

SUB-ADC2 [12bit 250MS/s]

6.2CLOCK

GENERATOR0.36

OUTPUT DATA INTERFACE

11.4

OFFSET CANCELLATION1.05

ADC channel power budget, 25mW


Expected Part Appearance

BGA 18 x 18 balls, 0.8mm ball pitch Final part, top view

Bottom view

Bypass capacitors

on the chip carrierLid

Note: Images are based on a previously

developed similar BGA package.


# Vendor# of

Channels

Sample

Rate,

MS/s

Power Cons.

per Channel

Architecture/

Latency

1. TI 12-bit ADS52J90 32 40 41mWPipeline/

2.5us

2.TI 12-bit

ADS5403IZAYR1 500 1W

Pipeline/

240ns

3.TI 12-bit

ADS54T04IZAYR2 500 1.15W

Pipeline/

240ns

4.ADI 12-bit

AD9234BCPZRL72 500 1.5W

Pipeline/

240ns

5.Pacific Microchip

Corp. 12-bit*32 500 25mW

SAR/Pipeline/

8ns

Comparison to ADCs Available

on the Market

* Expected performance


Project Milestones and

Deliverables

18


Plans for the Future

What is Beyond Phase II?

19

• End of Ph II - the chip’s prototype is ready.

• Redesign chip based on testing results and the

feedback from the customers.

• Fabricate the final chip.

• Test/evaluate it.

• Prepare chip description and datasheets.

• Organize the ADC ASIC design as an IP block and

advertise it.

• Provide the chip to the DoE community and commercial

customers.


THANK YOU

20

We would appreciate any application ideas and customer

leads for the presented ADC ASIC !

12-bit 32 channel 500msps low latency adc

Documents