12-bit, 80 msps/105 msps/125 msps/150 msps, 1.8 v dual analog-to-digital converter ad9627 · 2019....
TRANSCRIPT
12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
AD9627
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
FEATURES SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @ 150 MSPS SFDR = 84 dBc to 70 MHz @ 150 MSPS Low power: 820 mW @ 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply Integer 1-to-8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features
Fast detect/threshold bits Composite signal monitor
APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G)
GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
06
57
1-0
01
VIN+A
VIN–A
VREF
SENSE
VIN–B
VIN+B
D11A
D0A
CLK+
CLK–
DCOA
DCOB
D11B
D0B
AGND SYNC FD(0:3)B
ADC
ADC
SIGNAL MONITORDATA
AVDD DVDD FD(0:3)A
DRGND
PROGRAMMING DATA
DRVDD
FD BITS/THRESHOLDDETECT
REFSELECT DUTY CYCLE
STABILIZER
MULTICHIPSYNC
FD BITS/THRESHOLDDETECT
SIGNAL MONITORINTERFACE
DCOGENERATION
DIVIDE1 TO 8
SIGNALMONITOR
SPI
CM
OS
OU
TP
UT
BU
FF
ER
CM
OS
OU
TP
UT
BU
FF
ER
SHA
SHA
CSBSCLK/DFS
SDIO/DCS
CML
RBIAS
SMISDO/OEB
SMISCLK/PDWN
SMISDFS
AD9627
NOTES1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1.
PRODUCT HIGHLIGHTS 1. Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/
150 MSPS ADC. 2. Fast overrange detect and signal monitor with serial output. 3. Signal monitor block with dedicated serial output mode. 4. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz. 5. Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic families.
6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.
7. Pin compatibility with the AD9640, AD9627-11, and AD9600 for a simple migration from 12 bits to 14 bits, 11 bits, or 10 bits.
AD9627
Rev. B | Page 2 of 76
TABLE OF CONTENTS Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications ..................................................................................... 5
ADC DC Specifications—AD9627-80/AD9627-105 .................. 5
ADC DC Specifications—AD9627-125/AD9627-150 ................ 6
ADC AC Specifications—AD9627-80/AD9627-105 ................... 7
ADC AC Specifications—AD9627-125/AD9627-150 ................. 8
Digital Specifications ................................................................... 9
Switching Specifications—AD9627-80/AD9627-105 ................ 11
Switching Specifications—AD9627-125/AD9627-150 .............. 12
Timing Specifications ................................................................ 13
Absolute Maximum Ratings .......................................................... 15
Thermal Characteristics ............................................................ 15
ESD Caution ................................................................................ 15
Pin Configurations and Function Descriptions ......................... 16
Equivalent Circuits ......................................................................... 20
Typical Performance Characteristics ........................................... 21
Theory of Operation ...................................................................... 26
ADC Architecture ...................................................................... 26
Analog Input Considerations .................................................... 26
Voltage Reference ....................................................................... 28
Clock Input Considerations ...................................................... 29
Power Dissipation and Standby Mode ..................................... 31
Digital Outputs ........................................................................... 32
Timing .......................................................................................... 32
ADC Overrange and Gain Control .............................................. 33
Fast Detect Overview ................................................................. 33
ADC Fast Magnitude ................................................................. 33
ADC Overrange (OR) ................................................................ 34
Gain Switching ............................................................................ 34
Signal Monitor ................................................................................ 36
Peak Detector Mode................................................................... 36
RMS/MS Magnitude Mode ......................................................... 36
Threshold Crossing Mode ......................................................... 37
Additional Control Bits ............................................................. 37
DC Correction ............................................................................ 37
Signal Monitor SPORT Output ................................................ 38
Built-In Self-Test (BIST) and Output Test .................................. 39
Built-In Self-Test (BIST) ............................................................ 39
Output Test Modes ..................................................................... 39
Channel/Chip Synchronization .................................................... 40
Serial Port Interface (SPI) .............................................................. 41
Configuration Using the SPI ..................................................... 41
Hardware Interface ..................................................................... 41
Configuration Without the SPI ................................................ 42
SPI Accessible Features .............................................................. 42
Memory Map .................................................................................. 43
Reading the Memory Map Register Table ............................... 43
Memory Map Register Table ..................................................... 44
Memory Map Register Descriptions ........................................ 47
Applications Information .............................................................. 50
Design Guidelines ...................................................................... 50
Evaluation Board ............................................................................ 51
Power Supplies ............................................................................ 51
Input Signals................................................................................ 51
Output Signals ............................................................................ 51
Default Operation and Jumper Selection Settings ................. 52
Alternative Clock Configurations ............................................ 52
Alternative Analog Input Drive Configuration...................... 53
Schematics ................................................................................... 54
Evaluation Board Layouts ......................................................... 64
Bill of Materials ........................................................................... 72
Outline Dimensions ....................................................................... 74
Ordering Guide .......................................................................... 74
AD9627
Rev. B | Page 3 of 76
REVISION HISTORY 5/10—Rev. A to Rev. B Deleted CP-64-3 Package .................................................. Universal Added CP-64-6 Package .................................................... Universal Changed AD9627BCPZ-80 to AD9267-80 and AD9627BCPZ-105 to AD9627-105 Throughout .......................... 5 Changed AD9627BCPZ-125 to AD9267-125 and AD9627BCPZ-150 to AD9627-150 Throughout .......................... 6 Changes to Figure 6 ......................................................................... 16 Changes to Figure 7 ......................................................................... 18 Updated Outline Dimensions ........................................................ 74 Changes to Ordering Guide ........................................................... 74 6/09—Rev. 0 to Rev. A Changes to Table 6 .......................................................................... 11 Changes to Table 7 .......................................................................... 12 Changes to Figure 3 ......................................................................... 14 Changes to Figure 11, Figure 12, and Figure 14 .......................... 20 Changes to Table 15 ........................................................................ 32 Changes to Configuration Using the SPI Section ....................... 41 Change to Table 25 .......................................................................... 46 Change to Signal Monitor Period (Register 0x113 to Register 0x115) Section .............................................................. 49 Updated Outline Dimensions ........................................................ 74 10/07—Revision 0: Initial Version
AD9627
Rev. B | Page 4 of 76
GENERAL DESCRIPTION The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ 150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size, and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The AD9627 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.
In addition, the programmable threshold detector allows moni-toring of the incoming signal power, using the four fast detect bits of the ADC with very low latency. If the input signal level
exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition.
The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.
The AD9627 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
AD9627
Rev. B | Page 5 of 76
SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
Parameter Temperature AD9627-80 AD9627-105
Unit Min Typ Max Min Typ Max RESOLUTION Full 12 12 Bits ACCURACY
No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.2 ±0.6 ±0.3 ±0.7 % FSR Gain Error Full +0.1 −1.8 −3.7 −0.5 −2.2 −3.7 % FSR Differential Nonlinearity (DNL)1 Full ±0.4 ±0.4 LSB 25°C ±0.2 ±0.2 LSB Integral Nonlinearity (INL)1 Full ±0.9 ±0.9 LSB
25°C ±0.4 ±0.4 LSB MATCHING CHARACTERISTIC
Offset Error Full ±0.2 ±0.6 ±0.3 ±0.7 % FSR Gain Error Full ±0.2 ±0.75 ±0.2 ±0.75 % FSR
TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C
INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 mV
INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.3 0.3 LSB rms
ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 8 8 pF
VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES
Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Current IAVDD
1, 3 Full 233 278
310 365
mA IDVDD
1, 3 Full 26 34 mA IDRVDD
1 (3.3 V CMOS) Full 23 34 mA IDRVDD
1 (1.8 V CMOS) Full 11 15 mA IDRVDD
1 (1.8 V LVDS) Full 47 47 mA POWER CONSUMPTION
DC Input Full 452 490 600 650 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 495 657 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 550 740 mW Standby Power4 Full 52 68 mW Power-Down Power Full 2.5 6 2.5 6 mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
AD9627
Rev. B | Page 6 of 76
ADC DC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
Parameter Temperature AD9627-125 AD9627-150
Unit Min Typ Max Min Typ Max RESOLUTION Full 12 12 Bits ACCURACY
No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.2 ±0.6 % FSR Gain Error Full −0.7 −2.7 −3.9 −0.9 −3.2 −5.2 % FSR Differential Nonlinearity (DNL)1 Full ±0.4 ±0.9 LSB
25°C ±0.2 ±0.2 LSB Integral Nonlinearity (INL)1 Full ±0.9 ±1.3 LSB
25°C ±0.4 ±0.5 LSB MATCHING CHARACTERISTIC
Offset Error 25°C ±0.3 ±0.6 ±0.2 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.75 ±0.2 ±0.8 % FSR
TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C
INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 mV
INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.3 0.3 LSB rms
ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 8 8 pF
VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES
Supply Voltage AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Current IAVDD
1, 3 Full 385 455
419 495
mA IDVDD
1, 3 Full 42 50 mA IDRVDD
1 (3.3 V CMOS) Full 36 42 mA IDRVDD
1 (1.8 V CMOS) Full 18 22 mA IDRVDD
1 (1.8 V LVDS) Full 48 49 mA POWER CONSUMPTION
DC Input Full 750 800 820 890 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 814 895 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 900 995 mW Standby Power4 Full 77 77 mW Power-Down Power Full 2.5 6 2.5 6 mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
AD9627
Rev. B | Page 7 of 76
ADC AC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 3.
Parameter1 Temperature AD9627-80 AD9627-105
Unit Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz 25°C 69.7 69.6 dB fIN = 70 MHz 25°C 69.5 69.4 dB Full 68.1 68.6 dB fIN = 140 MHz 25°C 69.2 69.1 dB fIN = 220 MHz 25°C 68.5 68.4 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 69.6 69.5 dB fIN = 70 MHz 25°C 69.4 69.3 dB Full 67.4 68.0 dB fIN = 140 MHz 25°C 69.0 69.0 dB fIN = 220 MHz 25°C 68.3 68.1 dB
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 11.5 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.4 11.4 Bits fIN = 220 MHz 25°C 11.3 11.2 Bits
WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz 25°C −87 −87 dBc fIN = 70 MHz 25°C −85 −85 dBc Full −74 −74 dBc fIN = 140 MHz 25°C −84 −84 dBc fIN = 220 MHz 25°C −83 −83 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz 25°C 87 87 dBc fIN = 70 MHz 25°C 85 85 dBc Full 74 74 dBc fIN = 140 MHz 25°C 84 84 dBc fIN = 220 MHz 25°C 83 83 dBc
WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −88 dBc Full −82 −82 dBc fIN = 140 MHz 25°C −89 −87 dBc fIN = 220 MHz 25°C −89 −86 dBc
TWO-TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 85 85 dBc fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 dBc
CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
AD9627
Rev. B | Page 8 of 76
ADC AC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 4.
Parameter1 Temperature AD9627-125 AD9627-150
Unit Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz 25°C 69.5 69.4 dB fIN = 70 MHz 25°C 69.4 69.2 dB Full 68.1 67.1 dB fIN = 140 MHz 25°C 69.1 68.8 dB fIN = 220 MHz 25°C 68.8 68.2 dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 69.4 69.3 dB fIN = 70 MHz 25°C 69.3 69.1 dB Full 67.9 65.9 dB fIN = 140 MHz 25°C 69.0 68.7 dB fIN = 220 MHz 25°C 68.3 67.8 dB
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 11.4 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.3 11.3 Bits fIN = 220 MHz 25°C 11.3 11.2 Bits
WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz 25°C −86.5 −86.5 dBc fIN = 70 MHz 25°C −85 −84 dBc Full −74 −73 dBc fIN = 140 MHz 25°C −84 −83.5 dBc fIN = 220 MHz 25°C −83 −77 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz 25°C 86.5 86.5 dBc fIN = 70 MHz 25°C 85 84 dBc Full 74 73 dBc fIN = 140 MHz 25°C 84 83.5 dBc fIN = 220 MHz 25°C 83 77 dBc
WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −88 dBc Full −81 −80 dBc fIN = 140 MHz 25°C −89 −88 dBc fIN = 220 MHz 25°C −89 −88 dBc
TWO-TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 85 85 dBc fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 dBc
CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
AD9627
Rev. B | Page 9 of 76
DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 5. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ
SYNC INPUT Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full GND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ
LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF
LOGIC INPUT (SCLK/DFS)2 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA
AD9627
Rev. B | Page 10 of 76
Parameter Temperature Min Typ Max Unit Input Resistance Full 26 kΩ Input Capacitance Full 5 pF
DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage IOH = 50 μA Full 3.29 V IOH = 0.5 mA Full 3.25 V
Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V
CMOS Mode—DRVDD = 1.8 V High Level Output Voltage
IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V
Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V
LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V
1 Pull up. 2 Pull down.
AD9627
Rev. B | Page 11 of 76
SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 6.
Parameter Temperature AD9627-80 AD9627-105
Unit Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 625 MHz Conversion Rate
DCS Enabled1 Full 20 80 20 105 MSPS DCS Disabled1 Full 10 80 10 105 MSPS
CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 9.5 ns CLK Pulse Width High
Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 ns Divide by-1-Mode, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 ns Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns Divide-by-3 Through Divide-by-8
Modes, DCS Enabled Full 0.8 0.8 ns
DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2 Full 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (tDCO) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns Setup Time (tS) Full 6.25 5.25 ns Hold Time (tH) Full 5.75 4.25 ns
CMOS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 Full 2.4 5.2 6.9 2.4 5.2 6.9 ns DCO Propagation Delay (tDCO) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns Setup Time (tS) Full 6.65 5.15 ns Hold Time (tH) Full 5.85 4.35 ns
LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 Full 2.0 4.8 6.3 2.0 4.8 6.3 ns DCO Propagation Delay (tDCO) Full 5.2 7.3 9.0 5.2 7.3 9.0 ns
CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B Full 12/12.5 12/12.5 Cycles
Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 μs
OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors.
AD9627
Rev. B | Page 12 of 76
SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 7.
Parameter Temperature AD9627-125 AD9627-150
Unit Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 625 MHz Conversion Rate
DCS Enabled1 Full 20 125 20 150 MSPS DCS Disabled1 Full 10 125 10 150 MSPS
CLK Period—Divide-by-1 Mode (tCLK) Full 8 6.66 ns CLK Pulse Width High
Divide-by-1 Mode, DCS Enabled Full 2.4 4 5.6 2.0 3.33 4.66 ns Divide-by-1 Mode, DCS Disabled Full 3.6 4 4.4 3.0 3.33 3.66 ns Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns Divide-by-3-Through-8 Mode,
DCS Enabled Full 0.8 0.8 ns
DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2 Full 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (tDCO) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns Setup Time (tS) Full 4.5 3.83 ns Hold Time (tH) Full 3.5 2.83 ns
CMOS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 Full 2.4 5.2 6.9 2.4 5.2 6.9 ns DCO Propagation Delay (tDCO) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns Setup Time (tS) Full 4.4 3.73 ns Hold Time (tH) Full 3.6 2.93 ns
LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 Full 2.0 4.8 6.3 2.0 4.8 6.3 ns DCO Propagation Delay (tDCO) Full 5.2 7.3 9.0 5.2 7.3 9.0 ns
CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B Full 12/12.5 12/12.5 Cycles
Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 μs
OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors.
AD9627
Rev. B | Page 13 of 76
TIMING SPECIFICATIONS
Table 8. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS
tSSYNC SYNC to rising edge of CLK setup time 0.24 ns tHSYNC SYNC to rising edge of CLK hold time 0.40 ns
SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge 10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge
10 ns
SPORT TIMING REQUIREMENTS tCSSCLK Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns tSSCLKSDO Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 0.4 ns tSSCLKSDFS Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 0.4 ns
Timing Diagrams
CLK+
DCOA/DCOB
CH A/CH B DATA
N
N + 1N + 2
N + 3
N + 4
N + 5N + 6 N + 7
N + 8
N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4N – 13
CLK–
tCLK
tPD
tS tH tDCO tCLK
tA
CH A/CH B FASTDETECT
N – 1 N + 2 N + 3 N + 4 N + 5 N + 6N – 3 N – 2
N – 10
N + 1N
0657
1-0
02
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
AD9627
Rev. B | Page 14 of 76
CLK+
DCO+
DCO–
CH A/CH B DATA
N
N + 1N + 2
N + 3
N + 4
N + 5N + 6 N + 7
N + 8
N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4N – 13
CLK–
tCLK
tPD
tDCOtCLK
tA
CH A/CH B FASTDETECT
A B A B A B A B A B A B A B A B A AB
N – 10
N – 6 N – 5 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7
A B A B A B A B A B A B A B A B A AB
N – 4
0657
1-00
3
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
SYNC
CLK+
tHSYNCtSSYNC
065
71-0
04
Figure 4. SYNC Input Timing Requirements
CLK+
SMI SCLK
SMI SDFS
DATA DATASMI SDO
CLK–
tCSSCLK
tSSCLKSDFS tSSCLKSDO
0657
1-00
5
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
AD9627
Rev. B | Page 15 of 76
ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Rating ELECTRICAL
AVDD, DVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to +3.9 V SYNC to AGND −0.3 V to +3.9 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to DRGND −0.3 V to +3.9 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V SMI SDO/OEB −0.3 V to DRVDD + 0.3 V SMI SCLK/PDWN −0.3 V to DRVDD + 0.3 V SMI SDFS −0.3 V to DRVDD + 0.3 V D0A/D0B through D11A/D11B to
DRGND −0.3 V to DRVDD + 0.3 V
FD0A/FD0B through FD3A/FD3B to DRGND
−0.3 V to DRVDD + 0.3 V
DCOA/DCOB to DRGND −0.3 V to DRVDD + 0.3 V ENVIRONMENTAL
Operating Temperature Range (Ambient)
−40°C to +85°C
Maximum Junction Temperature Under Bias
150°C
Storage Temperature Range (Ambient)
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package.
Table 10. Thermal Resistance
Package Type
Airflow Velocity (m/s) θJA
1, 2 θJC1, 3 θJB
1, 4 Unit 64-Lead LFCSP 9 mm × 9 mm (CP-64-6)
0 18.8 0.6 6.0 °C/W 1.0 16.5 °C/W 2.0 15.8 °C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA.
ESD CAUTION
AD9627
Rev. B | Page 16 of 76
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
0657
1-0
06
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D3A
D4A
D5A
DR
GN
DD
RV
DD
D6A
D7A
DV
DD
D8A
D9A
D10
AD
11A
(M
SB
)F
D0A
FD
1AF
D2A
FD
3A
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DR
GN
DD
3BD
2BD
1BD
0B (
LS
B)
DN
CD
NC
DV
DD
FD
3BF
D2B
FD
1BF
D0B
SY
NC
CS
BC
LK
–C
LK
+
123456789
10111213141516
DRVDDD4BD5BD6BD7BD8BD9B
D10BD11B (MSB)
DCOBDCOA
DNCDNC
D0A (LSB)D1AD2A
SCLK/DFSSDIO/DCSAVDDAVDDVIN+BVIN–BRBIASCMLSENSEVREFVIN–AVIN+AAVDDSMI SDFSSMI SCLK/PDWNSMI SDO/OEB
48474645444342414039383736353433
PIN 1INDICATOR
AD9627PARALLEL CMOS
TOP VIEW(Not to Scale)
EXPOSED PADDLE, PIN 0(BOTTOM OF PACKAGE)
NOTES1. DNC = DO NOT CONNECT.2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 11. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 12, 13, 58, 59 DNC Do Not Connect.
ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement.
ADC Fast Detect Outputs 29 FD0A Output Channel A Fast Detect Indicator. See Table 17 for details. 30 FD1A Output Channel A Fast Detect Indicator. See Table 17 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Table 17 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Table 17 for details. 53 FD0B Output Channel B Fast Detect Indicator. See Table 17 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Table 17 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Table 17 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Table 17 for details.
AD9627
Rev. B | Page 17 of 76
Pin No. Mnemonic Type Description Digital Input 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 14 D0A (LSB) Output Channel A CMOS Output Data. 15 D1A Output Channel A CMOS Output Data. 16 D2A Output Channel A CMOS Output Data. 17 D3A Output Channel A CMOS Output Data. 18 D4A Output Channel A CMOS Output Data. 19 D5A Output Channel A CMOS Output Data. 22 D6A Output Channel A CMOS Output Data. 23 D7A Output Channel A CMOS Output Data. 25 D8A Output Channel A CMOS Output Data. 26 D9A Output Channel A CMOS Output Data. 27 D10A Output Channel A CMOS Output Data. 28 D11A (MSB) Output Channel A CMOS Output Data. 60 D0B (LSB) Output Channel B CMOS Output Data. 61 D1B Output Channel B CMOS Output Data. 62 D2B Output Channel B CMOS Output Data. 63 D3B Output Channel B CMOS Output Data. 2 D4B Output Channel B CMOS Output Data. 3 D5B Output Channel B CMOS Output Data. 4 D6B Output Channel B CMOS Output Data. 5 D7B Output Channel B CMOS Output Data. 6 D8B Output Channel B CMOS Output Data. 7 D9B Output Channel B CMOS Output Data. 8 D10B Output Channel B CMOS Output Data. 9 D11B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output.
SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
AD9627
Rev. B | Page 18 of 76
065
71-0
07
PIN 1INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D5+
D6–
D6+
DR
GN
DD
RV
DD
D7–
D7+
DV
DD
D8–
D8+
D9–
D9+
D10
–D
10+
D11
– (M
SB
)D
11+
(M
SB
)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DR
GN
DD
NC
DN
CF
D3+
FD
3–F
D2+
FD
2–D
VD
DF
D1+
FD
1–F
D0+
FD
0–S
YN
CC
SB
CL
K–
CL
K+
123456789
10111213141516
DRVDDDNCDNC
D0– (LSB)D0+ (LSB)
D1–D1+D2–D2+
DCO–DCO+
D3–D3+D4–D4+D5–
SCLK/DFSSDIO/DCSAVDDAVDDVIN+BVIN–BRBIASCMLSENSEVREFVIN–AVIN+AAVDDSMI SDFSSMI SCLK/PDWNSMI SDO/OEB
48474645444342414039383736353433
AD9627PARALLEL LVDS
TOP VIEW(Not to Scale)
EXPOSED PADDLE, PIN 0(BOTTOM OF PACKAGE)
NOTES1. DNC = DO NOT CONNECT.2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies
20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 2, 3, 62, 63
DNC Do Not Connect.
ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement.
ADC Fast Detect Outputs 54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details. 53 FD0− Output Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details. 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details. 55 FD1− Output Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details. 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details. 58 FD2− Output Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details. 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details. 60 FD3− Output Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details. Digital Input
52 SYNC Input Digital Synchronization Pin. Slave mode only.
AD9627
Rev. B | Page 19 of 76
Pin No. Mnemonic Type Description Digital Outputs 5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 7 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 9 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 13 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 12 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 15 D4+ Output Channel A/Channel B LVDS Output Data 4 —True. 14 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 17 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 16 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 19 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 18 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 23 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 22 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 26 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 25 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 28 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 27 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 30 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 32 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True. 31 D11− (MSB) Output Channel A/Channel B LVDS Output Data 11—Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 10 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
AD9627
Rev. B | Page 20 of 76
EQUIVALENT CIRCUITS
VIN
0657
1-00
8
Figure 8. Equivalent Analog Input Circuit
1.2V
10kΩ 10kΩCLK+ CLK–
AVDD
065
71-0
09
Figure 9. Equivalent Clock Input Circuit
DRVDD
DRGND
065
71-0
10
Figure 10. Digital Output
SDIO/DCS1kΩ
26kΩ
DRVDD
DRVDD
0657
1-0
11
Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit
SCLK/DFS1kΩ
26kΩ
065
71-0
12
Figure 12. Equivalent SCLK/DFS Input Circuit
SENSE1kΩ
065
71-0
13
Figure 13. Equivalent SENSE Circuit
CSB1kΩ
26kΩ
AVDD
065
71-0
14Figure 14. Equivalent CSB Input Circuit
VREF
AVDD
6kΩ
065
71-0
15
Figure 15. Equivalent VREF Circuit
AD9627
Rev. B | Page 21 of 76
TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 64k sample, TA = 25°C, unless otherwise noted.
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS2.3MHz @ –1dBFSSNR = 69.4dBc (70.4dBFS)ENOB = 11.4 BITSSFDR = 86.5dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
16
Figure 16. AD9627-150 Single-Tone FFT with fIN = 2.3 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS30.3MHz @ –1dBFSSNR = 69.3dBc (70.3dBFS)ENOB = 11.4 BITSSFDR = 84.0dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
17
Figure 17. AD9627-150 Single-Tone FFT with fIN = 30.3 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS70MHz @ –1dBFSSNR = 69.2dBc (70.2dBFS)ENOB = 11.4 BITSSFDR = 84.0dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
18
Figure 18. AD9627-150 Single-Tone FFT with fIN = 70 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS140MHz @ –1dBFSSNR = 68.8dBc (69.8dBFS)ENOB = 11.3 BITSSFDR = 83.5dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
19
Figure 19. AD9627-150 Single-Tone FFT with fIN = 140 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS220MHz @ –1dBFSSNR = 68.2dBc (69.2dBFS)ENOB = 11.2 BITSSFDR = 77.0dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
20
Figure 20. AD9627-150 Single-Tone FFT with fIN = 220 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS337MHz @ –1dBFSSNR = 67.6dBc (68.6dBFS)ENOB = 11.1 BITSSFDR = 74.0dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
21
Figure 21. AD9627-150 Single-Tone FFT with fIN = 337 MHz
AD9627
Rev. B | Page 22 of 76
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS440MHz @ –1dBFSSNR = 65.7dBc (66.7dBFS)ENOB = 10.4 BITSSFDR = 70.0dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
22
Figure 22. AD9627-150 Single-Tone FFT with fIN = 440 MHz
0
–20
–40
–60
–80
–100
–1200 605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
125MSPS2.3MHz @ –1dBFSSNR = 69.5dBc (70.5dBFS)ENOB = 11.4 BITSSFDR = 86.5dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
23
Figure 23. AD9627-125 Single-Tone FFT with fIN = 2.3 MHz
0
–20
–40
–60
–80
–100
–1200 605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
125MSPS30.3MHz @ –1dBFSSNR = 69.4dBc (70.4dBFS)ENOB = 11.4 BITSSFDR = 85dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
24
Figure 24. AD9627-125 Single-Tone FFT with fIN = 30.3 MHz
0
–20
–40
–60
–80
–100
–1200 605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
125MSPS70MHz @ –1dBFSSNR = 69.4dBc (70.4dBFS)ENOB = 11.4 BITSSFDR = 85dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
25
Figure 25. AD9627-125 Single-Tone FFT with fIN = 70 MHz
0
–20
–40
–60
–80
–100
–1200 605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
125MSPS140MHz @ –1dBFSSNR = 69.1dBc (70.1dBFS)ENOB = 11.3 BITSSFDR = 84dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
26
Figure 26. AD9627-125 Single-Tone FFT with fIN = 140 MHz
0
–20
–40
–60
–80
–100
–1200 605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
125MSPS337MHz @ –1dBFSSNR = 67.6dBc (68.6dBFS)ENOB = 11.1 BITSSFDR = 74dBc
SECONDHARMONIC
THIRDHARMONIC
065
71-0
27
Figure 27. AD9627-125 Single-Tone FFT with fIN = 337 MHz
AD9627
Rev. B | Page 23 of 76
120
100
80
60
40
20
0–90 0–10–20–30–40–50–60–70–80
SN
R/S
FD
R (
dB
c A
ND
dB
FS
)
INPUT AMPLITUDE (dBFS)
SFDR (dBFS)
SNR (dBc)
SNR (dBFS)
SFDR (dBc)85dB REFERENCE LINE
065
71-0
28
Figure 28. AD9627-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.4 MHz
100
80
60
40
20
0–90 0–10–20–30–40–50–60–70–80
SN
R/S
FD
R (
dB
c A
ND
dB
FS
)
INPUT AMPLITUDE (dBFS)
SFDR (dBFS)
SNR (dBc)
SNR (dBFS)
SFDR (dBc)
85dB REFERENCE LINE
065
71-0
29
Figure 29. AD9627-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz
95
90
85
80
75
70
65
60
550 45040035030025020015010050
SN
R/S
FD
R (
dB
c)
INPUT FREQUENCY (MHz)
SFDR = +25°C
SFDR = +85°C
SFDR = –40°C
SNR = +25°CSNR = +85°CSNR = –40°C
065
71-0
30
Figure 30. AD9627-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
95
90
85
80
75
70
65
60
550 45040035030025020015010050
SN
R/S
FD
R (
dB
c)
INPUT FREQUENCY (MHz)
SFDR = +25°C
SFDR = +85°C
SFDR = –40°C
SNR = +25°CSNR = +85°CSNR = –40°C
065
71-0
31
Figure 31. AD9627-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1 V p-p Full Scale
–2.5
–5.0
–4.5
–4.0
–3.5
–3.0
0.5
0
0.1
0.2
0.3
0.4
–40 806040
GAIN
OFFSET
200–20
GA
IN E
RR
OR
(%
FS
R)
OF
FS
ET
ER
RO
R (
%F
SR
)
TEMPERATURE (°C)
065
71-0
32
Figure 32. AD9627-150 Gain and Offset vs. Temperature
0
–20
–40
–60
–80
–100
–120–90 –78 –66 –54 –42 –30 –18 –6
SF
DR
/IM
D3
(dB
c A
ND
dB
FS
)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
IMD3 (dBc)
SFDR (dBFS)
IMD3 (dBFS)
065
71-0
33
Figure 33. AD9627-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
AD9627
Rev. B | Page 24 of 76
0
–20
–40
–60
–80
–100
–120–90 –78 –66 –54 –42 –30 –18 –6
SF
DR
/IM
D3
(dB
c A
ND
dB
FS
)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
IMD3 (dBc)
SFDR (dBFS)
IMD3 (dBFS)
065
71-0
34
Figure 34. AD9627-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
–20
–40
–60
–80
–100
–1200 15.36 30.72 46.08 61.44
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
065
71-0
35
Figure 35. AD9627-125, Two 64k WCDMA Carriers with fIN = 170 MHz, fS = 122.88 MSPS
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS29.1MHz @ –7dBFS32.1MHz @ –7dBFSSFDR = 86.1dBc (93.1dBFS)
065
71-0
36
Figure 36. AD9627-150 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
150MSPS169.1MHz @ –7dBFS172.1MHz @ –7dBFSSFDR = 83.8dBc (90.8dBFS)
065
71-0
37
Figure 37. AD9627-150 Two-Tone FFT with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
0
–20
–40
–60
–80
–100
–1200 70605040302010
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
065
71-0
38
NPR = 61.5dBcNOTCH @ 18.5MHzNOTCH WIDTH = 3MHz
Figure 38. AD9627-150 Noise Power Ratio (NPR)
100
90
80
70
60
500 150125100755025
SN
R/S
FD
R (
dB
c)
SAMPLE RATE (MSPS)
SFDR - SIDE B
SFDR - SIDE A
SNR - SIDE B
SNR - SIDE A
065
71-0
39
Figure 39. AD9627-150 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 2.3 MHz
AD9627
Rev. B | Page 25 of 76
12
10
8
6
4
2
0N + 3N + 2N + 1NN – 1N – 2N – 3
NU
MB
ER
OF
HIT
S (
1M)
OUTPUT CODE
0.3 LSB rms
065
71-0
40
Figure 40. AD9627 Grounded Input Histogram
0.4
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0 4096358430722560204815361024512
INL
ER
RO
R (
LS
B)
OUTPUT CODE
065
71-0
41
Figure 41. AD9627 INL with fIN = 10.3 MHz
0.25
–0.25
–0.05
–0.15
0.05
0.15
0 4096358430722560204815361024512
DN
L E
RR
OR
(L
SB
)
OUTPUT CODE
065
71-0
42
Figure 42. AD9627 DNL with fIN = 10.3 MHz
100
60
65
70
75
80
85
90
95
20 806040
SN
R/S
FD
R (
dB
c)
DUTY CYCLE (%)
065
71-0
43
SFDR DCS ON
SNR DCS ON
SFDR DCS OFF
SNR DCS OFF
Figure 43. AD9627-150 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz
95
60
65
70
75
80
85
90
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
SN
R/S
FD
R (
dB
c)
INPUT COMMON-MODE VOLTAGE (V)
065
71-0
44
SNR
SFDR
Figure 44. AD9627-150 SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30 MHz
AD9627
Rev. B | Page 26 of 76
THEORY OF OPERATION The AD9627 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion.
In nondiversity applications, the AD9627 can be used as a base-band or direct downconversion receiver, where one ADC is used for I input data, and the other is used for Q input data.
Synchronizaton capability is provided to allow synchronized timing between multiple channels or multiple devices.
Programming and control of the AD9627 are accomplished using a 3-bit SPI-compatible serial interface.
ADC ARCHITECTURE The AD9627 architecture consists of a dual front-end sample-and-hold amplifier (SHA), followed by a pipelined, switched capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digital-to-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
The input stage of each channel contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS The analog input to the AD9627 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal.
The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 45). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to Application Note AN-742, Frequency Domain Response of Switched-Capacitor ADCs; Application Note AN-827, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters,” for more information on this subject (see www.analog.com).
VIN+
VIN–
CPIN, PAR
CPIN, PAR
CS
CS
CH
CH
H
S
S
S
S
065
71-0
45
Figure 45. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9627 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.55 × AVDD is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 44). An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 × AVDD). The CML pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9627 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC.
AD9627
Rev. B | Page 27 of 76
The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9627 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
AVDD1V p-p 49.9Ω
523Ω0.1µF
R
R
C
499Ω
499Ω
499Ω
AD8138 AD9627
VIN+
VIN– CML
06
57
1-0
46
Figure 46. Differential Input Configuration Using the AD8138
For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 47. To bias the analog input, the CML voltage can be connected to the center tap of the secondary winding of the transformer.
2V p-p49.9Ω
0.1µF
R
R
C AD9627
VIN+
VIN– CML
065
71-0
47
Figure 47. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9627. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49).
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information.
In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 13 displays recommended values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide.
Table 13. Example RC Network
Frequency Range (MHz) R Series (Ω Each) C Differential (pF)
0 to 70 33 15 70 to 200 33 5 200 to 300 15 5 >300 15 Open
Single-Ended Input Configuration
A single-ended input can provide adequate performance in cost sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 48 shows a typical single-ended input configuration.
1V p-p
R
R
C
49.9Ω 0.1µF
10µF
10µF 0.1µF
AVDD
1kΩ
1kΩ
1kΩ
1kΩ
AD9627
AVDD
VIN+
VIN–
065
71-
048
Figure 48. Single-Ended Input Configuration
AD9627
R0.1µF0.1µF
2V p-p VIN+
VIN– CML
C
R0.1µF
S0.1µF25Ω
25Ω
SPA P
0657
1-04
9
Figure 49. Differential Double Balun Input Configuration
AD9627AD8352
0Ω
R
0Ω
CDRD RG
0.1µF
0.1µF
0.1µF
VIN+
VIN– CML
C
0.1µF
16
1
2
3
4
5
11
R0.1µF
0.1µF
10
14
0.1µF8, 13
VCC
200Ω
200Ω
ANALOG INPUT
ANALOG INPUT
0657
1-05
0
Figure 50. Differential Input Configuration Using the AD8352
AD9627
Rev. B | Page 28 of 76
VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9627. The input range can be adjusted by varying the reference voltage applied to the AD9627, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9627 detects the potential at the SENSE pin and configures the reference into four possible modes, which are summarized in Table 14. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1.0 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output.
VREF
SENSE
0.5V
AD9627
SELECTLOGIC
0.1µF1.0µF
VIN–A/VIN–B
VIN+A/VIN+B
ADCCORE
065
71-0
51
Figure 51. Internal Reference Configuration
If a resistor divider is connected external to the chip, as shown in Figure 52, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as follows:
R1R2VREF 15.0
The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
0.5V
AD9627
SELECTLOGIC
VIN–A/VIN–B
VIN+A/VIN+B
ADCCORE
VREF
SENSE
0.1µF1.0µF R2
R1
065
71-0
52
Figure 52. Programmable Reference Configuration
If the internal reference of the AD9627 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 shows how the internal reference voltage is affected by loading.
0
–1.250 2.0
LOAD CURRENT (mA)
RE
FE
RE
NC
E V
OL
TA
GE
ER
RO
R (
%)
–0.25
–0.50
–0.75
–1.00
0.5 1.0 1.5
VREF = 0.5V
VREF = 1.0V
065
71-0
53
Figure 53. VREF Accuracy vs. Load
Table 14. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × external reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF
R1
R210.5 (see Figure 52) 2 × VREF
Internal Fixed Reference AGND to 0.2 V 1.0 2.0
AD9627
Rev. B | Page 29 of 76
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac-teristics. Figure 54 shows the typical drift characteristics of the internal reference in 1.0 V mode.
2.5
–2.5–40
TEMPERATURE (°C)
RE
FE
RE
NC
E V
OL
TA
GE
ER
RO
R (
mV
)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20 0 20 40 60 80
065
71-0
54
Figure 54. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 15). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V.
CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9627 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 55) and require no external bias.
1.2V
AVDD
2pF 2pF
CLK–CLK+
065
71-0
55
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9627 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section.
Figure 56 and Figure 57 show two preferred methods for clocking the AD9627 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9627 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9627 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKYDIODES:
HSMS2822
CLOCKINPUT
50Ω 100Ω
CLK–
CLK+ADC
AD9627
Mini-Circuits®
ADT1–1WT, 1:1Z
XFMR
065
71-0
56
Figure 56. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1µF
0.1µF1nFCLOCK
INPUT
1nF
50Ω
CLK–
CLK+ADC
AD9627
SCHOTTKYDIODES:
HSMS2822
065
71-0
57
Figure 57. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 58. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
100Ω
0.1µF
0.1µF0.1µF
0.1µF
240Ω240Ω
PECL DRIVER
50kΩ 50kΩ
CLK–
CLK+
ADCAD9627
CLOCKINPUT
CLOCKINPUT
AD951x
06
57
1-0
58
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 59. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
100Ω
0.1µF
0.1µF0.1µF
0.1µF
50kΩ 50kΩ
CLK–
CLK+
ADCAD9627
CLOCKINPUT
CLOCKINPUT
AD951xLVDS DRIVER
06
57
1-0
59
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
AD9627
Rev. B | Page 30 of 76
In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applica-tions, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 60).
CLK+ can be driven directly from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.6 V, making the selection of the drive logic voltage very flexible.
OPTIONAL100Ω 0.1µF
0.1µF
0.1µF
39kΩ
50Ω1
150Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADCAD9627
VCC
1kΩ
1kΩ
CLOCKINPUT
AD951xCMOS DRIVER
06
571
-060
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
150Ω RESISTOR IS OPTIONAL.
OPTIONAL100Ω
0.1µF
0.1µF
0.1µF
VCC
50Ω1
CLK–
CLK+
ADCAD9627
1kΩ
1kΩ
CLOCKINPUT
AD951xCMOS DRIVER
06
57
1-0
61
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Input Clock Divider
The AD9627 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. If a divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled.
The AD9627 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchro-nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics.
The AD9627 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9627. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 43.
Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it thatmust be considered where the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 )10/( LFSNR ]
In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 62.
75
70
65
60
55
50
451 10 100 1000
SN
R (
dB
c)
INPUT FREQUENCY (MHz)
3.00ps
0.05ps
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps2.50ps
065
71-0
62
MEASURED
Figure 62. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9627. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.
Refer to Application Note AN-501 and Application Note AN-756 (see www.analog.com) for more information about jitter perform-ance as it relates to ADCs.
AD9627
Rev. B | Page 31 of 76
POWER DISSIPATION AND STANDBY MODE As shown in Figure 63 through Figure 66, the power dissipated by the AD9627 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (26, in the case of the AD9627, with the fast detect output pins disabled).
This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal.
Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 63 was taken using the same operating conditions as those used for the Typical Performance Characteristics, with a 5 pF load on each output driver.
TO
TA
L P
OW
ER
(W
)
SU
PP
LY
CU
RR
EN
T (
A)
SAMPLE RATE (MSPS)
0
0.1
0.2
0.3
0.4
0.5
IAVDD
IDVDD0.25
0
0.50
0.75
1.00
1.25
0 25 50 75 100 125 150
TOTAL POWER
065
71-0
63
IDRVDD
Figure 63. AD9627-150 Power and Current vs. Sample Rate
TO
TA
L P
OW
ER
(W
)
SU
PP
LY
CU
RR
EN
T (
A)
SAMPLE RATE (MSPS)
0
0.1
0.2
0.3
0.4
0.5
IAVDD
IDVDD
IDRVDD
0.25
0
0.50
0.75
1.00
1.25
0 25 50 75 100 125
TOTAL POWER
065
71-0
64
Figure 64. AD9627-125 Power and Current vs. Sample Rate
TO
TA
L P
OW
ER
(W
)
SU
PP
LY
CU
RR
EN
T (
A)
SAMPLE RATE (MSPS)
0
0.1
0.2
0.3
0.4
IAVDD
IDVDD
IDRVDD
0.25
0
0.50
0.75
1.00
0 25 50 75 100
TOTAL POWER
065
71-0
65
Figure 65. AD9627-105 Power and Current vs. Sample Rate
TO
TA
L P
OW
ER
(W
)
SU
PP
LY
CU
RR
EN
T (
A)
SAMPLE RATE (MSPS)
0
0.1
0.2
0.3
IAVDD
IDVDD
IDRVDD
0.25
0
0.50
0.75
0 20 40 60 80
TOTAL POWER
065
71-0
66
Figure 66. AD9627-80 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9627 is placed in power-down mode. In this state, the ADC typically dissipates 2.5 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9627 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Description section for more details.
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DIGITAL OUTPUTS The AD9627 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9627 can also be configured for LVDS outputs using a DRVDD supply voltage of 1.8 V.
In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.
The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 15).
As detailed in Application Note AN-877, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control.
Table 15. SCLK/DFS Mode Selection (External Pin Mode) Voltage at Pin SCLK/DFS SDIO/DCS AGND (default) Offset binary DCS disabled AVDD Twos complement DCS enabled
Digital Output Enable Function (OEB)
The AD9627 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SMI SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB pin is low, the output data drivers are enabled. If the SMI SDO/OEB pin is high, the output data drivers are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data and fast detect outputs of each channel can be independently three-stated by using the output enable bar bit in Register 0x14.
TIMING The AD9627 provides latched data with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9627. These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9627 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9627 provides two data clock output (DCO) signals intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description.
Table 16. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 1000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 1000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 0111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 0111 1111 1111 1
AD9627
Rev. B | Page 33 of 76
ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact infor-mation on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, latency of this function is of major concern. Highly pipelined converters can have significant latency. A good compromise is to use the output bits from the first stage of the ADC for this function. Latency for these output bits is very low, and overall resolution is not highly significant. Peak input signals are typically between full scale and 6 dB to 10 dB below full scale. A 3-bit or 4-bit output provides adequate range and resolution for this function.
Using the SPI port, the user can provide a threshold above which an overrange output is active. As long as the signal is below that threshold, the output should remain low. The fast detect outputs can also be programmed via the SPI port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature. In this mode, all 12 bits of the converter are examined in the traditional manner, and the output is high for the condition normally defined as overflow. In either mode, the magnitude of the data is considered in the calculation of the condition (but the sign of the data is not considered). The threshold detection responds identically to positive and negative signals outside the desired range (magnitude).
FAST DETECT OVERVIEW The AD9627 contains circuitry to facilitate fast overrange detec-tion, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level. The function of these pins is programmable via the fast detect mode select bits and the fast detect enable bits in Register 0x104, allowing range information to be output from several points in the internal datapath. These output pins can also be set up to indicate the presence of overrange or underrange conditions, according to programmable threshold levels. Table 17 shows the six configurations available for the fast detect pins.
Table 17. Fast Detect Mode Select Bits Settings
Fast Detect Mode Select Bits (Register 0x104[3:1])
Information Presented on Fast Detect (FD) Pins of Each ADC1, 2
FD[3] FD[2] FD[1] FD[0] 000 ADC fast magnitude
(see Table 18) 001 ADC fast magnitude
(see Table 19) OR
010 ADC fast magnitude (see Table 20)
OR F_LT
011 ADC fast magnitude(see Table 20)
C_UT F_LT
100 OR C_UT F_UT F_LT 101 OR F_UT IG DG 1 The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode
configuration and FD0+/FD0− to FD9+/FD9− for the LVDS mode configuration.
2 See the ADC Overrange (OR) and Gain Switching sections for more information about OR, C_UT, F_UT, F_LT, IG, and DG.
ADC FAST MAGNITUDE When the fast detect output pins are configured to output the ADC fast magnitude (that is, when the fast detect mode select bits are set to 0b000), the information presented is the ADC level from an early converter stage with a latency of only two clock cycles (when in CMOS output mode). Using the fast detect output pins in this configuration provides the earliest possible level indication information. Because this information is provided early in the datapath, there is significant uncertainty in the level indicated. The nominal levels, along with the uncertainty indicated by the ADC fast magnitude, are shown in Table 18.
Table 18. ADC Fast Magnitude Nominal Levels with Fast Detect Mode Select Bits = 000 ADC Fast Magnitude on FD[3:0] Pins
Nominal Input Magnitude Below FS (dB)
Nominal Input Magnitude Uncertainty (dB)
0000 <−24 Minimum to −18.07 0001 −24 to −14.5 −30.14 to −12.04 0010 −14.5 to −10 −18.07 to −8.52 0011 −10 to −7 −12.04 to −6.02 0100 −7 to −5 −8.52 to −4.08 0101 −5 to −3.25 −6.02 to −2.5 0110 −3.25 to −1.8 −4.08 to −1.16 0111 −1.8 to −0.56 −2.5 to FS 1000 −0.56 to 0 −1.16 to 0
AD9627
Rev. B | Page 34 of 76
When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table 19 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when ADC fast magnitude is presented on the FD[3:1] pins).
Table 19. ADC Fast Magnitude Nominal Levels with Fast Detect Mode Select Bits = 001
ADC Fast Magnitude on FD[3:1] Pins
Nominal Input Magnitude Below FS (dB)
Nominal Input Magnitude Uncertainty (dB)
000 <−24 Minimum to −18.07 001 −24 to −14.5 −30.14 to −12.04 010 −14.5 to −10 −18.07 to −8.52 011 −10 to −7 −12.04 to −6.02 100 −7 to −5 −8.52 to −4.08 101 −5 to −3.25 −6.02 to −2.5 110 −3.25 to −1.8 −4.08 to −1.16 111 −1.8 to 0 −2.5 to 0
When the fast detect mode select bits are set to 0b010 or 0b011 (that is, when ADC fast magnitude is presented on the FD[3:2] pins), the LSB is not provided. The input ranges for this mode are shown in Table 20.
Table 20. ADC Fast Magnitude Nominal Levels with Fast Detect Mode Select Bits = 010 or 011 ADC Fast Magnitude on FD[2:1] Pins
Nominal Input Magnitude Below FS (dB)
Nominal Input Magnitude Uncertainty (dB)
00 <−14.5 Minimum to −12.04 01 −14.5 to −7 −18.07 to −6.02 10 −7 to −3.25 −8.52 to −2.5 11 −3.25 to 0 −4.08 to 0
ADC OVERRANGE (OR) The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange condition is determined at the output of the ADC pipeline and, therefore, is subject to a latency of 12 ADC clock cycles. An overrange at the input is indicated by this bit 12 clock cycles after it occurs.
GAIN SWITCHING The AD9627 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. Fast detect mode select bit = 010 through fast detect mode select bit = 101 support various combinations of the gain switching options.
One such use is to detect when an ADC is about to reach full scale with a particular input condition. The result is to provide an indicator that can be used to quickly insert an attenuator that prevents ADC overdrive.
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast magnitude input level is greater than the level programmed in the coarse upper threshold register (Address 0x105[2:0]). This value is compared with the ADC Fast Magnitude Bits[2:0]. The coarse upper threshold output is output two clock cycles after the level is exceeded at the input and, therefore, it provides a fast indication of the input signal level. The coarse upper threshold levels are shown in Table 21. This indicator remains asserted for a minimum of two ADC clock cycles or until the signal drops below the threshold level.
Table 21. Coarse Upper Threshold Levels
Coarse Upper Threshold Register 0x105[2:0]
C_UT Is Active When Signal Magnitude Below FS Is Greater Than (dB)
000 <−24 001 −24 010 −14.5 011 −10 100 −7 101 −5 110 −3.25 111 −1.8
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input magnitude exceeds the value programmed in the fine upper threshold register located in Register 0x106 and Register 0x107. The 13-bit threshold register is compared with the signal magni-tude at the output of the ADC. This comparison is subject to the ADC clock latency but is accurate in terms of the converter resolution. The fine upper threshold magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input magnitude is less than the value programmed in the fine lower threshold register located at Register 0x108 and Register 0x109. The fine lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to ADC clock latency but is accurate in terms of the converter resolution. The fine lower threshold magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The operation of the fine upper threshold indicators and fine lower threshold indicators is shown in Figure 67.
AD9627
Rev. B | Page 35 of 76
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (Address 0x105). The increment gain indicator, similarly, corresponds to the fine lower threshold bits, except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. The dwell time is set by the 16-bit dwell time value located at Address 0x10A and Address 0x10B and is set in units of ADC input clock cycles ranging from 1 to 65,535. The fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison is subject to the ADC clock latency but allows a finer, more accurate comparison. The fine upper threshold magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The decrement gain output works from the ADC fast detect output pins, providing a fast indication of potential overrange conditions. The increment gain uses the comparison at the output of the ADC, requiring the input magnitude to remain below an accurate, programmable level for a predefined period before signaling external circuitry to increase the gain.
The operation of the increment gain output and the decrement gain output is shown in Figure 67.
UPPER THRESHOLD (COARSE OR FINE)
FINE LOWER THRESHOLD
IG
DG
F_LT
C_UT OR F_UT*
DWELL TIME
TIMER RESET BYRISE ABOVE F_LT
TIMER COMPLETES BEFORESIGNAL RISES ABOVE F_LT
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
DWELL TIME
065
71-0
67
Figure 67. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT
AD9627
Rev. B | Page 36 of 76
SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular threshold. Together, these functions can be used to gain insight into the signal characteristics and to estimate the peak/average ratio or even the shape of the complementary cumulative distribution function (CCDF) curve of the input signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The signal monitor result values can be obtained from the part by reading back internal registers at Address 0x116 to Address 0x11B, using the SPI port or the signal monitor SPORT output. The output contents of the SPI-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register. Both ADC channels must be configured for the same signal monitor mode. Separate SPI-accessible, 20-bit signal monitor result (SMR) registers are provided for each ADC channel. Any combination of the signal monitor functions can also be output to the user via the serial SPORT interface. These outputs are enabled using the peak detector output enable, the rms magnitude output enable, and the threshold crossing output enable bits in the signal monitor SPORT control register. For each signal monitor measurement, a programmable signal monitor period register (SMPR) controls the duration of the measurement. This time period is programmed as the number of input clock cycles in a 24-bit signal monitor period register located at Address 0x113, Address 0x114, and Address 0x115. This register can be programmed with a period from 128 samples to 16.78 (224) million samples. Because the dc offset of the ADC can be significantly larger than the signal of interest (affecting the results from the signal monitor), a dc correction circuit is included as part of the signal monitor block to null the dc offset before measuring the power.
PEAK DETECTOR MODE The magnitude of the input port signal is monitored over a programmable time period (determined by SMPR) to give the peak value detected. This function is enabled by programming a Logic 1 in the signal monitor mode bits of the signal monitor control register or by setting the peak detector output enable bit in the signal monitor SPORT control register. The 24-bit SMPR must be programmed before activating this mode. After enabling this mode, the value in the SMPR is loaded into a monitor period timer and the countdown is started. The magni-tude of the input signal is compared with the value in the internal peak level holding register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the peak level holding register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register (not accessible to the user), which can be read through the SPI port or output through the SPORT serial interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the peak level holding register, and the comparison and update procedure, as explained previously, continues.
Figure 68 is a block diagram of the peak detector logic. The SMR register contains the absolute magnitude of the peak detected by the peak detector logic.
SIGNAL MONITORHOLDING
REGISTER (SMR)
MAGNITUDESTORAGEREGISTER
COMPAREA>B
TOMEMORY
MAP/SPORT
FROMMEMORY
MAP
FROMINPUTPORTS
LOAD
CLEAR
LOAD LOAD
IS COUNT = 1?DOWNCOUNTER
SIGNAL MONITORPERIOD REGISTER
065
71-0
68
Figure 68. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE In this mode, the root-mean-square (rms) or mean-square (ms) magnitude of the input port signal is integrated (by adding an accumulator) over a programmable time period (determined by SMPR) to give the rms or ms magnitude of the input signal. This mode is set by programming Logic 0 in the signal monitor mode bits of the signal monitor control register or by setting the rms magnitude output enable bit in the signal monitor SPORT control register. The 24-bit SMPR, representing the period over which integration is performed, must be programmed before activating this mode.
After enabling the rms/ms magnitude mode, the value in the SMPR is loaded into a monitor period timer, and the countdown is started immediately. Each input sample is converted to floating-point format and squared. It is then converted to 11-bit, fixed-point format and added to the contents of the 24-bit accumulator. The integration continues until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the square root of the value in the accumulator is taken and transferred, after some formatting, to the signal monitor holding register, which can be read through the SPI port or output through the SPORT serial port. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the first input sample signal power is updated in the accumulator, and the accumulation continues with the subsequent input samples.
AD9627
Rev. B | Page 37 of 76
Figure 69 illustrates the rms magnitude monitoring logic.
SIGNAL MONITORHOLDING
REGISTER (SMR)ACCUMULATOR
TOMEMORY
MAP/SPORT
FROMMEMORY
MAP
FROMINPUTPORTS
LOAD
CLEAR LOAD
IS COUNT = 1?DOWNCOUNTER
SIGNAL MONITORPERIOD REGISTER
065
71-0
69
Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitoring result (SMR) register is a 20-bit fixed-point number. The following equation can be used to determine the rms magnitude in dBFS from the MAG value in the register. Note that if the signal monitor period (SMP) is a power of 2, the second term in the equation becomes 0.
RMS Magnitude = 20 log
)(logceil20 22log10
2 SMPSMPMAG
For ms magnitude mode, the value in the SMR is a 20-bit fixed-point number. The following equation can be used to determine the ms magnitude in dBFS from the MAG value in the register. Note that if the SMP is a power of 2, the second term in the equation becomes 0.
MS Magnitude = 10 log
)(logceil20 22log10
2 SMPSMPMAG
THRESHOLD CROSSING MODE In the threshold crossing mode of operation, the magnitude of the input port signal is monitored over a programmable time period (given by SMPR) to count the number of times it crosses a certain programmable threshold value. This mode is set by programming Logic 1x (where x is a don’t care bit) in the signal monitor mode bits of the signal monitor control register or by setting the threshold crossing output enable bit in the signal monitor SPORT control register. Before activating this mode, the user needs to program the 24-bit SMPR and the 13-bit upper threshold register for each individual input port. The same upper threshold register is used for both signal monitoring and gain control (see the ADC Overrange and Gain Control section).
After entering this mode, the value in the SMPR is loaded into a monitor period timer, and the countdown is started. The magni-tude of the input signal is compared with the upper threshold register (programmed previously) on each input clock cycle. If the input signal has a magnitude greater than the upper threshold register, the internal count register is incremented by 1.
The initial value of the internal count register is set to 0. This comparison and incrementing of the internal count register continues until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value in the internal count register is transferred to the signal monitor holding register, which can be read through the SPI port or output through the SPORT serial port.
The monitor period timer is reloaded with the value in the SMPR register, and the countdown is restarted. The internal count register is also cleared to a value of 0. Figure 70 illustrates the threshold crossing logic. The value in the SMR register is the number of samples that have a magnitude greater than the threshold register.
SIGNAL MONITORHOLDING
REGISTER (SMR)
COMPAREA > B
UPPERTHRESHOLDREGISTER
COMPAREA > B
TOMEMORY
MAP/SPORT
FROMMEMORY
MAP
FROMMEMORY
MAP
FROMINPUTPORTS
LOAD
CLEAR LOAD
IS COUNT = 1?DOWNCOUNTER
SIGNAL MONITORPERIOD REGISTER
B
A
065
71-
070
Figure 70. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS For additional flexibility in the signal monitoring process, two control bits are provided in the signal monitor control register. They are the signal monitor enable bit and the complex power calculation mode enable bit.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112, enables operation of the signal monitor block. If the signal monitor function is not needed in a particular application, this bit should be cleared (default) to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing the I data and Channel B is digitizing the Q data for a complex input signal (or vice versa). In this mode, the power reported is equal to
22 QI
This result is presented in the Signal Monitor DC Value Channel A register if the signal monitor mode bits are set to 00. The Signal Monitor DC Value Channel B register continues to compute the Channel B value.
DC CORRECTION Because the dc offset of the ADC may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the ADC is digitizing a time-varying signal with significant dc content, such as GSM.
AD9627
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DC Correction Bandwidth The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing the 4-bit dc correction register located at Register 0x10C, Bits[5:2]. The following equation can be used to compute the bandwidth value for the dc correction circuit:
22__ 14 CLKk f
BWCorrDC
where: k is the 4 bit value programmed in Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD9627 ADC sample rate in hertz (Hz).
DC Correction Readback
The current dc correction value can be read back in Register 0x10D and Register 0x10E for Channel A and Register 0x10F and Register 0x110 for Channel B. The dc correction value is a 12-bit value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the dc correction at its current state and continues to use the last updated value as the dc correction value. Clearing this bit restarts dc correction and adds the currently calculated value to the data.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in the signal monitor calculations. The calculated dc correction value can be added to the output data signal path by setting Bit 1 of Register 0x10C.
SIGNAL MONITOR SPORT OUTPUT The SPORT is a serial interface with three output pins: SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and SMI SDO (SPORT data output). The SPORT is the master and drives all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4, or 1/8 the ADC clock rate, based on the SPORT controls. The SMI SCLK can also be gated off when not sending any data, based on the SPORT SMI SCLK sleep bit. Using this bit to disable the SMI SCLK when it is not needed can reduce any coupling errors back into the signal path, if these prove to be a problem in the system. Doing so, however, has the disadvantage of spreading the frequency content of the clock. If desired, the SMI SCLK can be left running to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the start of a frame. One SPORT frame includes data from both datapaths. The data from Datapath A is sent just after the frame sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data is sent MSB first on the next positive edge after the SMI SDFS. Each data output block includes one or more rms magnitude, peak level, and threshold crossing values from each datapath in the stated order. If enabled, the data is sent, rms first, followed by peak and threshold, as shown in Figure 71.
20 CYCLES 16 CYCLES16 CYCLES 20 CYCLES 16 CYCLES 16 CYCLES
SMI SDFS
MSB MSBRMS/MS CH A PK CH A PK CH B THR CH BRMS/MS CH B RMS/MS CH ALSB LSBTHR CH ASMI SDO
SMI SCLK
GATED, BASED ON CONTROL
065
71-0
71
Figure 71. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
20 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES
SMI SCLK
SMI SDFS
SMI SDO MSB MSBRMS/MS CH A RMS/MS CH ALSB THR CH A RMS/MS CH B LSB THR CH B
GATED, BASED ON CONTROL
0657
1-07
2
Figure 72. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
AD9627
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BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9627 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9627. Various output test options are also provided to place predictable values on the outputs of the AD9627.
BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9627 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If one channel is chosen, its BIST signature is written to the two registers. If both channels are chosen, the results from Channel A are placed in the BIST signature registers.
The outputs are not disconnected during this test, so the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration.
OUTPUT TEST MODES The output test options are shown in Table 25. When an output test mode is enabled, the analog section of the ADC is discon-nected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
AD9627
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CHANNEL/CHIP SYNCHRONIZATION The AD9627 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro-nized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific time period. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The signal monitor block is synchronized on every SYNC input signal.
The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 8. The SYNC input should be driven using a single-ended CMOS-type signal.
AD9627
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SERIAL PORT INTERFACE (SPI) The AD9627 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are docu-mented in the Memory Map section. For detailed operational information, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Table 22). The SCLK/DFS (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) is an active-low control that enables or disables the read and write cycles.
Table 22. Serial Port Interface Pins Pin Function SCLK Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes. SDIO Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame.
CSB Chip Select Bar. An active-low control that gates the read and write cycles.
The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 73 and Table 8.
Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits.
All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output.
In addition to word length, the instruction phase determines whetherthe serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE The pins described in Table 22 comprise the physical interface between the user programming device and the serial port of the AD9627. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in Application Note AN-812, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9627 to prevent these signals from transi-tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9627.
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CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select should be connected to AVDD, which disables the serial port interface.
Table 23. Mode Selection
Pin External Voltage Configuration
SDIO/DCS AVDD (default) Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled
SCLK/DFS AVDD Twos complement enabled AGND (default) Offset binary enabled
SMI SDO/OEB AVDD Outputs in high impedance AGND (default) Outputs enabled
SMI SCLK/PDWN AVDD Chip in power-down or standby
AGND (default) Normal operation
SPI ACCESSIBLE FEATURES Table 24 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in Application Note AN-877, Interfacing to High Speed ADCs via SPI. The AD9627 part-specific features are described in detail following Table 25, the external memory map register table.
Table 24. Features Accessible Using the SPI Feature Name Description Mode Allows the user to set either power-down mode
or standby mode Clock Allows the user to access the DCS via the SPI Offset Allows the user to digitally adjust the
converter offset Test I/O Allows the user to set test modes to have
known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
tS tDH
tCLKtDS tH
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
tLOW
tHIGH
065
71-0
73
Figure 73. Serial Port Interface Timing Diagram
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x25); and the digital feature control registers (Address 0x100 to Address 0x11B).
The memory map register table (see Table 25) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF select register, has a hexadecimal default value of 0xC0. This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, from Register 0x100 to Register 0x11B, are documented in the Memory Map Register Description section.
Open Locations
All address and bit locations that are not included in Table 25 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written.
Default Values
After the AD9627 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 25.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simulta-neously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 25 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 25 affect the entire part or the channel features where independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.
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MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 25 are not currently supported for this device.
Table 25. Memory Map Registers
Addr (Hex)
Register Name
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 (LSB)
Default Value (Hex)
Default Notes/ Comments
Chip Configuration Registers
0x00 SPI Port Configuration (Global)
0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles are mirrored so LSB-first mode or MSB-first mode registers correctly, regardless of shift mode
0x01 Chip ID (Global)
8-bit Chip ID[7:0] (AD9627 = 0x12)
(default)
0x12 Read only
0x02 Chip Grade (Global)
Open Open Speed grade ID 00 = 150 MSPS 01 = 125 MSPS 10 = 105 MSPS 11 = 80 MSPS
Open Open Open Open Speed grade ID used to differentiate devices; read only
Channel Index and Transfer Registers
0x05 Channel Index Open Open Open Open Open Open Data Channel B (default)
Data Channel A (default)
0x03 Bits are set to determine which device on the chip receives the next write command; applies to local registers only
0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave
ADC Functions
0x08 Power Modes Open Open External power-down pin function (global) 0 = pdwn 1 = stndby
Open Open Open Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation
0x00 Determines various generic modes of chip operation
0x09 Global Clock (Global)
Open Open Open Open Open Open Open Duty cycle stabilizer (default)
0x01
0x0B Clock Divide (Global)
Open Open Open Open Open Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8
0x00 Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active
0x0D Test Mode (Local)
Open Open Reset PN23 gen
Reset PN9 gen
Open Output test mode 000 = off (default) 001 = midscale short 010 = positive FS 011 = negative FS 100 = alternating checkerboard 101 = PN 23 sequence 110 = PN 9 sequence 111 = one/zero word toggle
0x00 When this register is set, the test data is placed on the output pins in place of normal data
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Addr (Hex)
Register Name
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 (LSB)
Default Value (Hex)
Default Notes/ Comments
0x0E BIST Enable (Local)
Open Open Open Open Open Reset BIST sequence
Open BIST enable 0x00
0x10 Offset Adjust (Local)
Open Open Offset adjust in LSBs from +31 to −32 (twos complement format)
0x00
0x14 Output Mode Drive strength 0 V to 3.3 V CMOS or ANSI LVDS; 1 V to 1.8 V CMOS or reduced LVDS (global)
Output type 0 = CMOS 1 = LVDS (global)
Open Output enable bar(local)
Open Output invert (local)
00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary
(local)
0x00 Configures the outputs and the format of the data
0x16 Clock Phase Control (Global)
Invert DCO clock
Open Open Open Open Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles
0x00 Allows selection of clock delays into the input clock divider
0x17 DCO Output Delay (Global)
Open Open Open DCO clock delay (delay = 2500 ps × register value/31)
00000 = 0 ps 00001 = 81 ps 00010 = 161 ps … 11110 = 2419 ps 11111 = 2500 ps
0x00
0x18 VREF Select (Global)
Reference voltage selection 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default)
Open Open Open Open Open Open 0xC0
0x24 BIST Signature LSB (Local)
BIST Signature[7:0] 0x00 Read only
0x25 BIST Signature MSB (Local)
BIST Signature[15:8] 0x00 Read only
Digital Feature Control
0x100 Sync Control (Global)
Signal monitor sync enable
Open Open Open Open Clock divider next sync only
Clock divider sync enable
Master sync enable
0x00
0x104 Fast Detect Control (Local)
Open Open Open Open Fast Detect Mode Select[2:0] Fast detect enable
0x00
0x105 Coarse Upper Threshold (Local)
Open Open Open Open Open Coarse Upper Threshold[2:0] 0x00
0x106 Fine Upper Threshold Register 0 (Local)
Fine Upper Threshold[7:0] 0x00
0x107 Fine Upper Threshold Register 1 (Local)
Open Open Open Fine Upper Threshold[12:8] 0x00
0x108 Fine Lower Threshold Register 0 (Local)
Fine Lower Threshold[7:0] 0x00
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Addr (Hex)
Register Name
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 (LSB)
Default Value (Hex)
Default Notes/ Comments
0x109 Fine Lower Threshold Register 1 (Local)
Open Open Open Fine Lower Threshold[12:8] 0x00
0x10A Increase Gain Dwell Time Register 0 (Local)
Increase Gain Dwell Time[7:0] 0x00 In ADC clock cycles
0x10B Increase Gain Dwell Time Register 1 (Local)
Increase Gain Dwell Time[15:8] 0x00 In ADC clock cycles
0x10C Signal Monitor DC Correction Control (Global)
Open DC correction freeze
DC Correction Bandwidth[3:0] DC correction for signal path enable
DC correction for signal monitor enable
0x00
0x10D Signal Monitor DC Value Channel A Register 0 (Global)
DC Value Channel A[7:0] Read only
0x10E Signal Monitor DC Value Channel A Register 1 (Global)
Open Open DC Value Channel A[13:8] Read only
0x10F Signal Monitor DC Value Channel B Register 0 (Global)
DC Value Channel B[7:0] Read only
0x110 Signal Monitor DC Value Channel B Register 1 (Global)
Open Open DC Value Channel B[13:8] Read only
0x111 Signal Monitor SPORT Control (Global)
Open RMS/MS magnitude output enable
Peak detector output enable
Threshold crossing output enable
SPORT SMI SCLK divide
00 = undefined 01 = divide by 2 10 = divide by 4 11 = divide by 8
SPORT SMI SCLK sleep
Signal monitor SPORT output enable
0x04
0x112 Signal Monitor Control (Global)
Complex power calculation mode enable
Open Open Open Signal monitorrms/ms select
0 = rms 1 = ms
Signal monitor mode 00 = rms/ms magnitude 01 = peak detector 10 = threshold crossing 11 = threshold crossing
Signal monitor enable
0x00
0x113 Signal Monitor Period Register 0 (Global)
Signal Monitor Period[7:0] 0x80 In ADC clock cycles
0x114 Signal Monitor Period Register 1 (Global)
Signal Monitor Period[15:8] 0x00 In ADC clock cycles
0x115 Signal Monitor Period Register 2 (Global)
Signal Monitor Period[23:16] 0x00 In ADC clock cycles
0x116 Signal Monitor Result Channel A Register 0 (Global)
Signal Monitor Result Channel A[7:0] Read only
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Addr (Hex)
Register Name
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 (LSB)
Default Value (Hex)
Default Notes/ Comments
0x117 Signal Monitor Result Channel A Register 1 (Global)
Signal Monitor Result Channel A[15:8] Read only
0x118 Signal Monitor Result Channel A Register 2 (Global)
Open Open Open Open Signal Monitor Value Channel A[19:16] Read only
0x119 Signal Monitor Result Channel B Register 0 (Global)
Signal Monitor Result Channel B[7:0] Read only
0x11A Signal Monitor Result Channel B Register 1 (Global)
Signal Monitor Result Channel B[15:8] Read only
0x11B Signal Monitor Result Channel B Register 2 (Global)
Open Open Open Open Signal Monitor Result Channel B[19:16] Read only
MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external SYNC input to the signal monitor block. The sync signal is passed when Bit 7 and Bit 0 are high. This is continuous sync mode.
Bits[6:3]—Reserved Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is passed when Bit 1 is high and Bit 0 is high. This is continuous sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved Bits[3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output pins (see Table 17).
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the fast detect output pins are disabled, the outputs go into a high impedance state. In LVDS mode, when the outputs are interleaved, the outputs go high-Z only if both channels are turned off (power-down/standby/output disabled). If only one channel is turned off (power-down/standby/output disabled), the fast detect output pins repeat the data of the active channel.
Coarse Upper Threshold (Register 0x105)
Bits[7:3]—Reserved Bits[2:0]—Coarse Upper Threshold
These bits set the level required to assert the coarse upper threshold indication (see Table 21).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0] Register 0x107, Bits[7:5]—Reserved Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]
These registers provide the fine upper limit threshold. This 13-bit value is compared with the 13-bit magnitude from the ADC block. If the ADC magnitude exceeds this threshold value, the F_UT flag is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0] Register 0x109, Bits[7:5]—Reserved Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8]
These registers provide the fine lower limit threshold. This 13-bit value is compared with the 13-bit magnitude from the ADC block. If the ADC magnitude is less than this threshold value, the F_LT flag is set.
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Increase Gain Dwell Time (Register 0x10A and Register 0x10B)
Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0] Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8]
These registers are programmed with the dwell time in ADC clock cycles for which the signal must be below the fine lower threshold value before the increase gain output is asserted.
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved Bit 6—DC Correction Freeze
When Bit 6 is set high, the dc correction is no longer updated to the signal monitor block. It holds the last dc value it calculated.
Bits[5:2]—DC Correction Bandwidth
These bits set the averaging time of the power monitor dc correction function. This 4-bit word sets the bandwidth of the correction block according to the following equation:
22__ 14 CLKk f
BWCorrDC
where: k is the 4 bit value programmed in Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD9627 ADC sample rate in hertz (Hz).
Bit 1—DC Correction for Signal Path Enable
Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path.
Bit 0—DC Correction for Signal Monitor Enable
Bit 0 enables the dc correction function in the signal monitor block. The dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. Removing this dc offset from the measurement allows a more accurate reading.
Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
Register 0x10D, Bits[7:0]—DC Value Channel A[7:0] Register 0x10E, Bits[7:6]—Reserved Register 0x10E, Bits[5:0]—DC Value Channel A[13:8]
These read-only registers hold the latest dc offset value computed by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
Register 0x10F, Bits[7:0]—DC Value Channel B[7:0] Register 0x110, Bits[7:6]—Reserved Register 0x110, Bits[5:0]—DC Value Channel B[13:8]
These read-only registers hold the latest dc offset value computed by the signal monitor for Channel B.
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable
These bits enable the 20-bit rms or ms magnitude measurement as output on the SPORT.
Bit 5—Peak Detector Output Enable
Bit 5 enables the 13-bit peak measurement as output on the SPORT.
Bit 4—Threshold Crossing Output Enable
Bit 4 enables the 13-bit threshold measurement as output on the SPORT.
Bits[3:2]—SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio from the input clock. A value of 0x01 sets divide by 2 (default), a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Bit 1— SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the signal monitor block has no data to transfer.
Bit 0—Signal Monitor SPORT Output Enable
When set, Bit 0 enables the SPORT output of the signal monitor to begin shifting out the result data from the signal monitor block.
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
This mode assumes I data is present on one channel and Q data is present on the alternate channel. The result reported is the complex power, measured as
22 QI
Bits[6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting Bit 3 high selects ms power measurement mode.
Bits[2:1]—Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for data output to Register 0x116 through Register 0x11B. Setting Bit 2 and Bit 1 to 0x00 selects rms/ms magnitude output; setting these bits to 0x01 selects peak detector output; and setting these bits to 0x10 or 0x11 selects threshold crossing output.
Bit 0—Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
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Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16]
This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. The minimum value for this register is 128 cycles; programmed values less than 128 revert to 128.
Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16]
This 20-bit value contains the result calculated by the signal monitoring block for Channel A. The result is dependent on the settings in Register 0x112[2:1].
Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0] Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x11B, Bits[7:4]—Reserved Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16]
This 20-bit value contains the result calculated by the signal monitoring block for Channel B. The result is dependent on the settings in Register 0x112[2:1].
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9627 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9627, it is recommended that two separate 1.8 V supplies be used: one supply should be used for analog (AVDD) and digital (DVDD), and a separate supply should be used for the digital outputs (DRVDD). The AVDD and DVDD supplies, while derived from the same source, should be isolated with a ferrite bead or filter choke and separate decoupling capacitors. The designer can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the pins of the part with minimal trace length.
A single PCB ground plane should be sufficient when using the AD9627. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved.
LVDS Operation
The AD9627 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed using the SPI configuration registers after power-up. When the AD9627 powers up in CMOS mode with LVDS termination resistors (100 Ω) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9627, but it should be taken into account when consid-ering the maximum DRVDD current for the part.
To avoid this additional DRVDD current, the AD9627 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed into LVDS mode via the SPI port, the OEB pin can be taken low to enable the outputs.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask), copper plane on the PCB should mate to the AD9627 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evalua-tion board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, see Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
CML
The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 47.
RBIAS
The AD9627 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9627 to keep these signals from transitioning at the converter inputs during critical sampling periods.
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EVALUATION BOARD The AD9627 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configura-tions. The converter can be driven differentially through a double balun configuration (default) or optionally through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry. Each input configuration can be selected by proper connection of various components (see Figure 75 to Figure 92). Figure 74 shows the typical bench characterization setup used to evaluate the ac performance of the AD9627.
It is critical that the signal sources used for the analog input and clock have very low phase noise (<<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.
See Figure 75 to Figure 79 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level.
POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The output of the supply is a 2.1 mm inner diameter circular jack that connects to the PCB at J16. Once on the PC board, the 6 V supply is fused and conditioned before connection to six low dropout linear regulators that supply the proper bias to each of the various sections on the board.
External supplies can be used to operate the evaluation board by removing L1, L3, L4, and L13 to disconnect the voltage regulators supplied from the switching power supply. This enables the user to individually bias each section of the board. Use P3 and P4 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for AVDD and DVDD; a separate 1.8 V to 3.3 V supply is recom-mended for DRVDD. To operate the evaluation board using the AD8352 option, a separate 5.0 V supply (AMP VDD) with a 1 A current capability is needed. To operate the evaluation board using the alternate SPI options, a separate 3.3 V analog supply (VS) is needed, in addition to the other supplies. The 3.3 V supply (VS) should have a 1 A current capability, as well. Solder Jumper SJ35 allows the user to separate AVDD and DVDD, if desired.
INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA100A signal generators or the equivalent. Use 1 m long, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude for the ADC. The AD9627 evaluation board from Analog Devices, Inc., can accept a ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recom-mended that a multipole, narrow-band, band-pass filter with 50 Ω terminations be used. Band-pass filters of this type are available from TTE, Allen Avionics, and K&L Microwave, Inc. Connect the filter directly to the evaluation board, if possible.
OUTPUT SIGNALS The parallel CMOS outputs interface directly with the Analog Devices standard ADC data capture board (HSC-ADC-EVALCZ). For more information on the ADC data capture boards and their optional settings, visit www.analog.com/FIFO.
USBCONNECTION
AD9627EVALUATION BOARD
12-BITPARALLEL
CMOS
12-BITPARALLEL
CMOS
HSC-ADC-EVALCZFPGA BASED
DATACAPTURE BOARD
PC RUNNINGVISUAL ANALOG
AND SPICONTROLLER
SOFTWARE
1.8V– +– +
AV
DD
IN
VS
DR
VD
D I
N
GN
D
GN
D
– +5.0V
GN
D
AM
P V
DD
3.3V
6V DC2A MAX
WALL OUTLET100V TO 240V AC47Hz TO 63Hz
SWITCHINGPOWERSUPPLY
– +
GN
D
3.3V
VC
P
– +
GN
D
3.3V
SPI SPI
0657
1-07
4
ROHDE & SCHWARZ,SMA100A,
2V p-p SIGNALSYNTHESIZER
CLK
ROHDE & SCHWARZ,SMA100A,
2V p-p SIGNALSYNTHESIZER
AINBBAND-PASSFILTER
ROHDE & SCHWARZ,SMA100A,
2V p-p SIGNALSYNTHESIZER
AINABAND-PASSFILTER
Figure 74. Evaluation Board Connection
AD9627
Rev. B | Page 52 of 76
DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9627 evaluation board.
POWER
Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double balun configuration analog input with optimum 50 Ω impedance matching from 70 MHz to 200 MHz. For more bandwidth response, the differ-ential capacitor across the analog inputs can be changed or removed (see Table 13). The common mode of the analog inputs is developed from the center tap of the transformer via the CML pin of the ADC (see the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground by adding a jumper on Header J5 (Pin 1 to Pin 2). This causes the ADC to operate in 2.0 V p-p full-scale range. To place the ADC in 1.0 V p-p mode (VREF = 0.5 V), a jumper should be placed on Header J4. A separate external reference option is also included on the evalua-tion board. To use an external reference, connect J6 (Pin 1 to Pin 2) and provide an external reference at TP5. Proper use of the VREF options is detailed in the Voltage Reference section.
RBIAS RBIAS requires a 10 kΩ resistor (R503) to ground and is used to set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple balun-coupled circuit using a high bandwidth 1:1 impedance ratio balun (T5) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD9627 input clock divider is utilized, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5.
PDWN
To enable the power-down feature, connect J7, shorting the PDWN pin to AVDD.
CSB
The CSB pin is internally pulled up, setting the chip into external pin mode, to ignore the SDIO and SCLK information. To connect the control of the CSB pin to the SPI circuitry on the evaluation board, connect J21, Pin 1 to J21, Pin 2.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the data format of the outputs. If the pin is left floating, the pin is inter-nally pulled down, setting the default data format condition to offset binary. Connecting J2, Pin 1 to J2, Pin 2 sets the format to twos complement. If the SPI port is in serial pin mode, connecting J2, Pin 2 to J2, Pin 3 connects the SCLK pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin sets the duty cycle stabilizer. If the pin is left floating, the pin is internally pulled up, setting the default condition to DCS enabled. To disable the DCS, connect J1, Pin 1 to J1, Pin 2. If the SPI port is in serial pin mode, connecting J1, Pin 2 to J1, Pin 3 connects the SDIO pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS Two alternate clocking options are provided on the AD9627 evaluation board. The first option is to use an on-board crystal oscillator (Y1) to provide the clock input to the part. To enable this crystal, Resistor R8 (0 Ω) and Resistor R85 (10 kΩ) should be installed, and Resistor R82 and Resistor R30 should be removed.
A second clock option is to use a differential LVPECL clock to drive the ADC input using the AD9516 (U2). When using this drive option, the AD9516 charge pump filter components need to be populated (see Figure 79). Consult the AD9516 data sheet for more information.
To configure the clock input from S5 to drive the AD9516 reference input instead of directly driving the ADC, the following components need to be added, removed, and/or changed.
1. Remove R32, R33, R99, and R101 in the default clock path.
2. Populate C78 and C79 with 0.001 μF capacitors and R78 and R79 with 0 Ω resistors in the clock path.
In addition, unused AD9516 outputs (one LVDS and one LVPECL) are routed to optional Connector S8 through Connector S11 on the evaluation board.
AD9627
Rev. B | Page 53 of 76
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet.
To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for Channel A. For Channel B the corresponding components should be changed.
1. Remove C1, C17, C18, and C117 in the default analog input path.
2. Populate C8 and C9 with 0.1 μF capacitors in the analog input path. To drive the AD8352 in the differential input mode, populate the T10 transformer; the R1, R37, R39, R126, and R127 resistors; and the C10, C11, and C125 capacitors.
3. Populate the optional amplifier output path with the desired components including an optional low-pass filter. Install 0 Ω resistors, R44 and R48. R43 and R47 should be increased (typically to 100 Ω) to increase to 200 Ω the output impedance seen by the AD8352.
AD9627
Rev. B | Page 54 of 76
SCHEMATICS
06571-075
BA
IND
060
312
123
654
IND
060
312
912E
NB15 6
7
432
813
VC
M
14
VIN
5
VIP
16
VO
N10
VO
P11
AD
8352
1
VC
C
GN
D
GN
D
GN
D
VC
C
RG
N
RD
N
RG
P
RD
P
1
2
54
123
PSF
54
123
PSF
1 1
5 4
1 2 3
PS F
IND
060
312
1
2
IND
060
312
DN
PD
NP
DN
P
OP
TIO
NA
LA
MP
LIF
IER
INP
UT
PA
TH
DE
FA
UL
TA
MP
LIF
IER
INP
UT
PA
TH
Tra
nsf
orm
er/a
mp
chan
nel
A
AIN
+
AIN
-
DN
PD
NP
DN
P
L16
180
NH
R31
0O
HM
C16
0.00
1U
R5
57.6 OHM
R1
57.6 OHM
R28
57.6 OHM
R126
4.12K
R27
33
OH
M
R26
33
OH
M
R41
10K OHM
R40
10K
OH
M
S2
AM
P+A
L17
180
NH
VIN
-A
AV
DD
R50
0O
HM
VIN
+A
AM
P+A
AM
P-A
INA+INA-
INA
-
INA+
ET
C1-
1-13
T10
C1
25.3
PF
R127
100 OHM
R1
21 RE
S04
02
0O
HM
R4
0 OHM
R48
0O
HM
R49 0
OH
M
R47
33 OHM
R43
33 OHM
R42
0O
HM
R44
0O
HM
R11
0
0O
HM
R2
0O
HM
R1
20
0O
HM
R39
0O
HM
R38
DN
P
R37
0O
HM
R36
DNP
R54
0O
HM
R35
24.9 OHM
R29
24.9 OHM
TP
15
TP
14
C27
10U
C23
0.1
UC
220.
1U
ET
C1-
1-13
T2
ETC
1-1
-13
T1
CM
L
CM
L
AV
DD
AM
P-A
AM
PV
DD
C9
0.1U
C4
18P
FC
139
12P
F
C5
4.7
PF
C12
0.00
1U
C3
0.1
U
C1
0.1
U
C8
0.1U
C10
0.1U C
11
0.1
U
C47
0.1U
C11
7
0.1
U
C17
0.1
U
C18
0.1
U
C2
0.1
U
S1
Z1
L14
120
NH
AD
T1_
1WT
T7
L15
120
NH
AM
PV
DD
W1
AM
PV
DD
Figure 75. Evaluation Board Schematic, Channel A Analog Inputs
AD9627
Rev. B | Page 55 of 76
06571-076
BA
EN
BV
CM
VIN
VIP
VO
N
VO
P
AD
8352
VC
C
GN
D
GN
D
GN
D
VC
C
RG
N
RD
N
RG
P
RD
P
PS F
IND
0603
IND
060
3
IND
060
3IN
D06
03
PS F
PS F
DN
PD
NP
DN
P
DN
PD
NP
OP
TIO
NA
LA
MP
LIF
IER
INP
UT
PA
TH
DE
FA
UL
TA
MP
LIF
IER
INP
UT
PA
TH
AIN
+
AIN
-
DN
P
R13
3
DN
P
R72
57.6 OHM
R52
57.6 OHM
R51
57.6 OHM
R128
4.12K
R73
33O
HM R
74
33
OH
M
R70
33 OHM
R71
33 OHM
R53
10K OHM
AM
PV
DD
R13
1
10K
OH
M
R135
24.9 OHM
R129
100 OHM
R69
0 OHM
R67
0O
HM
R1
23
RE
S04
020
OH
M
R12
2
RE
S0
402
0O
HM
R1
11
0O
HM
R94
0O
HM
R95
0O
HM
R96
0O
HM
R81
0O
HM
R80
0O
HM
R55
0O
HM
R6
0O
HM
R68
DNP
R134
24.9 OHM
R1
32
0O
HM
R66
0O
HM
321
45
ET
C1-
1-13
T4
456
321AD
T1_
1WT
T8
321
45
ET
C1
-1-13
T3
C51
0.1
U
C28
0.1
UINB
-
INB
+
CM
LA
MP
-B
AM
P+B
CM
L
VIN
-B
AV
DD
AV
DD
AM
P-B
AM
P+B
AMPVDD
INB
-
INB
+
C19
18P
F
C29
12PF
C84
4.7
PF
C1
28
.3PF
C46
0.0
01U
C1
40
0.0
01U
C38
0.1
U
C30
0.1U
C31
0.1U
C82
0.1
U
C83
0.1U
C24
0.1
U
C7
0.1U
C39
0.1
U
C6
0.1
U
2
1
S3
2
1
S4
1TP
16
1TP
17
12
L19
120
NH
12
L21
180N
H
12
L20
180N
H
12
L18
120
NH
321
45
ET
C1
-1-13
T11
912
67
15
41 32
813
51614
1011
Z2
W2
C62
10U
C61
0.1
UC
600.
1U
AM
PV
DD
VIN
+B
Figure 76. Evaluation Board Schematic, Channel B Analog Inputs
AD9627
Rev. B | Page 56 of 76
06571-077
PS F
EN
C
EN
C\
VS
C14
5
0.1
U
C2
0
0.1
U
R85
10K OHM
R8
0 OHM
21
TP2
R8
4
24.9
OH
M
R79
0O
HM
R34
DNP
R10
1
0O
HM
R3
0O
HM
R7
57.6 OHMR
90
0O
HM
R30
57.6 OHMR
32
0O
HM
R33
0O
HM
R9
9
0O
HM
R7
8
0O
HM
R82
10K OHM
ALT
CLK
-
C6
4
0.00
1U
C94
0.00
1U
321
45
ET
C1-
1-13
T5
C7
9
0.00
1U
OP
T_C
LK-
CLK
-CLK
+
OP
T_C
LK+
OP
T_
CLK
+
C7
7
0.00
1U
C7
8
0.00
1U
C6
3
0.00
1U
C5
6
0.1
U
C2
1
0.1
U
2
1
SM
A20
0UP
S6
2
1
SM
A20
0UP
S5
4 5 6
3 2 1 AD
T1_
1WT
T9
OP
T_C
LK-
ALT
CLK
+
R83
24.9 OHM
Figure 77. Evaluation Board Schematic, DUT Clock Input
AD9627
Rev. B | Page 57 of 76
06571-078
TE
ST
TE
ST T
ES
T
BY
PA
SS
_LD
O
CL
K
CP
CP_RSET
GN
D_E
SD
GN
D_O
UT
89_D
IV
GND_REF
LD
LF
NC
1
NC2
NC3
NC4
OUT0
OUT1
OU
T2
OU
T3
OUT4
OUT5
OU
T6
OU
T7
OU
T8
OU
T9
REFIN
RE
FM
ON
RE
F_
SE
L
RSET_CLOCK
SC
LK
SDIO
SDO
ST
AT
US
VC
P
VS
_CLK
_D
IST
VS_OUT01_DIV
VS_OUT01_DRV
VS
_OU
T2
3_D
IV
VS
_O
UT
23_
DR
V
VS_OUT45_DIV
VS_OUT45_DRV
VS_OUT67_1
VS_OUT67_2VS_OUT89_1
VS_OUT89_2
VS
_PLL
_1
VS_PLL_2
VS_PRESCALER
VS_REF
VS
_VC
O
CL
KB
CSB
OUT0B
OUT1B
OU
T2
B
OU
T3
B
OUT4B
OUT5B
OU
T6
B
OU
T7
B
OU
T8
B
OU
T9
B
PDB
REFINB
RESETB
SY
NC
BA
D95
16_6
4LF
CS
P
PAD
2
AD
9516
CLK
IN
LVD
S
OU
TP
UT
LVP
EC
LO
UT
PU
T
TO
AD
CLV
PE
CL
1
S7 V
CX
O_C
LK-
R89
49.9 OHM
R12
4.12K
R9
100 OHM
R75
100 OHM
1TP
8
2
1
S1
1
OU
T6
P
OU
T6
N
10
135
62
44
37
59
3 9
15
18
19
20
56
53
43
40
25
28
48
46
33
35
2 7
58
22
21
64
12
51
54
38
41
30
27
49
50 31
32
61
60
57
11
14
17
55
52
42
39
26
29
47
45
34
36
24
63
23
81
16
64
U2
20
0R
91
200
R8
6
R11
5.1K
200
R8
8
20
0R
92
R1
25
RE
S04
020O
HM
R1
24
RE
S04
020O
HM
R1
0
0O
HM
C10
4
0.1
U
C1
01
0.1
U
C9
8
0.1
U
C9
9
0.1
UC
96
0.1
UC
97
0.1
U
C10
0
0.1
U
SY
NC
VC
PV
S_
OU
T_
DR
VC
XO
_C
LK+
1
TP
18
LD
1
TP
19
C8
0
18P
F
C14
1
0.0
01U
C8
6
0.1
U
C8
5
0.1
U
C8
7
0.1
U
C8
8
0.1
U
C14
3
0.1
U
C14
2
0.1
U
2
1
S1
0
2
1
S9
2
1
S8
1
TP
20
OP
T_C
LK+
SC
LKVS
SY
NC
B
RESETB
OP
T_C
LK-
PDB
CSB_2
VS
VS
VS
VS
VS
VS_OUT_DR
VS
_OU
T_D
R
VS
VS
_O
UT
_D
R
VC
P
SDO
SDI
RE
F_
SE
L
LF
AG
ND
AG
NDA
GN
DC
P
BY
PA
SS
_LD
O
ST
AT
US
RE
FM
ON
ALT
CLK
-
ALT
CLK
+
Figure 78. Evaluation Board Schematic, Optional AD9516 Clock Circuit
AD9627
Rev. B | Page 58 of 76
06571-079
A1
GN
D
A2
Y1
VC
C Y2
OU
T2
OU
T1
VC
C
GN
D
OU
T_D
ISA
BLE
FR
EQ
_CT
RL_
V VS
-500
AC
VA
LV
AL
VA
L
VA
L
VA
L
Ch
arg
eP
um
pF
ilter
SY
NC
VS
VS
C14
4S
EL
C92
SE
L
C89
SE
L
R93
R87
24.9 OHM
R98
R13
6R
137
R97
R11
7
RE
S04
020O
HM
R11
6
RE
S04
020O
HM
R108
RES0402
10K OHM
R109
RES0402
10K OHM
R107
RES0402
10K OHM
R106
RES0402
10K OHM
R13
9
RE
S04
020O
HM
R11
4
RE
S04
020O
HM
R105
RES0402
10K OHM
R103
RES0402
10K OHM
R102
RES0402
10K OHM
R100
RES0402
10K OHM
SY
NC
R10
4
RE
S04
020O
HM
R46
RE
S04
02
33
OH
M
200
R76
R45
RES0603
57.6 OHM
LD
RE
SE
TBS
YN
CBP
DB
RE
F_S
EL
VS
VS
VS
VS
VC
XO
_CLK
-
VC
XO
_CLK
+
VC
P
VC
P
LF
CP
456
321
U25
OS
CV
EC
TR
ON
_VS
500
C91
SE
L
C90
SE
L
C25
0.1U
C26
0.1U
2
1
SM
A20
0UP
S12
1TP1
456
321
NL2
7WZ
04
U3
BY
PA
SS
_LDO
Figure 79. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input
AD9627
Rev. B | Page 59 of 76
06571-080
J7-
INS
TA
LLF
OR
PD
WN
J8-
INS
TA
LLF
OR
OU
TP
UT
DIS
AB
LE
J5-
INS
TA
LLF
OR
IVV
RE
F/2
VIN
PU
TS
PA
N
J4-
INS
TA
LLF
OR
0.5V
VR
EF
/IV
INP
UT
SP
AN
J6-
INS
TA
LLF
OR
EX
TE
RN
AL
RE
FE
RE
NC
EM
OD
E
AD
9627
36 4549
50
41
58
25
6
26
7
27
8
28913
5914
6015
6116
62
17
6318
2
19
3
22
4
23
511 1012
64
20
1
21
2457
2953
30
54
31
55
32
56
4634 3533 4240
51
4847
52
37 4438 4339
U1
D3
A
D6
B
5 6 7 8
4 3 2 1
22
oh
m
RP
AK
4R
58
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
22
oh
m
RP
AK
8
R60
AV
DD
R112
RES0402
0 OHM
R11
5 RE
S04
02
0O
HM
R11
3 RE
S04
02
0O
HM
1T
P6
R63
RE
S04
02
10K
OH
M
C15
1U
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
22
ohm
RP
AK
8
R59
FD
0B
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
22 o
hm
RP
AK
8
R57
FD
1B
FD
2B
FD
3B
SP
AR
E1
SP
AR
E2
D0
BD
1B
D2
BD
3B
D1
1B
D1
0B
D9
BD
8B
D7
B
D5
BD
4B
DC
OB
DC
OA
SP
AR
E3
SP
AR
E4
D0
AD
1A
D2
A
D4
AD
5A
D6
AD
7A
D8
AD
9A
D10
AD
11A
DV
DD
AV
DD
PWR_SDFS
FD0A
PWR_SDOPWR_SCLK
FD3AFD2AFD1A
DR
VD
D
11 11
C10
9
0.1U
C12
1
0.1U
C12
2
0.00
1U
C12
60.
001U
C12
70.
001U
C34
0.1U
C33
0.00
1U
C35
0.00
1UC36
0.1U
C32
0.1U
C14
0.1U
C40
0.1U
C12
00.
1U
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1
22 o
hm
RP
AK
8
R61
1T
P3
1 TP
5
910111213141516
87654321
22 ohmRPAK8
R62
DVDD DVDD
SYNC
SPI_CSB
CLK-
CLK+
AV
DD
VIN
+A
VIN
-A
VIN
-B
VIN
+B
AV
DD
AV
DD
SP
I_S
DIO
SP
I_S
CL
K
DR
VD
D
CM
L
DR
VD
D
C13
7
0.00
1U
R64
RE
S04
02
0O
HM
AV
DD
1
AV
DD
2CLK+
CLK-
CM
L
D8A
D8B
D9A
D9B
D10A
D10
BD11A_MSB_
D11
B_M
SB
D0A
_LSB
D0B_LSBD
1AD1B
D2A
D2B
D3A
D3BD4A
D4B
D5B
D6A
D6B
D7A
D7B
DC
OA
DC
OB
NC
DRGND
DRGND1
DR
VD
D
DRVDD1
DVDD1DVDD2
FD0AFD0B
FD1A
FD1B
FD2A
FD2B
FD3A
FD3B
AV
DD
3
SM
I_S
CLK
/PD
WN
SM
I_S
DFS
SM
I_S
DO
/OEB
RB
IAS
SE
NSE
SPI_CSB
SP
I_S
CLK
/DFS
SP
I_S
DIO
/DCS
SYNC
VIN
+A
VIN
+B
VIN
-A
VIN
-B
VR
EF
NC
NC
NC
D5A
Figure 80. Evaluation Board Schematic, DUT
AD9627
Rev. B | Page 60 of 76
06571-081
TE
ST
TE
ST
TE
ST T
ES
T
VAL
CH
AN
NE
LA
CH
AN
NE
LB
DIG
ITA
L/H
SC
-AD
C-E
VA
LC
ZIN
TE
RF
AC
E
484746454443424140393837363534333231302928272625
123456789101112131415161718192021222324
74V
CX
162
244M
TD
U1
7
484746454443424140393837363534333231302928272625
123456789101112131415161718192021222324
74V
CX
162
244M
TD
U1
6
484746454443424140393837363534333231302928272625
123456789101112131415161718192021222324
74V
CX
162
244M
TD
U1
5
SD
I
CS
B
SC
LK
R1
45
RE
S04
020O
HM
R14
2
RE
S04
020O
HM
SD
O
R14
1
RE
S04
020O
HMR
119
RE
S04
020O
HM
CS
B_
2
V_
DIG
VS
R140
RES0402
10K OHM
R118
RES0402
10K OHM
R130 R77
100 OHM
SY
NC
OU
T6
N
OU
T6
P
OU
T6
P
OU
T6
N
FD
0BF
D1B
DG
10
DG
9D
G8
DG
7D
G6
DG
5D
G4
DG
3D
G2
DG
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B1
0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C1
0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0
BG
10
BG
9B
G8
BG
7B
G6
BG
5B
G4
BG
3B
G2
BG
1
TY
CO
_HM
-ZD
J11
V_
DIG
V_D
IG
FD
2BF
D3B
SP
AR
E1S
PA
RE2
D0B
D1B
V_D
IGD
2BD
3B
D4B
D5B
V_
DIGV_
DIG
V_D
IG
V_D
IG
D6B
D7B
D8B
D9B
D10
BD
11B
DC
OB
DC
OA
SP
AR
E3S
PA
RE4
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
V_D
IGD
10A
D1
1A
FD
3AF
D2A
FD
1AF
D0A
V_
DIG
PW
R_
SDO
PW
R_S
DF
SS
CLK
_OU
TS
DF
S_
OU
T
SD
O_
OUT
PW
R_S
CLK
SD
O_O
UT
1T
P23
SC
LK_O
UTS
DF
S_
OUT
1
TP
21
V_
DIG
C6
5
0.1
U
VS
C7
1
0.1
U
C7
0
0.1U
C6
9
0.1
U
C6
8
0.1
U
C6
6
0.1
U
C6
7
0.1U
C7
2
0.1U
C7
3
0.1
U
C7
6
0.1
U
C7
4
0.1U
C7
5
0.1
U
RE
SE
TB
DG
10
DG
9D
G8
DG
7D
G6
DG
5D
G4
DG
3D
G2
DG
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B1
0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C1
0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0
BG
10
BG
9B
G8
BG
7B
G6
BG
5B
G4
BG
3B
G2
BG
1
TY
CO
_HM
-ZD
J12
DG
10
DG
9D
G8
DG
7D
G6
DG
5D
G4
DG
3D
G2
DG
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B1
0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C1
0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0
BG
10
BG
9B
G8
BG
7B
G6
BG
5B
G4
BG
3B
G2
BG
1
TY
CO
_HM
-ZD
J10
1
TP
22
1T
P24
V_D
IG
R14
3
RE
S04
020O
HM
R1
44
RE
S04
020O
HM
Figure 81. Evaluation Board Schematic, Digital Output Interface
AD9627
Rev. B | Page 61 of 76
06571-082
Y1
VC
C
Y2
A1
GN
D
A2
Y1
VC
C
Y2
A1
GN
D
A2
J1 -
JU
MP
ER
PIN
S 2
TO
3 F
OR
SP
I O
PE
RA
TIO
NJU
MP
ER
PIN
S 1
TO
2 F
OR
DC
S E
NA
BL
E
J2 -
JU
MP
ER
PIN
S 2
TO
3 F
OR
SP
I O
PE
RA
TIO
NJU
MP
ER
PIN
S 1
TO
2 F
OR
TW
OS
CO
MP
LE
ME
NT
OU
TP
UT
J21
- I
NS
TA
LL
JU
MP
ER
FO
R S
PI
OP
ER
AT
ION
13
J2
13
J1C
SB
_2
R23
RE
S0
60
3
100K
OH
M
R22
RE
S0
60
3
100K
OH
M
R17
RE
S0
60
3
100K
OH
M
R65
RES0402
10K OHM
C81
0.1U
R24
RE
S0
40
2
10K
OH
M
R21
RE
S0
60
3
1K O
HM
R19
RE
S0
60
3
1K O
HM
R18
RE
S0
40
2
10K
OH
M
R20
RE
S0
60
3
1K O
HM
C13
0.1U
SD
I
SD
O
SC
LK
CS
B
V_D
IG
SD
I
VS
SD
O
V_D
IG
V_D
IG
V_D
IG
SP
I_S
DIO
SP
I_S
CLK
SP
I_C
SB
V_D
IGV_D
IG
V_D
IG
SC
LK
CS
B321
456
NC
7W
Z1
6P
6X
U8
321
456
NC
7W
Z0
7P
6X
U7
Figure 82. Evaluation Board Schematic, SPI Circuitry
AD9627
Rev. B | Page 62 of 76
06571-083
1P
1 2P
2 3P
3 4P
4 5P
5 6P
6
P1
P2
P3
P4
SM
DC
110
F
GND
INP
AD4
OU
T
AC
AD
P33
34
3F
B
GN
D
5
8IN IN
27
1O
UT
OU
T22
SD
6
BIA
S
PS
G
CB
CG CG
CG
6V,
2AM
AX
PO
WE
RIN
PU
T
BN
X-0
16
OP
TIO
NA
LP
OW
ER
SU
PP
LYIN
PU
TS
DR
VD
DS
ET
TIN
G
DR
VD
DR
13
R1
4
3.3
1.8
2.5
140
K
107
K
76.8
K
78.7
K
94.0
K
147
K
GN
DT
ES
TP
OIN
TS
1 3
2 4 5 6
F1
VR
1
21
S2A
_R
ECT
CR
12
21
S2A
_RE
CT
CR
112
1SH
OT
_R
EC
T
CR
8
2 1
S2A_RECT
CR7
1
3
AD
P33
39
VR
3
VS
DR
VD
DIN
C1
03
0.1
U
SJ35
AV
DD
IN
C1
02
10U
C52
10U
VC
P
F2
PW
R_I
N
21
S2
A_R
ECT
CR
10
C42
1U
231
PO
WE
R_J
AC
K
J16
C53
10U
C54
10U
C41
10U
C59
0.1
U
C58
0.1
U
C57
0.1
U
1TP
4
21
10u
hIN
D12
10
L3
1TP25
V_
DIG
DV
DD
DR
VDD
AV
DD
DR
VD
DI N
AV
DD
IN
11
C45
1UC
44
1U
C43
1U
C93
0.00
1U
P4
12
L6
IND
1210
10U
H
1TP
13
1TP
12
1TP
10
1TP
9
21
10uh
IND
1210
L11
21
10uh
IND
1210
L10
21
10u
h
IND
1210 L4
21
10U
HIN
D12
10
L9
P3
R16
RES0603
261 OHM
R13
140 KOHM
R14
78.7 KOHM
Figure 83. Evaluation Board Schematic, Power Supply
AD9627
Rev. B | Page 63 of 76
06571-084
AD
P33
34
FB
GN
D
IN IN2
OU
TO
UT2
SD
GND
INP
AD4
OU
T
GND
INP
AD4
OU
T
GND
INP
AD4
OU
T
Po
we
rS
up
ply
ByP
ass
Ca
pa
cito
rs
1
3A
DP
333
9
VR
6
1
3A
DP
333
9
VR
5
1
3A
DP
333
9
VR
4
SJ36
SJ37C
12
4
10
U
C11
8
10U
C1
19
10
U
C10
8
0.1
U
C1
05
0.1
U
C11
6
0.1
U
C1
07
0.1
U
C1
13
0.1
U
VS
C11
4
0.1
U
C1
15
0.1
U
C1
11
0.1
U
C1
12
0.1
U
C1
10
0.1
U
21
10u
h
IND
121
0
L1
2
AM
PV
DD
C12
9
1U
VC
P
VC
P
VSVS
_OU
T_D
R
3
5
8 71 2
6
VR
2
C1
35
1U
C1
36
1U
C1
32
1U
C13
1
1U
C1
34
1U
C1
33
1U
C1
30
1U
C9
5
0.0
01U
21
10u
h
IND
121
0
L1
3
21
10U
H
IND
121
0
L1
21
10U
H
IND
121
0
L8
PW
R_I
N
PW
R_I
N
PW
R_I
N
PW
R_
IN
R15
78.7 KOHM
R25
140 KOHM
VC
PV
S_
OU
T_
DR
VS
Figure 84. Evaluation Board Schematic, Power Supply (Continued)
AD9627
Rev. B | Page 64 of 76
EVALUATION BOARD LAYOUTS
065
71-0
85
Figure 85. Evaluation Board Layout, Primary Side
AD9627
Rev. B | Page 65 of 76
065
71-0
86
Figure 86. Evaluation Board Layout, Ground Plane
AD9627
Rev. B | Page 66 of 76
065
71-0
87
Figure 87. Evaluation Board Layout, Power Plane
AD9627
Rev. B | Page 67 of 76
065
71-0
88
Figure 88. Evaluation Board Layout, Power Plane
AD9627
Rev. B | Page 68 of 76
065
71-0
89
Figure 89. Evaluation Board Layout, Ground Plane
AD9627
Rev. B | Page 69 of 76
065
71-0
90
Figure 90. Evaluation Board Layout, Secondary Side (Mirrored Image)
AD9627
Rev. B | Page 70 of 76
065
71-0
91
Figure 91. Evaluation Board Layout, Silkscreen, Primary Side
AD9627
Rev. B | Page 71 of 76
065
71-0
92
Figure 92. Evaluation Board Layout, Silkscreen, Secondary Side
AD9627
Rev. B | Page 72 of 76
BILL OF MATERIALS
Table 26. Evaluation Board Bill of Materials (BOM)1, 2
Item Qty Reference Designator Description Package Manufacturer Mfg. Part Number
1 1 AD9627CE_REVB PCB PCB Analog Devices
2 55 C1 to C3, C6, C7, C13, C14, C17, C18, C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, C108, C110 to C116, C145
0.1 μF, 16 V ceramic capacitor, SMT 0402
C0402SM Murata GRM155R71C104KA88D
3 1 C80 18 pF, COG, 50 V, 5% ceramic capacitor, SMT 0402
C0402SM Murata GJM1555C1H180JB01J
4 2 C5, C84 4.7 pF, COG, 50 V, 5% ceramic capacitor, SMT 0402
C0402SM Murata GJM1555C1H4R7CB01J
5 10 C33, C35, C63, C93 to C95, C122, C126, C127, C137
0.001 μF, X7R, 25 V, 10% ceramic capacitor, SMT 0402
C0402SM Murata GRM155R71H102KA01D
6 13 C15, C42 to C45, C129 to C136
1 μF, X5R, 25 V, 10% ceramic capacitor, SMT 0805
C0805 Murata GR4M219R61A105KC01D
7 10 C27, C41, C52 to C54, C62, C102, C118, C119, C124
10 μF, X5R, 10 V, 10% ceramic capacitor, SMT 1206
C1206 Murata GRM31CR61C106KC31L
8 1 CR5 Schottky diode HSMS2822, SOT23 SOT23 Avago Technologies HSMS-2822-BLKG
9 2 CR6, CR9 LED RED, SMT, 0603, SS-type LED0603 Panasonic LNJ208R8ARA
10 4 CR7, CR10 to CR12 50 V, 2 A diode DO_214AA Micro Commercial Components S2A-TP
11 1 CR8 30 V, 3 A diode DO_214AB Micro Commercial Components SK33-TP
12 1 F1 EMI filter FLTHMURATABNX01 Murata BNX016-01
13 1 F2 6.0 V, 3.0 A, trip current resettable fuse
L1206 Tyco Raychem NANOSMDC150F-2
14 2 J1 to J2 3-pin, male, single row, straight header
HDR3 Samtec TWS-1003-08-G-S
15 9 J4 to J9, J18, J19, J21
2-pin, male, straight header HDR2 Samtec TWS-102-08-G-S
16 3 J10 to J12 Interface connector TYCO_HM_ZD Tyco 6469169-1
17 1 J14 8-pin, male, double row, straight header
CNBERG2X4H350LD Samtec TSW-104-08-T-D
18 1 J16 DC power jack connector PWR_JACK1 Cui Stack PJ-002A
19 10 L1, L3, L4, L6, L8 to L13
10 μH, 2 A bead core, 1210 1210 Panasonic EXC-CL3225U1
20 1 P3 6-terminal connector PTMICRO6 Weiland Electric, Inc. Z5.531.3625.0
21 1 P4 4-terminal connector PTMICRO4 Weiland Electric, Inc. Z5.531.3425.0
22 3 R7, R30, R45 57.6 Ω, 0603, 1/10 W, 1% resistor
R0603 NIC Components NRC06F57R6TRF
23 27 R2, R3, R4, R32, R33, R42, R64, R67, R69, R90, R96, R99, R101, R104, R110 to R113, R115, R119, R121, R123, R141 to R145
0 Ω, 1/16 W, 5% resistor R0402SM NIC Components NRC04ZOTRF
24 2 R13, R25 140 kΩ, 0603, 1/10 W, 1% resistor
R0603 NIC Components NRC06F1403TRF
25 2 R14, R15 78.7 kΩ, 0603, 1/10 W, 1% resistor
R0603 NIC Components NRC06F7872TRF
AD9627
Rev. B | Page 73 of 76
Item Qty Reference Designator Description Package Manufacturer Mfg. Part Number
26 1 R16 261 Ω, 0603, 1/10 W, 1% resistor
R0603 NIC Components NRC06F2610TRF
27 3 R17, R22, R23 100 kΩ, 0603, 1/10 W, 1% resistor
R0603 NIC Components NRC06F1003TRF
28 7 R18, R24, R63, R65, R82, R118, R140
10 kΩ, 0402, 1/16 W, 1% resistor
R0402SM NIC Components NRC04F1002TRF
29 3 R19, R20, R21 1 kΩ, 0603, 1/10 W, 1% resistor
R0603 NIC Components NRC06F1001TRF
30 9 R26, R27, R43, R46, R47, R70, R71, R73, R74
33 Ω, 0402, 1/16 W, 5% resistor
R0402SM NIC Components NRC04J330TRF
31 5 R57, R59 to R62 22 Ω, 16-pin, 8-resistor, resistor array
R_742 CTS Corporation 742C163220JPTR
32 1 R58 22 Ω, 8-pin, 4-resistor, resistor array
RES_ARRY CTS Corporation 742C083220JPTR
33 1 R76 200 Ω, 0402, 1/16 W, 1% resistor
R0402SM NIC Components NCR04F2000TRF
34 4 S2, S3, S5 ,S12 SMA, inline, male, coaxial connector
SMA_EDGE Emerson Network Power
142-0701-201
35 1 SJ35 0 Ω, 1/8 W, 1% resistor SLDR_PAD2MUYLAR NIC Components NRC10ZOTRF
36 5 T1 to T5 Balun TRAN6B M/A-COM MABA-007159-000000
37 1 U1 IC, AD9627 LFCSP64-9X9-9E Analog Devices AD9627BCPZ
38 1 U2 Clock distribution, PLL IC LFCSP64-9X9 Analog Devices AD9516-4BCPZ
39 1 U3 Dual inverter IC SC70_6 Fairchild Semiconductor NC7WZ04P6X_NL
40 1 U7 Dual buffer IC, open-drain circuits
SC70_6 Fairchild Semiconductor NC7WZ07P6X_NL
41 1 U8 UHS dual buffer IC SC70_6 Fairchild Semiconductor NC7WZ16P6X_NL
42 3 U15 to U17 16-bit CMOS buffer IC TSOP48_8_1MM Fairchild Semiconductor 74VCX16244MTDX_NL
43 2 VR1, VR2 Adjustable regulator LFCSP8-3X3 Analog Devices ADP3334ACPZ
44 1 VR3 1.8 V high accuracy regulator SOT223-HS Analog Devices ADP3339AKCZ-1.8
45 1 VR4 5.0 V high accuracy regulator SOT223-HS Analog Devices ADP3339AKCZ-5.0
46 2 VR5, VR6 3.3 V high accuracy regulator SOT223-HS Analog Devices ADP3339AKCZ-3.3
47 1 Y1 Oscillator clock, VFAC3 OSC-CTS-CB3 Valpey Fisher VFAC3-BHL
48 2 Z1, Z2 High speed IC, op amp LFCSP16-3X3-PAD Analog Devices AD8352ACPZ
1 This bill of materials is RoHS compliant. 2 The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.
AD9627
Rev. B | Page 74 of 76
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
0.22 MINTOP VIEW
8.75BSC SQ
9.00BSC SQ
164
1617
4948
3233
0.500.400.30
0.50BSC
0.20 REF
12° MAX 0.80 MAX0.65 TYP
1.000.850.80
7.50REF
0.05 MAX0.02 NOM
0.60 MAX0.60MAX
SEATINGPLANE
PIN 1INDICATOR
7.557.50 SQ7.45
PIN 1INDICATOR
0.300.230.18
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
02-2
3-20
10-B
EXPOSED PAD(BOTTOM VIEW)
Figure 93. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-6)
Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9627ABCPZ-150 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9627ABCPZ-125 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9627ABCPZ-105 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9627ABCPZ-80 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9627-150EBZ Evaluation Board AD9627-125EBZ Evaluation Board 1 Z = RoHS Compliant Part.
AD9627
Rev. B | Page 75 of 76
NOTES
AD9627
Rev. B | Page 76 of 76
NOTES
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