12 nm-Gate-Length Ultrathin-Body InGaAs/InAs

MOSFETs with 8.3∙105 ION/IOFF

Cheng-Ying Huang1, Prateek Choudhary1, Sanghoon Lee1, Stephan Kraemer2, Varistha Chobpattana2, Brain Thibeault1, William Mitchell1,

Susanne Stemmer2, Arthur Gossard1,2, and Mark Rodwell1

1Electrical and Computer Engineering, University of California, Santa Barbara

2Materials Department, University of California, Santa Barbara

Device Research Conference 2015Late News

Columbus, OH

III-V FETs at sub-10-nm nodes?• III-V channels: low electron effective mass, high velocity, high

mobility higher Ion at lower VDD reducing switching power• III-V FETs have high leakage current because: Low bandgap larger band-to band tunneling (BTBT) leakage High permittivity worse electrostatics, large subthreshold leakage• Ioff<100 nA/µm (High performance) and Ioff<100 pA/µm (Low power) • Question: Can III-V MOSFETs scale to sub-10-nm nodes?

2

Logic industry

node

Physical gate length

(nm)

16/14 2010 177 145 12

Ref: 2013 ITRS Roadmap

Record high performance III-V FETs

S. Lee et al., VLSI 2014

310 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014 J . Lin, IEDM 2013 T. Kim, IEDM 2013 Intel, IEDM 2009 J . Gu, IEDM 2012 D. Kim, IEDM 2012

I on (

mA

/m

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/m

-0.3-0.2-0.1 0.0 0.1 0.2 0.3 0.4 0.510-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)

Curr

ent D

ensi

ty (m

A/

m)

Gate Bias (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0L

g = 25 nm

SS~ 72 mV/dec.

SS~ 77 mV/dec.

Ion= 500 A/m at Ioff

=100 nA/mand V

D=0.5V

Vertical Spacer

N+ S/D

Lg~25 nm

Record low leakage III-V FETs

4

• Minimum Ioff~ 60 pA/μm at VD=0.5 V for Lg-30 nm• Recessed InP shows 100:1 smaller Ioff compared to InGaAs spacers• BTBT leakage is completely removed sidewall leakage dominates Ioff

Lg-30nm

C. Y. Huang et al., IEDM 2014

Lg-30nm

UCSB Gate Last Process Flow

ZrO2

BarrierSubstrate

N+ S/D

IsolationStrip dummy gate Digital etchDeposit ALD dielectricFGA anneal

Ni

BarrierSubstrate

Lift-off gate metal

Ni

BarrierSubstrate

Ti/Pd/Au

DepositS/D contacts

HSQ

BarrierSubstrate

Pattern dummy gateSource/drain recess etch

Channel

BarrierSubstrate

MBE grown device epilayer

MOCVD source/drain regrowth

5

Ch.

HSQ

BarrierSubstrate

N+ S/D

Ch.Ch.N+ S/D N+ S/D

Ch.

Ch.

TEM images of Lg~12 nm devices

N+InGaAs

InP spacer

InAlAsBarrier

Lg~12nm

~ 8nm

6

tch~ 2.5 nm(1.5/1 nm InGaAs/InAs)

Top View

Ni

Cross-setion

N+InP

ID-VG and ID-VD curves of 12nm Lg FETs

7

0.0 0.2 0.4 0.6 0.80.0

0.2

0.4

0.6

0.8

1.0

gm (m

S/m

)I D (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4V

DS = 0.1 to 0.7 V,

0.2 V increment

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.5

1.0

1.5

I D (m

A/

m)

VDS

(V)

Ron

= 302 Ohm-m

at VGS

= 1.0 V

VGS

= -0.2 V to 1.2 V

0.2 V increment

-0.2 0.0 0.2 0.4 0.6 0.810-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

SS ~ 107.5 mV at V

DS=0.5 V

SS ~ 98.6 mV at V

DS=0.1 V

VDS

= 0.1 to 0.7 V

0.2 V increment

I D, |I G

| (m

A/

m)

VGS

(V)

Ioff~1.3 nA/μm Ion~1.1 mA/μm

Ion/Ioff > 8.3∙105

Lg-12nm

On-state performance

8

• Slightly higher Gm for a 2.5 nm composite channel than a 4.5 nm InGaAs channel larger gate capacitance.

• A 2.5nm InAs channel with a 12 nm InGaAs spacer shows highest Gm high indium content channel is desirable for UTB III-V FETs.

• InP spacers increase parasitic RS/D to ~260 Ω μ∙ m InP spacers need further optimization.

0.00 0.05 0.10 0.15 0.20 0.250

250

500

750

1000

1250

Ron

at zero Lg

~220 Ohm.m ~260 Ohm.m ~262 Ohm.m

On R

esis

tance

(O

hm

-m

)

Gate length (m)

2.5nm InAs+12 nm InGaAs spacer at V

GS=0.7V

4.5nm InGaAs+graded InP spacer at V

GS=1V

This work at VGS

=1V

0.01 0.1 10.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VDS

= 0.5 V

Gate length (m)

2.5nm InAs+12nm InGaAs spacer 4.5nm InGaAs+graded InP spacer This work

Pea

k G

m (m

S/

m)

Subthreshold characteristics

9

• A 2.5nm InAs channel with a 12 nm InGaAs spacer shows the lowest SS and DIBL because of the best electrostatics.

• A 5 nm un-doped InP spacer with the atop 8 nm linearly doping-graded InP have shorter effective gate length as compared to 12 nm un-doped InGaAs spacers worse electrostatics.

• SS~107 mV/dec. and DIBL~260 mV/V for 12 nm devices FinFETs will cure this.

0.01 0.1 160

80

100

120

140

Gate length (m)

Subth

resh

old

Sw

ing (m

V/d

ec)

VDS

=0.1 V, 2.5nm InAs

VDS

=0.5 V, 2.5nm InAs

VDS

=0.1 V, 4.5nm InGaAs

VDS

=0.5 V, 4.5nm InGaAs

VDS

=0.1 V, This work

VDS

=0.5 V, This work

0.01 0.10

100

200

300

400

Vth at 1 A/m

DIB

L (m

V/V

)

Gate length (m)

2.5nm InAs+12nm InGaAs spacer 4.5nm InGaAs+graded InP spacer This work

Ion and Ioff versus Lg

10

0 20 40 60 80 100 1200

100

200

300

400

500

600

700 2.5nm InAs+12nm InGaAs spacer 4.5nm InGaAs+graded InP spacer This work

I on (A

/m

)

Gate length (nm)

VDS

= 0.5 V

Ioff

= 100 nA/m

10 100 100010-3

10-2

10-1

100

101

102

103

2.5nm InAs+12nm InGaAs spacer 4.5nm InGaAs+graded InP spacer This work

I OFF, M

IN (nA

/m

)Gate length (nm)

VDS

= 0.5 V

• High In% content channels are required to improve Ion, but Ioff is relatively large (~10 nA/µm).

• InGaAs channels with recessed InP source/drain spacers are required for low leakage FETs.

• A clear tradeoff between on-off performance.

-0.2 0.0 0.2 0.4 0.60.0

0.5

1.0

1.5

2.0

2.5

Cox

= 4.2 F/cm2

EOT= 0.8 nm

W/L= 25m/21 m

Freq: 200kHz

2.5 nm InAs 5.0 nm InAs

Ga

te C

ap

ac

ita

nc

e (F

/cm

2 )

Gate Bias (V)

0

1

2

3

4

5

6

7

x 10

12

Car

rier

Den

sity

(/c

m2 )

Mobility extraction at Lg-25 µm long channel FETs

0.0 0.2 0.4 0.6 0.8 1.00.0

0.5

1.0

1.5

2.0

2.5

3.0

Carrier d

ensity (10

12 cm-2)

Cac

c (

F/c

m2 )

VGS

(V)

0

2

4

6

8

10V

DS = 0.1 to 0.7 V

0.2 V increment

0 1 2 3 4 5 60

100

200

300

400

500

Mobility

(cm

2 /Vs

)

Carrier density (cm-2)

VDS

= 25 mV to 50 mV

Mobility~ 250 cm2/V s∙

Mobility~ 280 cm2/V s∙

Freq: 200 kHzEOT~ 0.9~1 nm

This work InAs channel

1.5/1 nm InGaAs/InAs

1.5/1 nm InGaAs/InAs

m*, RS/D more important! 11

0 1 2 3 4 5 6 70

200

400

600

800

1000

1200

x 1012

eff (c

m2 /s-

V)

Carrier Density (/cm2)

2.5 nm InAs 5.0 nm InAs

Summary

12

• We demonstrated a 12nm-Lg ultrathin body III-V MOSFET with well-balanced on-off performance. (Ion/Ioff> 8.3·105)

• The 12nm-Lg FET shows Gm~1.8 mS/µm and SS~107 mS/dec., and minimum Ioff~ 1.3 nA/µm.

• High indium content channel is required to improve on-state current. (High performance logic)

• Thin channels, InGaAs channels, and recessed InP source/drain spacers are the key design features for very low leakage III-V MOSFETs. (Low Power Logic)

• III-V MOSFETs are scalable to sub-10-nm technology nodes.

cyhuang@ece.ucsb.edu

Thanks for your attention!Questions?

• This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.009) and GLOBALFOUNDRIES(Task 2540.001).

• A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network.

• This work was partially supported by the MRSEC Program of the National Science Foundation under Award No. DMR 1121053.

Acknowledgment

(backup slides follow)

Record low subthreshold swing

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

eak

age|

(A

/cm

2)

Cu

rren

t D

ens

ity

(mA

/m

)

Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse SweepSolid: Forward SweepL

g = 1 m

15

Achieved SS~ 61 mV/dec.Superior high-k dielectrics on III-V channels.

Dielectrics from Gift Chobpattana, Stemmer group, UCSB.

S. Lee et al., VLSI 2014

Why InAs channel is better…

• Electron scattering with oxide traps inside conduction band• Electrons in high In% content channel have less scattering with

oxide traps.

J. Robertson et al., J. Appl. Phys. 117, 112806 (2015)J. Robertson, Appl. Phys. Lett 94, 152104 (2009)

N. Taoka et al., Trans. Electron Devices. 13, 456 (2011)N. Taoka et al., IEEE IEDM 2011, 610.

InP spacer thickness: on-state

Thicker InP spacer increases Ron, and degrades Gm

Thinner spacer is desired at source to reduce RS/D. 17

0.02 0.04 0.06 0.08 0.100.0

0.4

0.8

1.2

1.6

2.0 VDS

= 0.5 V

Gate length (m)

5 nm InP spacer13 nm InP spacer

Pea

k g

m (m

S/

m)

0.02 0.04 0.06 0.08 0.100

100

200

300

400

500

600

Ron (

m)

Gate length (m)

5 nm InP spacer, RS/D

~199 m13 nm InP spacer, R

S/D~364 m

0 20 40 60 80-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0InGaAs Channel

N+In

P Spac

er

N+InGaAs Source

Energ

y (eV)

Distance to source contact (nm)

Bar

rier

Fermi level

4.5 nm InGaAs

Ni/AuTi/Pd/Au Ti/Pd/Au

ZrO2

10 nm N+InP

50 nm N+InGaAs 50 nm N+InGaAs

10 nm N+InP

3 nm13 nm U.I.D InP 13 nm U.I.D InP

Ni/Au

10 nm N+InP

Back Barrier

Doping-graded InP spacer

Doping-graded InP spacer reduces parasitic source/drain resistance and improves Gm.

Gate leakage limits Ioff~300 pA/μm.18

-0.2 0.0 0.2 0.4 0.610-910-810-710-610-510-410-310-210-1100101

gm (m

S/m

)

I D, |I G

| (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

|IG|

VDS

= 0.1 to 0.7 V

0.2 V increment

ID

Ron at zero Lg

(Ω∙μm)

5 nm UID InP

13 nmUID InP

Doping graded InP

~199 ~364 ~270

Lg-30 nm, 30Å ZrO2