12.08.2013embedded systemspage 1 c166-core port 5 port 3 cpu dual port ram 2 kbyte interrupt...

04EI

12.08.2013Embedded Systems

164CL

XTAL

C166-CoreC166-Core

Port 5 Port 3

CPU

Dua

l Por

t

RAM

2 KByte

Interrupt Controller

Watchdog

Peripheral Data

External Instr./Data

Instr./Data

USART

ASC

BRG

GPT1

16

16

16

1632

PEC

64 K ROM

(C164 CI-8RM)or

OTP(C164CI-8EM)

Interrupt Bus

Data

Data

Port 8

BRG

SSC

Sync. Channel(SPI)

PLL-Oscillatorprog. Multiplier:

0.5; 1; 1.5; 2;2.5; 3; 4; 5

XB

US

(16-

bit N

ON

MU

X D

ata

/ Add

ress

es)

T2

T4

T3

13 ext. IR

Full-CANInterfaceV2.0Bactive

RTC

10-BitADC

Tim

er 7

Tim

er 8

Port 1

Tim

er 1

3

1 Comp.Channel

3/6 CAPCOMChannels

CAPCOM6 Unit forPWM Generation

8 9 4 16

6

16

Port 4

8-Channels

External Bus8/16 bit

MUX only&

XBUSControl

CAPCOM 2

8-Channel

C164CI Block Diagram

P4.6/ CAN TxD

P4.5/ CANRxD

Port

0

04EI


On-Chip(EP)ROM

SP

STK OV

STK UV

CPU – Block Diagram

CPUCPU

MDL

MDH

Barrel-Shifter

ALU

16-bit

Mul./Div.-HW

Bit-Mask Gen.

Code Seg.Ptr

On-ChipStaticRAM

R15

R0

STK OV

STK UV

4-StagePipeline

32

16

16

Exec. Unit

Instr. Ptr.

Instr. Reg.

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Context Ptr.Data Page Pointer

SFR

PSW

General

R15

R0

Purpose

Registers

C:\irber\MC164\Vorlesung\documentation\data sheets_eng\SFRCPUEX_eng.doc

04EI


Fetch

Decode

Execute

Write Back

1. Instr. 2. Instr. 3. Instr. 4. Instr.

Time

1 Machine Cycle = 100 ns at 20 MHz CPU clock

Four stage instruction-pipeline

100ns effective execution time (20 MHz fCPU) Three Pre-Fetch-Steps in word size (Bus Controller) for supporting of the

Pipeline Optimized execution of jumps

–For jump instructions (Jump, Cond. Jump, Call, Return,...) usually only one additional machine cycle is necessary, to fetch the instruction at the destination address

Jump Cache

–For the execution of loops no additional machine cycle is necessary

04EI


Arithmetic Logic Unit

ALU

A B

Z

Cin

op

Cout

flags

Arithmetic Operations:

Logic Operations:

Shift / Rotate:

add subinc decneg

and nandor norexor exnornot

sll srlsla srarol ror

s/ro : shift/rotatel/r : left/rightl/a : logic (unsigned)/arithmetic (signed)

04EI


Barrel Shifter

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

D0

D1

D2

D3

D15

S0 S1 S14

Q0

Q1

Q2

Q3

Q15

04EI


General Purpose Register (GPR)

16 GPRs form a register bankwhich consits of maximize

– 8 Word-Registers and

– 8 Word-Registers with byte access to the least significant and most significant byte

The GPRs are bit-addressable the register banks can be arranged in the internal

RAM in any order The mapping of the active register bank is determined by

the Context Pointer (CP) CP can easily changed to choose an other register bank -

“Switch Context”-instruction.

04EI


0F600

R8R9R10R11R12R13R14R15

RH0RH1RH2RH3RH4RH5RH6RH7

RL0RL1RL2RL3RL4RL5RL6RL7

Context pointer

0FDFE

2KBytesinternal RAM

R6

R0R1R2R3R4R5

R7

STKOV

STKUV

R15

R0

0FC00

Stackpointer UnderflowStackpointer

Stackpointer Overflow

STKUV

STKOV

2 kByte internal RAM – mapping of the register banks and the stack

SP

04EI


Complete address space:– 64 kByte non-segmented address space

– Up to 4 MBytes segmented address spaces:64 kByte Code-Segments and 16 kBytes Data-Pages

– “von Neumann”-Architecture, which is internally equipped with Multi-BUS-Structures to avoid BUS-Bottlenecks

Internal Address Space– 2 KByte RAM

– 64 KBytes Flash/OTP ROM (One Time Programmable ROM)(C164CI-8FM)

Flexible external BUS-Configurations– Up to 22-Bit Address-BUS / 8-Bit Data-BUS (multiplexed)

– Up to 22-Bit Address -BUS / 16- Bit Data-BUS (multiplexed)

– 5 completely independent configuration-registers

– 4 programmable “Chip Selects” and programmable BUS-control signals help to avoid external logic.

Address Space

04EI


Internal and external address mapping of the C164CI

Bit-adressierbarer Bereich

X-Bus Peripheral

Segment 0 contains the internal memory

Internes RAM

512 BytesSFR’s

2kInternes

RAM

ExternerSpeicher

InternesROM /

Flash E²PROM(can be mapped to Segm. 1 )

512 BytesESFR’s

0x000000

0x008000

0x00FE00

0x00FA00

0x00F600

0x00F200

0x0100007 0

32k

0.5k

Reserviert

Up to 4 MBytes

Code Segments Daten Pages

0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

InternalROM/

FLASH2*32k

0x010000

0x020000

0x030000

0x040000

Full -CANFull -CAN0x00F000

0x00E800Reserviert

0.5k

0x000000

04EI


The programming language C for the C164

C166 is the realisation of ANSI-C for the microcontroller-family C166.

The C166-Compiler provides a number of extensions of the ANSI-C Standard. Ispecially such, that directly support the C 166-architecture:

C166-denotation commentary

memory types As completition to the „storage class" to every definition of a variable a „memory type " can be specified. This allows a from the actual „memory model" independent addressing of variables in different address spaces of the 166-systems. Following typs are defined:

near, idata, bdata, sdata, far, huge, xhuge.sfr Is used as declaration of "Special-Function-Register" (SFR)

of the 166-family

sbit Declaration of Bits within SFR's.

bit Data type bit. Return values and passing parameters of functions can be of type bit.

bit-addressable Variables in bit addressable space can be defined as memory type by means of bdata.

04EI


The programming language C for the microcontroller C164

C166-denotation commentary

register bank (using) Each function can contain a declaration, in which the register bank to be used can be set.

interrupt Functions can declared als Interrupt-Service-Routines by indication of the interrupt names respectively – vectors.

register mask The C166-Compiler generates for each C-function a register-mask, in which the registers used by the function are listed. Those can be used as funktion prototype, due to optimize the usage of the registers.

RTX166 tasks By the keyword _task_ the functions is specified as a task of the operating system RTX166.

New Keywords (summarisation):Memory types: near, idata, bdata, sdata, far, huge, xhugeData types: bit, sfr, sbitFunctions: interrupt, _task_, using

04EI


Memory Types

Type Address space

near 16-Bit addresses up to 64 kBytes

idata On-chip RAM (fastest access)

bdata Bit-addressable On-chip-RAM

sdata System Page (0xC000-0xFFFF) inclusive SFR‘s

far 32-Bit Pointer with 16-Bit address calculation, the size of the object is 16 kByte.

huge 32-Bit Pointer with 16-Bit, address calculation, the size of the object is 32 kByte.

xhuge 32-Bit Pointer with 32-Bit address calculation, the size of the object is 16 MByte.


04EI


According to the memory types memory models can be predeterminded as presettings, which always will be used, when no memory type is explicitly specified by the variable – or function

This is done by the preprocessor directive: # pragma storage model


Storage model Variable functions Segmentation Code size

TINY near near no 64kSMALL near near yes 64kCOMPACT far near yes 64kHCOMPACT huge near yes 64kMEDIUM near far yes unlimitedLARGE far far yes unlimitedHLARGE huge far yes unlimited

04EI


Data types: : size of memory and range of values

Datentyp size of memory range of values

bit # 1 Bit 0 or 1

signed char 1 Byte -128 to +127

unsigned char 1 Byte 0 to 255

signed int 2 Bytes -32768 to + 32767

unsigned int 2 Bytes 0 to 65535

signed long 4 Bytes -2147483648 to +2147483642

unsigned long 4 Bytes 0 to 4294967295

float 4 Bytes 1.176E-38 to 3.40E+38

double 8 Bytes 1.7E-308 to 1.7E+308

pointer 2/4 Bytes Address of the object


Datatypes for the access to Special Function Registers (SFR)

sbit # 1 Bit 0 or 1

sfr # 2 Bytes 0 to 65535

# special data types in C166, which are not defined in ANSI-C.

04EI


Integrated Development Environment

C-Library

ANSI CCompiler

Macro-Assembler

– Debugger– Simulator

Emulator &

PROM Programmer

RTX TinyReal TimeOperatingSystem

– µVision2Editor / Project Management

Library

Manager

Linker / Locater

CPU &Simulator

Monitor

Target DebuggingPeripheral

Start of lab practical

C:\irber\MC164\Vorlesung\documentation\power point_eng\prakt\pract_ec1a.ppt

04EI


Code-addressing using segmentationin the 4 MByte address space

Code Segment Pointer (CSP) for Code-Addressing

22-Bit physical Code-Addresse (C164)

6-Bit Segment-number

16-Bit

0131416-Bit Instr. Pointer

15 780131415Code Seg. Pointer7 6 58

The Instruction Pointer (IP) is incremented after each instruction fetch phase

The Code Segment Pointer (CSP) is only changed by absolute jumps, respectively indirect y in case of the return from a subroutine by the stack

04EI


Addressing of data by paging within the 4 MByte Address space

Data addressing via the Data Page Pointer (DPP)

14-bit

013 16-bit Adresse1415

Selection of aData Page Pointer

10-bitPage-number

DPP3DPP2DPP1

DPP0

Physical 24-Bit Data-Address

(up to 22 external available for C164)

SFR

C:\irber\MC164\Vorlesung\documentation_ss12\data sheets_eng\SFRCPUEX_eng.doc

04EI


External Bus Controller

Allows variable timing of CPU-controlling signals by software Realizes up to 4 Chip-Select-Signals Selection of 4 address ranges possible

Special Function Register BUSCON0..4Programmable timingsDeterminition of CS# - signalsSelection of the bandwith of the Data-BUS 8 / 16 Bit

Special Function Register ADDRSEL1..4Programmable ranges of the address space for the access to external components with the properties of the assigned BUSCONx- registers.

04EI


Multiplexed Address- and Data-BUS

Address

Address

Address

Data

Data

A16..A21

ALE

CS#

A0..A15D0..D15 (7)

RD#

A0..15D0..15 (7)

WR#

Extension of the Address-Setups

Memory-Access Time

Tri-State - Time

WR-Delay

RD-Delay

SFR

C:\irber\MC164\Vorlesung\documentation\data sheets_eng\SFRCPUEX_eng.doc

04EI


Integrated Chip Select - Signals

The base address is always a multiple of the address space.(i.e. the Chip Select with an adress range of 128kByte starts at a 128kByte boundary)

A21A20A19

CS3#CS2#CS1#

CBA

G

CS11CS10

CS9CS8CS7CS6CS5CS4

74ACT138

C164 0xB800000xB000000xA800000xA000000x9800000x9000000x8800000x800000

Extra Memory-MappedChip-Selects

P3.9P3.8P3.6

CS3#CS2#CS1#

CBA

G

CS11CS10

CS9CS8CS7CS6CS5CS4

74ACT138

C164 0xF000000xE000000xD000000xC000000xB000000xA000000x9000000x800000

Extra IO-MappedChip-Selects

All with equal Bus-Mode, Waitstates, et al.

CS0# P6.0 BUSCON0CS1# P6.1 BUSCON1 ADDRSEL1CS2# P6.2 BUSCON2 ADDRSEL2CS3# P6.3 BUSCON3 ADDRSEL3

Active for those address space, which is not covered by CS1#..CS3#

04EI


Connection of external memory chips with 8 Bit - organisation

C164[20 MHz] W

E#

WE

#O

E#

OE

#O

E#

OE

#

CS

#

CS

#C

E#

CE

#D

0-7

D0

-7D

0-7

D0

-7A

0-1

6

A0

-16

A0

-18

A0

-18

MT5LC128K8D4 MT5LC128K8D4

AM27C040 AM27C040

RAMRAM

ROM ROM

MT5LC128K8D4Fa. Micron SRAM 128k x 8access time 25 ns

ADDRSEL1 = 0x0406BUSCON1 = 0x04CF

AM27C040Fa. AMD Eprom 512k x 8access time 120 ns

BUSCON0 = 0x04CEA1-15

15-Bit D-Latch

EN

WRL#WRH#

RD#

D0-15

A16-19

CS1#CS0#

ALE

04EI


BH

E#

OE

#O

E#

CS

#C

E#

D0

-15

D0

-15

A0

-15

A0

-16

IDT71016

M27C202

RAM

ROM

IDT71016Co. IDT (Integrated Device Technology)SRAM 64k x 16Access time 20 ns

ADDRSEL1 = 0x0405BUSCON1 = 0x04CF

M27C202Co. ST MicroelectronicsST Eprom 128k x 16Access time 100 ns

BUSCON0 = 0x04CE

BL

E#

WE

#

C164[20 MHz]

A1-15

16-Bit D-Latch

EN

WR#

BHE#RD#

D0-15

A16-17

CS1#CS0#

ALE

A0

Connection of external memory chipswith 16 Bit- organisation

04EI


Overlapping Address Ranges

XBCON0

BUSCON2 BUSCON4

BUSCON1 BUSCON3

BUSCON0

0x000000

0xFF

FF

FF

Inactive range

Active rangeHighest Priority

Overlapping not allowed

04EI


Interrupt System

Interrupt Controller

– Short interrupt-reaction times:Min. 250ns, typical 400ns (@20 MHz)

– Low overhead for ISR’s

– Powerful priorisationin 15 priority levels, each in 4 groups

– Hardware Traps detects run time error

– Software Traps

Peripheral Events Controller (PEC)

– Releases the CPU from simple and frequently arising ISR’s

– Interrupt controlled “DMA-simular” data transfer with CPU-participation

– Reaction times: Min. 150ns, typical 300ns with a CPU-load of 100ns (@20 MHz)

04EI


3 2 1 0151413121110

9876543210

Group

L e

v e

l

1

64

Level 15 group 1group 0

group 2group 3

Level 14group 1

group 0

group 2group 3

PEC 0

PEC 6 PEC 5PEC 4

PEC 3PEC 2 PEC 1

PEC 7

Level 1-13group 1

group 0

group 2group 3

(Level 0) group 1group 0

group 2group 3

Interrupts und PEC - Priorisation

04EI


Interrupt Processing

INTR Flag is set

Periph. Interrupt

External Interrupt*

External Interrupt*

Priority-Check

Comparision of theinterrupt priority with the run-time-priority

of the CPU

16 Priority-Levels

ifhigher

priority

Interrupt Control Register of the triggering peripheral-elementsINTR Service:

Rescuing:PSW, CSP, IP

New CPU-Prio. in PSW.

CSP and IP fromperipherie-vector or trap-number

PECService

* External Interrupts are possible e.g. instead of the “Capture” Inputs

13 ext. Interrupts (+ NMI) including 4 “fast” interrupts32 Peripheral Interrupts

4 Groups

Group Check

ClearINTR Flag

Periph. Interrupt

Periph. Interrupt

Periph. Interrupt

DaveSFRI-Vektor-Tabelle µV-v1_isrDave v1_isr

C:\Programme\DAvE\dave.exe C:\irber\MC164\kristl\c164prj\vorl\v1_isr\vorl1.dav

C:\irber\MC164\Vorlesung\documentation\data sheets_eng\SFRintr_eng.doc

C:\irber\MC164\Vorlesung\documentation\data sheets_eng\IntTable_eng.doc

C:\irber\MC164\kristl\c164prj\vorl\v1_isr\vorl1.uvproj

C:\Programme\DAvE\dave.exe C:\irber\MC164\kristl\c164prj\vorl\v1_isr\vorl1.dav

04EI


Interrupt has passed priority- and group-check

Interrupt Priority < 14 Interrupt Priority 14 or 15and Data Counter > 0Interrupt Priority 14 or 15and Data Counter > 0

Interrupt Service PEC Service

8 PECChannels

Data Counter

SRC Pointer

DEST Pointer

Contr. Reg.

Memory Segment 0

0xFFFF

0x0000

Byte bzw.WordTransfer

INTR Service:

Rescuing:PSW, CSP, IP

New CPU-Prio. in PSW.

CSP and IP fromperipheral-vector or Trap-Number

Interrupt if Data Counter = 0

Prioritäts- & GroupCheck

Peripheral Events Controller (PEC)

Peripheral Events Contoller

SFR Demo v1a_isr_pec

C:\irber\MC164\Vorlesung\documentation\data sheets_eng\SFRintr_eng.doc

12.08.2013embedded systemspage 1 c166-core port 5 port 3 cpu dual port ram 2 kbyte interrupt...

Documents

embedded systemspage

address bus

databus multiplexed5

databus multiplexedup

necessaryembedded systems12

sfrpswembedded systems12

stackspembedded systems12

register banks