12.2 Silicon Solar Cells

Executive Summary

Salient Features:1. Mask design and fabrication for investigation of TLM structures for contact optimization

completed. 2. Multi layer passivation/ARC layers for front side passivation of p-Si wafer based solar

cells investigated. 3. Al2O3 deposited by pulsed-DC sputtering developed with surface recombination velocity

of 42 cm/s.4. Boron rich layer formed due to boron diffusion process is seen to improve passivation of

Si surface. 5. Selective emitter process using an etch back after diffusion is demonstrated. 6. Emitter formation by laser anneal as a test case for 3D junctions is developed and cells

fabricated. 7. Design of a system for contact formation using a temperature sensitive paste is

completed. 8. Solar cell process with Ni/Cu contacts for front side contact demonstrated. 9. Surface damage resulting from Wire EDM slicing of Si ingots is studied and reported.

Publications and presentations:1. Sandeep S. S., Ketan Warikoo, Anil Kottantharayil, “Optimization of ICP-CVD Silicon

Nitride for Si Solar Cell Passivation”, presented at the IEEE PVSC Conference, Austin, USA, 3-9 June 2012.

2. Karthick Murukesan, D.V. Sridhara Rao, Muraleedharan K., Ashok Kumar Kapoor, Anuradha Dhaul, Brajesh Singh Yadav, Brij Mohan Arora, “An Investigation of Silicon Boride Surface Layer Resulting from Boron Diffusion in Silicon”, presented at the IEEE PVSC Conference, Austin, USA, 3-9 June 2012.

3. Karthick Murukesan, Narasimha Rao Mavilla, Brij Mohan Arora, “Towards Fabrication of Low-Cost High-Efficiency c-Si Solar Cell: Progress and Optimization Using TCAD Simulation Study”, presented at the IEEE PVSC Conference, Austin, USA, 3-9 June 2012.

4. Dongre Ganesh, R.K. Singh, Suhas S. Joshi, "Response Surface Analysis of Slicing ofSilicon Ingots with Focus on Photovoltaic Application," Accepted for publication inJournal of Machining Science and Technology (Taylor and Francis publisher).

Patents: None.

Other: Karthick Murukesan, a research assistant employed in the project was sent on an internship atSolar Energy Resarch Institute Singapore (SERIS). Karthick has carried out research work oncrystalline silicon solar cell processes and it is hoped that this exposure would help him contribute better to the NCPRE.

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12.2.1. High Efficiency Crystalline Solar CellsMonocrystalline silicon solar cells on p-type substrates (Kalaivani S., Ketan Warikoo, Sandeep S. S.):

During the last quarter we had reported a cell performance of 14.9% efficiency, where the fillfactor was only 64% whereas the VOC = 590 mV, JSC = 39.5 mA/cm2. Series resistance wasidentified as the key issue. During this quarter we have focussed on reducing the contactresistance. For this purpose transmission line measurement (TLM) structures were designed.A new set of masks were designed and written with these structures as shown in Fig. 12.1.Wafers are currently being processed to optimize front side contacts.

d1 = 1 mmd2 = 1.5 mmd3 = 3 mmd4 = 6 mmd5 = 12 mm

Fig. 12.1: Designed TLM structures and the mask. The TLM structures are placed along with solarcells of various dimentions so that cell performance and resistance measurements can beassessed on the same wafers.

Optimization of SiNx for ARC: (Sandeep S. S.)

Novel dielectric stacks based on silicon dioxide and silicon nitride are being investigated asan alternative for single layer nitride based stacks to attain better thermal stability and higherpassivation quality. In order to study the interface properties, MOS capacitors with Al as frontand back contact was fabricated on 1-5 ohm-cm p-type <100> wafers.

Fig 12.2: C-V data for the bi layer silicon nitride.film.

Fig 12.3: C-V data for oxide based passivationlayer.

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Al2O3 deposited by reactive sputtering for surface passivation (Meenakshi Bhaisare)

Objective: Effect of post deposition annealing conditions on pulsed- DC reactive sputteredAl2O3 dielectric for surface passivation of p-type silicon surface for c-Si solar cellapplications. Results & Discussions: The fixed oxide charges and interface state densities were extractedfrom high - frequency capacitance versus voltage (HFCV) measurements done on MOScapacitors. The life-time measurements were done and surface recombination velocity wascalculated for all these films deposited on 1 Ω-cm p-type (FZ) wafers for various PDAconditions.

The HFCV measurements were done on MOS capacitor structures for the AlOx filmsdeposited at 1000 W with Ar:O2 flow of 15:55 sccm for 300 sec and Aluminum is thermallyevaporated as top gate material using shadow mask. Fig. 12.3 (a) shows the high frequencyC-V curve measured at 100 kHz and Fig. 12.3 (b) shows the corresponding values of negativefixed oxide charges (Qox) and density of interface states (Dit) extracted from the measurement.

Fig. 12.3: High frequency C-V plot measured at 100 kHz and (b) Qox versus Dit values extracted fromHFCV measurement for different PDA conditions.

The effective minority carrier life-time for different PDA conditions are shown in Fig. 12.4(a) and effective surface recombination velocity is shown in Fig. 12.4 (b). The surfacerecombination velocity was calculated using the following formula:

bulkeffeff

WS

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Here W is the wafer thickness, which is 300 nm and τbulk = 546.3μs was measured on 1 Ω-cmp-type c-Si (FZ) wafer with a surface passivation provided by iodine-methanol solution inthis work.

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Fig. 12.4: (a) Effective minority carrier life-time (τeff) measured data and (b) Effective surfacerecombination velocity (Seff) for different PDA conditions.

The HFCV curve shows a positive shift in flat band voltage (VFB) for all annealed samplesand the high Qox values (6 × 1012 cm-2) are obtained for these samples with the low values ofDit (4 × 1011 eV-1cm-2). The film thickness was 26 nm with RI ~1.6 was measured byspectroscopic ellipsometry (SE). It is observed that the lowest Seff ~ 42 cm/sec is obtained forfilms annealed in O2+ N2 gas ambient and only N2 gas ambient at 520 oC.

Monocrystalline silicon solar cells on n-type substrates (Bandana Singha)

Detailed progress report: Study of boron rich layer (BRL) - its properties and characterizationOne interesting phenomenon seen after deglazing of boron diffused samples is boron richlayer (BRL) which, in general, cannot be removed completely by any chemical treatment.Due to this the emitter behaves as a dead layer. But the interesting property which is seen inthis experiment is, the minority carrier lifetime value increases in presence of BRL.The values of minority carrier lifetime (taking average of different measurements) measuredat different stages are listed below in the Table 1.

Table 1: Minority carrier lifetime measured at different steps of B- diffused emitter formation.

StepsBeforeRCA

cleaning

After RCAcleaning

With BRL (whichremains at the surface

after deglazing)

Removal/ loweringof BRL by HNA

solution

Minority carrierlifetime (μsec)

5 32 124 11

The increase in minority carrier lifetime value was observed in all the samples which hadBRL at the surface (in 3rd column in Table 1). The lifetime value degrades after HNA solutiontreatment which is generally used to remove/lower the concentration of BRL. So, from thechange in minority carrier lifetime value it can be said that BRL shows gettering effect.

Selective Emitter Solar Cells (Karthick Murukesan):

Fabrication steps Rear side BSF by solid source B diffusion at 940 0C for 20 min

Front emitter by the solid source P diffusion (R = 30 Ω/)

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RIE Etch time optimization

etch rate = 35- 40 nm/min

Removal of dead layer by etching.

RIE to define active area (Selective emitter formation, R=90 Ω/).

Oxidation to cure any surface damage by RIE.

2 stack SiO2 (10 nm) / SiN (60 nm) ARC

Fig. 12.5: Optimization of the etch rate of theheavily doped emitter.

Fig. 12.6: Illuminated IV of the cell fabricatedusing the selectrive emitter process.

The 5 mm x 5 mm device fabricated by the above procedure was an improvement on ourprevious device, which had efficiency of 11.2 %. However, both Voc and Isc need to beimproved further.

HIT solar cells (Sanchit Khatavkar):

In the last report, we had presented results on half-HIT structure fabricated with improved p+a-Si:H layer, but found the illuminated I-V characteristics continued to be anomalous. Wedecided to investigate the various process steps. TEM of the fabricated structures shows theintrisic a-Si:H layer and the p+ a-Si:H layers of thickness in the range 5-10 nm, which isacceptable. The other question we addressed: whether there are variations in the electrical/optical properties of the layers on varying the thickness. This work is still in progress. Wehave made significant progress in analysing the optical characteristics by using the new UV-Visible-IR spectrophotometer. In the thin film structures, transmission (T) and reflection (R)spectra are modulated by interference effects. Determination of band gap can have errorsbecause of these modulations. Accurate values of measured T and R allow minimising theeffect of intereference modulations.

12.2.2. 3D Junctions (Student: Som Mondal)

Salient features:

Fabrication of an emitter-wrap-through solar cell with diffused bulk channels using the laserassisted diffusion technology. The salient feature of this work is to investigate the laserassisted diffusion of Phosphorous in p-type silicon using 1070 nm long wavelength laser.

Detailed progress report:

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The laser irradiation, when absorbed in silicon, can raise the temperature to very high valuereaching melting point or above. At such temperature, diffusion coefficient can get enhancedby several orders of magnitude. This is being experimented with the laser available at theNCPRE and it is found that it is possible to diffuse P into Si using Laser Assisted Diffusion(LAD) in very short time.

The parameters those affect the temperature rise in the substrate are laser power (PL), pulserepetition rate or frequency (fL), duty ratio (DL) and scan speed. Apart from them surfacecondition of the material is also an important factor that needs to be taken care of.

Initial experiments have been carried out to find out a certain set of the above parameters forwhich the substrate reaches melting point so that diffusion can occur in very short time. It isobserved that under the following conditions, the surface melted and re-crystallized but didnot get ablated.

Condition 1: PL= 7.5 W; fL = 97 kHz; DL = 28%; Scan speed = 70 unit/sCondition 2: PL= 7.5 W; fL = 67 kHz; DL = 25%; Scan speed = 40 unit/s

However among these parameters, sample is highly sensitive to fL and DL. It means that if DL

changes by 1% or fL changes by 1 kHz, the morphology of the irradiated samples wouldchange substantially, as seen under optical microscope. A lower fL like 95 kHz for condition1 and 65 kHz for condition 2 or a higher DL like 30% for condition 1 and 27% for condition 2would ablate surface of the sample. Hence it was decided to use these conditions for diffusionexperiments. Fig. 12.7 describes the surface morphology after LAD with condition 2 whileFig. 12.8 describe the surface ablation under DL = 28%.

Fig. 12.7: Surface morphology after LAD withcondition 2.

Fig. 12.8: Surface ablation with DL = 28%.

The samples were prepared using P-Spin-on-dopant (Filmtronics Inc. USA) as source on p-type silicon. Two types of p-type substrates are used - 4-7 ohm-cm, <100> oriented and 250µm thick and 0.01 - 0.02 ohm-cm. The SOD was spun coated at 3000 rpm and subsequentlybaked at 250 oC for 15 min in an open air hot-plate. It thus forms a film of dopant rich layeron silicon. Then the sample was irradiated with the condition mentioned earlier. 15 mm X 15mm is the area of each sample (4 samples could be made on each 2" wafer). The sheetresistance was measured on different locations within each sample with a 4 probe station. It isobserved that for most of the samples made on 4 - 7 ohm-cm substrate the sheet resistance isquite uniform over different locations of the sample and the average sheet resistance is samefor most of the samples. However this is not observed for samples made on 0.01 - 0.02 ohm-cm substrate. The average sheet resistance values are shown in Table 2. The minimum valueof sheet resistance measured is 2.2 ohm/sq. The laser being of 1070 nm wavelength, theabsorption occurs throughout the bulk of the substrate and hence, high junction depth and

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high surface concentration of dopants are assumed to be the reason for such low sheetresistance.

Table 2: Sheet resistance of different samples

Wafer resistivity (Ω-cm) Avg. sheet resistance (Ω/sq.) No of samples

4 - 7 6.4 6

0.01 – 0.02 14.5 6

The junction depths were measured using 4 point probe (4PP) method. In this method thesample sheet resistance is measured after removal of a thin of sample in1: 100-HF:HNO3solution. The sample is dried and again same procedure is followed. The sheet resistanceincreases slowly first and then rapidly. After a certain step the sheet resistance drops to a lowvalue which is almost same as of the p-type substrate's sheet resistance. Three samples inwhich the LAD was done under different line to line spacing and operating conditions on0.01-0.02 ohm-cm substrate were used to measure the junction depth. The junction depthsobtained are 2.1 µm, 4.4 µm and 5.7 µm. However these results need confirmation.

Metallization was done on two samples in which junction was fabricated using condition 1mentioned earlier and on 4 - 7 ohm-cm substrate. Approximately 150 nm Al was thermallyevaporated on the backside of both the samples. The front contacts were made using Agsputtering and Ni/Cu bath deposition and subsequent annealing. The contacts were made tojust check if they show any photovoltaic activity. Hence contact pattern and depositionconditions were not optimized. Table 3 describes the illuminated I-V characteristics results.The I-V characteristics are shown in Fig. 12.9. The conclusion is that the sample showsphotovoltaic properties which means the junction fabrication using the laser is successful.However the Fill Factors are very low which can be improved by proper contact patterns andannealing condition. Lifetime measurements are also done before and after LAD. Howeverno significant conclusion could be drawn as results were highly fluctuating with a trend ofsmall increase after LAD, which may be speculated to come from impurity gettering. Hencefurther investigation is required.

Table 3: I-V data of Ag sputtered and Ni/Cu plated samples.

Contacts Voc (mV) Jsc (mA/cm2) FF (%) Eff (%)

Ag 347 25.7 47 1.7

Ni/Cu 535 27 57 3.7

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Fig. 12.9: I-V characteristics Ag sputtered and Ni/Cu plated samples.

12.2.3. Novel technology for contact formation using temperature sensitive paste (Sastry)

Salient feature:

Patterning prior to the metallization of c-Si solar cells in industry is the objective.

Detailed progress report:

Photovoltaic solar cell uses solar radiation and converts it into electricity. Even though theconverting efficiencies are reached to 25% for a crystalline silicon solar cell, thecommercially available cells have efficiencies of 17%. Hence, there is a huge gap betweenthe commercial and laboratory scale production.

Patterning (Pre-metallization) of the solar cells at front side is an alternative method to thecommercially available screen printing technique in order to achieve better features of finger-grid at front side (finger width < 100µm). Patterning of half – finished solar cells are done byusing a mechanical structure.

Using EDM (Electro Discharge Machines) wires also patterning can be done. This methoduses very thin (30 µm) Tungsten wire to pattern. From previous experiments it is evident thatby using this method the finger width could be as low as 78 µm. The experiments wereperformed for single finger to ensure continuity of etching and uniformity.

Patterning by EDM Wire:

For a single finger, it was observed that the minimum finger width using a 30 µm wire couldbe 78 µm. This method could be expanded for complete patterning of a solar cell with size 4X 4 cm2. Before that,

1. To eliminate the manual patterning while experimentation, mechanical design issuggested.

2. Best suitable metallization (for example Ni/Cu two step metallization at front)

1. Design for the patterning of solar cell

Etching paste

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Fig. 12.10: Design for patterning of solar cell.

To ensure the continuity and fine patterning, a mechanical device as shown in Fig. 12.10, isproposed for patterning of solar cell. It is proposed with acrylic sheets. Wheels with gearingmechanism are made and are kept inside a container with etching paste. Paste is in contactwith the wire. Wire is taken out from a small slit such that sufficient amount of paste is on thewire and excess paste will be removed.

This wire is taken with some other wheels with gearing mechanism to the end part where inthe solar cell is contacted to the paste applied wire. Depending upon the number of fingers,the grooves are made on the contacting wheel. Solar cell is governed by up and downmechanism. Once the patterning is done, the cell is removed and wire is passed. Usingcontinuous motion of wire, always sufficient amount of paste is applied on the wire and iscontacted with solar cell.

Current status:

Design part is finished and assembling and testing parts are yet to be finished.

Once the assembling complete, the initial experiments are to be done to evaluate the featureslike finger width and continuity.

2. Metallization of solar cells using Ni/Cu electroless deposition

The two step Ni/Cu metallization is done on the samples which were etching by EDM wiremanually.

Current status:

Ni layer height of 0.2 µm on which 10 µm Cu layer plated is observed with the experimentalresults.

The patterned cells by above described design (complete solar cells) could be metalized further.

12.2.4. Ni-Cu Front side Metallization of c-Si solar cells (Vishnu Kant Bajpai)

Salient feature:

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The Ni/Cu front-contact metallization scheme for c-Si solar cells is a low cost and potentiallyuseful for high efficiency solar cells manufacturing.

Detailed Progress report: Nickel deposition process for various process parameters have been repeated and the

deposition is still in the form of spherical drops and higher at the peaks of textured Sisubstrate in spite of using magnetic stirrer to ensure uniform metal ions concentration inthe deposition bath.

To study the growth process of nickel deposition using electroless deposition technique,

the silicon substrate was immersed into the deposition bath (alkaline solution with pH -7.5) for very small periods of time (10s and 30 s) and characterized using scanningelectron microscope (SEM) and atomic force microscopy (AFM).

The nucleation sites created due to surface defects and displacement reactions occurring

at the interface which is purely a surface phenomenon and there is no role of reducingagent. The reducing agent comes into play after creation of nucleation sites and then itcontributes to the growth process. This is observed from both SEM and AFM imaging ofthe samples for small duration depositions.

Using Ni-Cu metallization, front side metallization was done for several c-Si solar cells.

Contact resistance was considerably good but the higher FF couldn’t be achieved and itcame out to be around 50%. This was mainly because of non-optimized contact design,annealing, Ni-seed layer and Cu-electroplating. FF should be more than 75%, so being aninstant target point. There is still performance (FF) improvement potential in solar cellmetallization process using Ni-Cu metallization.

Fig. 12.11: SEM images of electroless nickeldeposition on textured emitter of a solar cell for 4 min (pH ~7.5).

Fig. 12.12: AFM images of nickel deposition for 30 s on textured emitter of a solar cell.

12.2.5 Ni/Cu metallization for front contact

(Mehul Raval)

Salient features:

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Impact of activation and native oxide etch step on background plating in Ni bathcharacterized.

Detailed progress Report: Characterization of Background Plating for varying Nickel bathtemperature for activated samples

Objective:

In continuation of previous quarter work, effect of PdCl2 based sample activation along withnative oxide etch on background plating under nickel plating has been analyzed. QSSPC,Reflectance and Suns-Voc studies after plating and annealing have been performed toascertain its impact on the solar cells.

Experimental Conditions and characterization:

The sample details were same as in the previous report. Native-oxide etch was done in 1%HF for 30 seconds followed by PdCl2 based activation of samples prior to exposure in Ni bathsolution. Since the aim of the experiments was to observe background plating, no patterningof the front side was performed. To check the impact of background plating on the actual cellperformance, cells were also patterned and plated with the ARC exposed to Ni.

An optimized Ni bath with temperatures 90°C and pH 5.2 were used to check the influenceof different degrees of bath activity. Samples were exposed to the plating solution for 30seconds and then annealed at 400°C for 30 seconds. A fresh bath was taken for each set ofexperiments at different temperatures.

In addition to lifetime and front surface reflectance studies, Suns-Voc measurements weredone to check the impact on cell parameters like Voc and Vmp.

Results and Discussions:

Fig. 12.13 and Fig. 12.14 represent the front surface reflectance data for samples treated withactivation only and activation along with native oxide etch respectively. Though the increasein reflection was not large after activation, inclusion of exposure to 1%HF did result in asubstantial increase in the reflectance. The corresponding changes in optical constant valuefor the QSSPC life time measurements were also calculated. After incorporating the opticalconstant value changes in the life time data, the change in the life time for the two cases areshown in Table 4 and 5. It can be observed that the decrease in lifetime was large in bothcases, though was more pronounced for the later case. The results indicate changes in theARC properties due to activation and treatment in 1% HF, which lead to visible etching ofSiNx and unwanted Ni deposition.

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Fig. 12. 13: Reflectance data for cells exposed to Ni bath- Temperature = 90°C, pH = 5.2 and treated with activation solution.

Fig. 11.14: Reflectance data for cells exposed to Ni bath-Temperature = 90°C,pH = 5.2, native oxide etch and activation.

Table 4. Variation in Life Time for bath temperature of 90°C with activation.

Cell Processing %change in Lifetime afterplating(sec) @ 1014cm-3

for IR illumination

%change in Lifetime afterplating(sec) @ 1014cm-3

for UV illuminationNo processing 0 0Exposed to Ni bath -36 -36.4Annealed post exposure -26.8 -29

Table 5. Variation in Life Time for bath temperature of 90°C with native oxide etch and activation.

Cell Processing %change in Lifetime afterplating(sec) @ 1014cm-3

for IR illumination

%change in Lifetime afterplating(sec) @ 1014cm-3 forUV illumination

No processing 0 0Exposed to Ni bath -47.9 -58.5Annealed post exposure -46.1 -56.1

Life time data for UV illumination in Table 5 indicate more decrease in the lifetime ascompared to IR illumination, which indicates that changes related to surface modification arecaptured better due to lower penetration depth of UV light.

Results for the Suns-Voc study are shown in Table 6. It can be observed that there is asubstantial decrease in Vmp and Voc@0.1, though the decrease in FF is not much. The dataindicates change in the passivation quality of the SiNx due to background plating.

Table 6. Changes in Suns-Voc data for bath temperature of 90°C with native oxide etch and activation.

Cell Processing %change inVoc

%change inVmp

% change inVoc @0.1 sun

% change inFF

Exposed to Nibath

-13.4 -17.8 -21.8 -2.2

Annealed post exposure

-9.6 -11.4 -14.4 -1.4

12.2.6 Slicing of silicon wafers for PV applications using Wire Electric Discharge Machining (We-EDM) (Dongre G.G., Ashwin P.)

Salient features: Wire- Electro-Discharge Machining (EDM) used extensively primarily in automobile, tool,die, and mould making industries. Experimental analysis demonstrate that wire-EDM canalso be used effectively for silicon ingot slicing. As, existing silicon ingot slicing processes

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like inner diameter (ID) saw and abrasive wire cutting have drawbacks of high kerf loss,lower finish and limitation on the thickness of wafer. However, the surfaces generated bywire-EDM process must be free from subsurface damage and wire material contamination.This study gives an overview of the characterization of wafer surfaces sliced by wire-EDMprocess.

Detailed progress report: This report is based on the experimental work on silicon ingotslicing by wire-EDM process and wafer surface characterization.

1. Analysis for depth of thermal damage

Due to localized heating and rapid cooling of wafer surfaces during sparking in wire-EDMprocess, a multi layered surface is created. It consists of three layers namely: recast or whitelayer being the top most, it is followed by heat affected zone (HAZ), and a transformed layer,where a changed grain structure appears.

In the case of silicon wafers used for PV cells, the damaged layer must be removed either bypolishing or etching. The polishing is usually done using abrasives such as silicon carbide,alumina, or diamond with a lubricant to achieve the mirror-like finish. The larger the depth ofthe damaged layers, the greater the polishing efforts required.

In order to characterize the thermal damage, the damaged work surface cross sections onwafers were examined under scanning electron microscope. This helped to quantify the depthof damage. Fig. 12.15 a-b shows typical SEM photograph of the silicon wafers cross sectionssliced using various parametric conditions. In order to obtain the minimum thermal damagethat is in the range of 10 µm, energy must be minimum. In this case, minimum damage isobtained at current -3.5 A, Ton- 8 µs, Toff – 40 µs and servo reference voltage – 90V. Table 7presents the amount of thermal damage on wafer surface due to wire-EDM at differentregimes of energy parameters. According to Table 7, the energy parameter, pulse on-time andcurrent increase, the thermal damage also increases. At the same time, an increase in pulseoff-time from 35 to 40 µs shows a decrease in the thermal damage from 8.82 to 6.65 µm.However, the slicing speed at these processing conditions will be minimum at 0.28 mm/min.A balance between the slicing speed and depth of thermal damage must be maintained inorder to achieve moderate productivity by minimizing depth of damage. The smaller thedepth of damage, lower are the polishing efforts post slicing of silicon wafers.

To this end, it may be noted that the wafers cut by wire-EDM are free from saw marks,abrasives marks and micro-cracks that are often visible in the mechanical abrasive slicing bythe linear and wire saws (see Fig. 12.16). Thus wire- EDM is beneficial in terms of thisviewpoint. The wire-EDM, however shows thermal damage on the sliced surfaces. Themeasurement of thermal damage presented through microscopy shows that the extent of thethermal damage in wire-EDM and the mechanical abrasive processes is more or lessidentical.

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a. Current- 3.5 A, Voltage- 90V, Ton -8 µs b. Current- 5 A, Voltage- 90V, Ton -10 µsFig. 12.15: SEM images showing thermal damage of silicon wafers.

Table 7. Overview of investigated regimes and resulting thermal damage.Regimes I II III IV VCurrent (A) 3.5 4.5 3.5 3.5 3.5

Ton (µs) 8 8 10 8 8

Toff (µs) 30 30 30 35 40

Thermal damage (µm) 11.8 15.8 18.2 8.82 6.65

Fig. 12.16: SEM photographs of silicon wafer (a) wire sawn surface (b) wire-EDM surface.

2. Identification of material removal mechanism

Generally, during EDM, three types of material removal mechanisms occur:melting/evaporation, spalling and oxidation/decomposition. Fig. 12.17 shows surfacetopography of silicon wafer machined by wire-EDM process in deionized water. The Figureindicates regularly formed craters and no evidence of foamy or porous layer is observed. Thesurface shows that melting and evaporation are the most dominant material removalmechanisms. It is unlike to the ceramic materials which show formation of foamy or porous

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layer indicating oxidation/decomposition being the dominant material removal mechanism.Further, the surfaces do not show presence of large micro-cracks or irregularly shaped craterswhich, usually considered as an evidence of thermal spalling, a mechanism usually observedin EDM machining of ceramics at higher energy levels.

Fig. 12.17: SEM photograph of silicon wafer surface machined by wire-EDM.3. Effect of energy on surface topography

To understand the effect of energy parameters on surface topography, voltage-currentwaveforms were captured and correlated with crater geometry. Figure 4 shows a combinationof voltage current waveforms at different parametric combinations of current and pulse on-time. The wire-EDM surfaces shows crater formations like those on wire-EDMed surfaces ofsteel. Fig. 12.18 also shows an increase in crater diameter from 20 to 35 µm as currentincreases from 3.5 to 5 A and an increase in pulse on-time from 8 to 10 µs. It may be due toan increase in current and pulse on-time and the corresponding increase in the dischargeenergy of sparks causing wider craters. However, there are no visible subsurface micro-crackson wire-EDM surface like those observed on the wire sawn surfaces.

Fig. 12.18: Pulse shapes and corresponding surface topographies.

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4. Material contamination of machined wafer surfaces

The contamination of wire material on wafer surfaces is one of the major problems inexisting silicon ingot slicing methods. However, it is observed that the surfaces machined bywire-EDM do not have any contamination of the wire material. Fig. 12.19 (a) and (b) showthe EDS (Energy-dispersive X-ray spectroscopy) spectrum of the silicon surface before andafter machining, respectively. The silicon surface after machining does not show any traces ofthe wire material, namely, copper and zinc.

Fig.12.19: (a-b) EDS analysis of silicon surface (a) before wire-EDM (b) after wire-EDM.

Conclusion

The wafer surface characterization depicts that silicon wafers generated by wire-EDMprocess are free from wire material contamination and subsurface damages. However, inorder to minimize the post processing operations, the thermal damage must be minimized byproper selection of processing conditions. This work will leads to the development of a novelwire-EDM process for slicing of silicon wafers for application in Photovoltaic cells. Finally,the aim is develop the technology by keeping the view on transferring value of research to thebenefit of Industry. Applied Materials have shown interest in this work and startedcollaborative project on this with IIT Bombay.

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