CSE539: Advanced Computer Architecture

ACADEMIC TASK #2 [HOMEWORK]

Section: K2R21 Course Teacher: Mr. Sumit Mittu

Instructions

i. Applicable to Roll Nos.: 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40

ii. Attempt all questions and parts thereof.

iii. Answer the questions in serial order. Put the correct question no. and part no. against answers.

iv. Diagrams, illustrations, etc. in the answers shall be neatly drawn and well-labelled.

v. Download the cover-page format from UMS and use it. Start answering from the cover-page itself.

vi. Submission would be taken in scheduled lecture of 22-Oct-2012. Submission after class will not be entertained.

vii. Award of 0 marks: Plagiarism in any form (from each other, internet or same source, etc.).

To avoid plagiarism, study from suitable resources but write the answers from your own mind.

E.g. first study thoroughly from the book or website, then close the book or website and then write ion

your own without peeping into the book or website.

Questions

1 Illustrate direct mapping, fully associative mapping and sector mapping (1 sector = 4 blocks) over

the memory unit such that main memory contains 64K words of 8 bits each and cache has the

capacity of holding 64 words of 8 bits each. Each block in memory consists of 32 words.

[15 marks]

2 Considering the reservation table(s) given below:

a) Draw the block diagram of the pipeline.

b) Identify the streamline connection, feed-forward connection and feedback connections.

c) Determine the forbidden latencies for the operation X.

d) Compute speedup and efficiency of the pipeline as against non-pipelined processor

1 2 3 4 5 6 7 8

S1 X

S2 X X X

S3 X X

S4 X X

[10 marks]

3 Determine the theoretically possible maximum throughput of a pipeline processor with k-stages

and n-tasks.

[5 marks]

4 Loop-unrolling is a relatively simple technique used by compiler to make independent instructions from

multiple successive iterations of a loop to execute in parallel. Explore this concept and illustrate it with

the help of an arbitrary program example.

[5 marks]

For additional practice, solve the exercise questions of Chapter 5 and 6 of the text book.

Mode: Manual (handwritten) DOA: 16-10-2012 DOS: 22-10-2012

CSE539: Advanced Computer Architecture

ACADEMIC TASK #2 [HOMEWORK]

Section: K2R21 Course Teacher: Mr. Sumit Mittu

Instructions

i. Applicable to Roll Nos.: 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38

ii. Attempt all questions and parts thereof.

iii. Answer the questions in serial order. Put the correct question no. and part no. against answers.

iv. Diagrams, illustrations, etc. in the answers shall be neatly drawn and well-labelled.

v. Download the cover-page format from UMS and use it. Start answering from the cover-page itself.

vi. Submission would be taken in scheduled lecture of 22-Oct-2012. Submission after class will not be entertained.

vii. Award of 0 marks: Plagiarism in any form (from each other, internet or same source, etc.)

a. To avoid plagiarism, study from suitable resources but write the answers from your own mind.

E.g. first study thoroughly from the book or website, then close the book or website and then write ion

your own without peeping into the book or website.

Questions

1 Illustrate direct mapping, fully associative mapping and sector mapping (1 sector = 4 blocks) over

the memory unit such that main memory contains 32K words of 16 bits each and cache has the

capacity of holding 1K words of 16 bits each. Each block in memory consists of 16 words.

[15 marks]

2 Considering the reservation table(s) given below:

a) Draw the block diagram of the pipeline.

b) Identify the streamline connection, feed-forward connection and feedback connections.

c) Determine the forbidden latencies for the operations A and B.

d) Compute speedup and efficiency of the pipeline as against non-pipelined processor

1 2 3 4 5 6 1 2 3 4 5

S1 A S1 B B

S2 A A S2 B

S3 A A A S3 B B

[10 marks]

3 Determine the theoretically possible maximum efficiency of a pipeline processor with k-stages and

n-tasks.

[5 marks]

4 Instructions execute in parallel on multiple functional units. A reorder buffer serves the function of

bringing completed instructions back into an order that is consistent with program order. Explore the role

of reorder buffer and state how it may address several types of dependencies in the program.

[5 marks]

For additional practice, solve the exercise questions of Chapter 5 and 6 of the text book.

Mode: Manual (handwritten) DOA: 16-10-2012 DOS: 22-10-2012

CSE539: Advanced Computer Architecture

ACADEMIC TASK #2 [HOMEWORK]

Section: K2R21 Course Teacher: Mr. Sumit Mittu

Instructions

i. Applicable to Roll Nos.: 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39

ii. Attempt all questions and parts thereof.

iii. Answer the questions in serial order. Put the correct question no. and part no. against answers.

iv. Diagrams, illustrations, etc. in the answers shall be neatly drawn and well-labelled.

v. Download the cover-page format from UMS and use it. Start answering from the cover-page itself.

vi. Submission would be taken in scheduled lecture of 22-Oct-2012. Submission after class will not be entertained.

vii. Award of 0 marks: Plagiarism in any form (from each other, internet or same source, etc.)

a. To avoid plagiarism, study from suitable resources but write the answers from your own mind.

E.g. first study thoroughly from the book or website, then close the book or website and then write ion

your own without peeping into the book or website.

Questions

1 Illustrate direct mapping, fully associative mapping and sector mapping (1 sector = 4 blocks) over

the memory unit such that main memory contains 16K words of 32 bits each and cache has the

capacity of holding 512 words of 32 bits each. Each block in memory consists of 8 words.

[15 marks]

2 Considering the reservation table(s) given below:

a) Draw the block diagram of the pipeline.

b) Identify the streamline connection, feed-forward connection and feedback connections.

c) Determine the forbidden latencies for the operations P, Q, and R.

d) Compute speedup and efficiency of the pipeline as against non-pipelined processor

1 2 3 4 5 1 2 3 1 2 3 4 5

S1 P S1 S1 R

S2 P S2 Q S2 R R

S3 P S3 Q Q S3 R

S4 P P S4 S4 R

[10 marks]

3 Determine the theoretically possible maximum speed-up of a pipeline processor with k-stages and

n-tasks.

[5 marks]

4 Output dependence (WAW) can be removed from executing program by assigning anther target register for

second write instruction i.e. register renaming. Explore the concept of register renaming and illustrate

with the help of an example if it can be adopted to resolve the WAR hazard.

[5 marks]

For additional practice, solve the exercise questions of Chapter 5 and 6 of the text book.

Mode: Manual (handwritten) DOA: 16-10-2012 DOS: 22-10-2012