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1276 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 8, AUGUST 2014

Ultraminiaturized WLAN RF ReceiverModule in Thin Organic Substrate

Srikrishna Sitaraman, Yuya Suzuki, Fuhan Liu, Nitesh Kumbhat, Sung Jin Kim,Venky Sundaram, and Rao Tummala, Fellow, IEEE

Abstract— This paper presents the design, analysis, anddemonstration of an ultra-thin wireless local area network(WLAN) RF receiver module with chip-last embedded actives andembedded passives in a low-loss organic substrate using system-on-package approach. The overall thickness of the module,including the embedded dies, is 160 µm– more than 3× thicknessreduction compared to current wire-bond and flip-chip packages.The receiver module consists of gallium arsenide low-noiseamplifier (LNA) dies, chip-last embedded in an ultrathin, low-loss organic substrate, and connected to a substrate-embeddedthree-metal-layer band-pass filter (BPF) in close proximity. Full-wave electromagnetic simulation was performed on a 3-D modelof the designed receiver module to obtain its two-port scat-tering parameters (S-parameters) and to study noise couplingbetween the power-supply network and the signal path. Thereceiver module was then fabricated, tested for yield of theBPF, assembled and characterized, and the measured resultswere correlated with simulation. The BPF dimensions in thepackage were 1.5 mm × 2.9 mm × 0.15 mm, and its measuredpass-band insertion loss was 2.3 dB with more than 15 dBreturn loss. The receiver module (LNA + BPF) dimensions were5.5 mm × 2 mm × 0.16 mm, and it had a measured peak gain of11 dB with more than 30 dB attenuation in the adjacent-band,indicating excellent performance in a miniaturized form-factor.

Index Terms— Chip-last embedding, embedded passives,low-noise amplifier (LNA), organic substrate, system-on-package(SOP), wireless local area network (WLAN).

I. INTRODUCTION

THE growing demand for smart mobile systems drivesthe development of miniaturized electronic devices with

increased functional density. System-on-package (SOP) [1]and system-on-chip (SoC) are two major approachesfor system integration. For digital integration, SoC andthrough-silicon-via integration approaches have achievedminiaturization with improved performance and low cost.However, to miniaturize radio frequency (RF) components,SoC-based solutions [2], [3] suffer from very low Q-factor and

Manuscript received October 26, 2013; revised March 20, 2014; acceptedMarch 27, 2014. Date of publication June 26, 2014; date of current versionJuly 31, 2014. Recommended for publication by Associate Editor A. Shapiroupon evaluation of reviewers’ comments.

S. Sitaraman, F. Liu, N. Kumbhat, S. J. Kim, and V. Sundaramare with the Department of Electrical and Computer Engineer-ing, Georgia Institute of Technology, Atlanta, GA 30332 USA(e-mail: [email protected]; [email protected]; [email protected];[email protected]; [email protected]).

Y. Suzuki and R. Tummala are with the Department of Material ScienceEngineering, Georgia Institute of Technology, Atlanta, GA 30332 USA(e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2014.2325592

Fig. 1. Components of a WLAN sub-system.

high cost. Alternately, SOP approach effectively addresses therequirements of multifunctional wireless systems by enablingminiaturized high-performance RF and mixed-signal integra-tion at low cost [1]. Traditional SOP-based integration ofhigh-performance actives and passives for WLAN RF moduleswas demonstrated on low-temperature co-fired ceramics(LTCC) substrates [4]–[6]. Subsequently, to overcome thelarge thickness of LTCC substrates, RF integration on organicmaterials, such as liquid crystal polymer (LCP), was developedwith surface mounted actives [7], [8]. Further, to address therequirement for low-profile form-factor and to improve RFperformance, embedded integration approaches, such as chip-first fan-out wafer level packaging [9], have been pursued [10].However, they face the following barriers: 1) yield loss issuesafter die embedding causing loss of both substrate and dies;2) technical challenges associated with embedding multipleheterogeneous components having dissimilar thicknesses; and3) thermal dissipation issues among densely integrated actives.To mitigate such concerns in miniaturizing high-performancemodules, SOP approach using chip-last embedding was pio-neered by and is currently being pursued at Georgia TechPackaging Research Center (GT-PRC) [11].

Chip-last embedded SOP has six essential advantages overSoC and chip-first approaches: 1) ability to embed multipleheterogeneous actives with minimal substrate yield loss;2) intermediate-testability of substrates and components beforeassembly; 3) shorter interconnections between components,enabling superior electrical performance; 4) accessibility ofthe die backside, facilitating improved thermal performance;5) flexible choice of substrate materials to address the require-ments of different components; and 6) low-cost manufactura-bility for market affordability. A typical WLAN RF receivermodule consists of an LNA and a BPF, as represented inFig. 1. Using chip-last SOP, functional WLAN RF receivermodules were demonstrated in ultrathin six-metal-layer andthree-metal-layer organic substrates [12], [13]. This paperextends on [13] by including the following: 1) extractionof S-parameters of the low-noise amplifier (LNA) dies from

2156-3950 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

SITARAMAN et al.: ULTRAMINIATURIZED WLAN RF RECEIVER MODULE IN THIN ORGANIC SUBSTRATE 1277

Fig. 2. Stack-up structure of the three-metal-layer substrate.

the LNA module [no band-pass filter (BPF)] measurement;2) 3-D full-wave electromagnetic (EM) simulation and char-acterization of the embedded BPF; and 3) 3-D full-waveEM simulation and analysis of the WLAN receiver module(LNA + BPF) design. The receiver module demonstrated hereis more than 3× miniaturized in thickness compared to currentwire-bond and flip-chip packages [14].

This paper is organized into six sections. Section I is theintroduction. Section II details the design of the LNA moduleand the receiver module (LNA + BPF). Section III presentsthe simulation and analysis of the receiver module. Section IVdiscusses the fabrication, assembly, and characterizationresults. Correlation between the simulation and measurementsis presented in Section V, followed by the conclusion inSection VI.

II. WLAN RECEIVER MODULE DESIGN

Miniaturization of RF components involves electrical designof miniaturized high-gain actives and high-Q passives, andinterconnecting these components with minimal substratelosses and interconnection parasitics. While superior perfor-mance of RF actives can be achieved through optimal designof GaAs and GaN dies, miniaturizing high-Q passives requiressubstrate materials having high permittivity (Dk) and low-loss tangent (Df); and short interconnections with reducedparasitics. For this paper, the dies were obtained from TriQuintSemiconductor, Inc., [15].

A. Substrate Material, Stack-Up, and Design Rules

To realize miniaturized high-Q passives, ZEONIF ™ XL(X-L)–a low-loss organic material–has been employed inthis paper. X-L, developed by Zeon Corp, is a halogen-freeglass–fiber-reinforced polymer laminate. The cross section ofthe stack-up is illustrated in Fig. 2. The substrate stack-upconsists of a core layer and a build-up film. To achievethis stack-up, a 100 μm-thick X-L prepreg (Dk = 6.5,Df = 0.0035) was laminated onto one side of an X-L copper-clad laminate (CCL) core (Dk = 6.2, Df = 0.0031) ofthickness 35 μm.

B. Design of LNA Module and Receiver Module

For this demonstration, two modules were designed, fab-ricated, and characterized: 1) an LNA module, designed withonly the LNA dies and without the filter– for comparison withthe original package from which the dies were sourced, and

Fig. 3. LNA module design top view.

Fig. 4. Simulated performance of the BPF.

2) a receiver module, designed by integrating the LNA diesand an embedded BPF–to demonstrate miniaturization withimproved performance over the original LNA package (nofilter).

1) LNA Module Design: The LNA module consisted oftwo embedded LNA dies along with RF signal transmis-sion lines and DC power supply rails. The RF transmissionlines were designed for 50 � impedance. EM simulation ofthe transmission lines was performed using SONNET [16].The dies were embedded in a cavity formed in the 100 μm-thick build-up layer and were connected to landing pads onmetal layer M2 with very short (15 μm height) copper–copper


Fig. 5. WLAN receiver module. (a) Schematic cross section and 3-D view. (b) Top view.

Fig. 6. Simulation flow used for analyzing the receiver module layout.

interconnections using thermo-compression bonding [17].Since the separation between the active side of the die andthe ground plane (M3) was only 45 μm, the copper onM3 was etched away under the dies to avoid eddy-currentlosses in the on-chip inductors. Metal patches were added tothe power-supply rails on M1 to facilitate surface assemblyof the decoupling capacitors. The LNA module occupied anarea of 2.6 mm × 2.1 mm, as shown in Fig. 3. However, thecoupon for this module was designed bigger to accommodateadditional structures that aid in characterization. The thicknessof this module was 160 μm.

2) Receiver Module Design: The receiver module designessentially integrated the LNA module with an embeddedband-pass filter. The circuit schematic of the filter was sim-ulated using Agilent ADS [18]. Based on the schematic, thelayout of the filter was designed and optimized using SONNETEM simulator [16]. To achieve the highest capacitance density,the capacitors were designed between metal-layers M2–M3across the thinner dielectric layer. The inductors were designedas two-layered structures across M2–M3 as well to increase themutual inductance. The metal on layer M1 was assigned as thefilter ground plane. To minimize the effect of ground parasitics,all the capacitors on M2–M3 were designed as stitched capac-itors [19]. The filter occupied an area of 1.5 mm × 2.9 mmand its simulated response is shown in Fig. 4.

For the receiver module design, this BPF was integratedwith the LNA module design, such that the BPF connectedthe antenna to the LNA. For the characterization of thismodule, the antenna was replaced with a set of RF-probe pads.

Fig. 7. Top view of the WLAN receiver 3-D model.

The schematic cross section, 3-D view and top-view of thereceiver module layout, is shown in Fig. 5. Its dimensionswere 5.5 mm × 2 mm × 0.16 mm.

III. FULL WAVE 3-D EM SIMULATIONS

The entire receiver module layout was simulated usingHFSS, a 3-D full-wave EM solver. The simulation flow shownin Fig. 6 was employed.

The receiver module layout design was imported into HFSSand set up for simulation. Setting-up the model includedthe following: 1) specifying the substrate dimensions andassigning stack-up materials; 2) creating tapered, conformally-metalized vias similar to the ones in the fabricated sample;3) defining metal types and thicknesses; and 4) assigning ports.The metal thickness was set as 10 μm on all the layers. SinceEM models of the dies were not available, the input and outputterminals of the dies were replaced with lumped ports. Further,to include the effect of the die on the package resonances, aperfect electric conductor (PEC) sheet was introduced at thelocation of the die active surface. To capture any noise cou-pling from the power supply network to the receiver moduleinput, a lumped port was located at the DC pads as well. Thesimulation was set-up for a driven terminal solution. A fre-quency sweep from 100 MHz to 20 GHz was defined in steps


Fig. 8. Characteristics of output RF signal path.

Fig. 9. Coupling from DC pad to RF signal path.

Fig. 10. Agilent ADS set-up to extract the LNA die S-parameters.

of 100 MHz. The top view of the 3-D model in HFSS is shownin Fig. 7, with the die cavity, the BPF, and the ports indicated.This model was simulated and its S-parameters were obtained.

The signal loss in the input and output RF paths and thecoupling from the DC pads to the RF signal paths are studied.The input signal path contains the BPF which has a loss of1.7 dB, as observed from Fig. 4. The insertion loss of theoutput signal path is shown in Fig. 8. It can be seen thatthe insertion loss at 2.4 GHz was 0.3 dB and return loss15 dB. Additionally, the noise coupling from the power supplynetwork to the signal input and output paths was also obtained,as shown in Fig. 9. Very low-noise coupling at the input iscritical, since the input signal level is low and any additional

Fig. 11. Complete package model created in Agilent ADS indicating signalflow.

Fig. 12. Complete receiver model simulated using HFSS and Agilent ADS.

Fig. 13. Image of the test vehicle mask layout.

interference would lower the signal-to-noise ratio (SNR) atthe input. It can be observed that even the worst-case noisecoupling at the input is as low as −40 dB up to 10 GHz.Thus the low insertion loss of the signal path and low-noisecoupling inside the package indicate that the noise added bythe package is very low.

Next, to obtain the S-parameter model of the LNA dies,the set-up shown in Fig. 10 was used. First, the S-parametersof the package interconnections of the LNA module(no filter) were obtained through the 3-D EM simulations


Fig. 14. Fabrication process steps.

Fig. 15. Images of (a) substrate prior to assembly. (b) Top view of die cavity.

using HFSS. Following this, the LNA module (no filter) wasfabricated and characterized. Then, the simulated S-parametersof the package interconnections were de-embedded from thecharacterized results of the LNA module. This yielded theS-parameter model of the LNA dies.

To simulate the complete receiver package along withthe dies, the simulated S-parameter model of the receiverpackage, and the de-embedded S-parameter model of the LNAdies were imported into Agilent ADS, as shown in Fig. 11.

The die model was connected to its correspondinginput–output port locations on the receiver package model.This set-up was then simulated in Agilent ADS to obtain theS-parameters of the complete package, as shown in Fig. 12.

IV. FABRICATION, ASSEMBLY, AND CHARACTERIZATION

A. Fabrication

The module layout was panelized and integrated into a test-vehicle for fabrication. The top-view image of the test vehiclelayout is shown in Fig. 13.

The fabrication process steps are depicted in Fig. 14.To achieve a good yield especially for the copper featureswith 30 μm spacing, semi additive process was employed for

Fig. 16. RF receiver module after assembly. (a) Top view. (b) X-ray image.

the metal patterning. The first step of substrate fabricationwas the drilling of through-vias in the XL CCL using laserablation to obtain vias of diameter 50 μm. Next, electro-lessplating was performed to metalize the vias with a seed layerof 1 μm (steps 1–2). This was followed by the photoresistlamination on the top side and photo-lithography to pattern thephotoresist, such that only the regions where the copper needsto be retained are exposed (step 3). Subsequently, electrolyticplating was performed to increase the thickness of the exposedcopper (step 4). Once the thickness of the plated copper wasclose to 10 μm, the photoresist was stripped away and theseed layer removed through microetching (step 5).

Then, the prepreg material was laminated on the top sideof the core (step 6) followed by blind via drilling and metalpatterning through subtractive etching (steps 7–8). Finally,cavities were formed on the build-up layer for die embedding,and nicked-gold surface finish was applied to the copper traces(step 9). An image of the substrate just before assembly isshown in Fig. 15 along with an image of the top view of thecavity containing copper traces and die landing pads.

B. Assembly

The ability to perform intermediate testing with chip-lastapproach helped to determine the yield of the BPFs throughcharacterization, prior to die assembly.


Fig. 17. Cross-section view of the receiver module.

Fig. 18. Measured response of the LNA module.

Fig. 19. Measured response of the RF receiver module.

The two LNA dies and the decoupling capacitors wereassembled on tested known-good coupons. The top view ofthe assembled receiver module and its X-ray image [13] areshown in Fig. 16. The ground planes on the backside of thedies were wire-bonded to each other and to the ground islandson the substrate. Multiple wire-bonds were used to achieve alow-inductance short between the substrate ground and thedies’ ground. After assembly, the modules were characterizedusing a vector network analyzer (VNA) to study the model-to-hardware correlation. A cross section of the fabricated receivermodule is shown in Fig. 17.

C. Characterization

After assembly, the LNA and receiver modules were char-acterized using the following set-up.

Fig. 20. Comparison of filter response simulation versus measurement.

Fig. 21. Comparison of receiver performance simulation versus measurement.

1) GSG RF probes: 500 μm pitch.2) DC supply: 3.3 V, 14 mA [15].3) Two-port VNA.4) Short open load thru (SOLT) calibration to isolate the

parasitics of the coaxial cables and probes.

The measured response of the LNA module is shown inFig. 18. The peak gain at 2.4 GHz was 14.13 dB with morethan 15 dB return loss. It is noteworthy that the measuredgain of the LNA module is comparable with its datasheetperformance [15], despite the fact that the LNA dies weredesigned and optimized for a wire-bond package.

The measured response of the RF-probe design is shownin Fig. 19. The peak gain of the receiver module was 11 dB,and the gain at 2.4 GHz was 9.2 dB with more than 25 dBadjacent band rejection (at 5.2 GHz). The isolation of GSM


band at 1.9 GHz was 32.35 dB. The shift in peak gain wasattributed to the pass band of the BPF shifting to 2.6 GHz,reducing the gain of the receiver module at 2.4 GHz.

V. ANALYSIS

A comparison between the performances of the 3-D full-wave EM simulation of the BPF and its measurement isshown in Fig. 20. A slight drift in the performance towardthe higher frequencies was observed and is attributed toprocess variations that potentially cause a reduction in thecapacitor or inductor values. Good correlation between thecomplete receiver package simulation and its measurement canbe observed from Fig. 21.

VI. CONCLUSION

This paper demonstrates a chip-last embedded WLANreceiver module in a low-loss organic substrate. The LNAmodule with dimensions 2.6 mm × 2 mm × 0.16 mm ismore than 3× smaller in volume compared with currentpackages [14]. It has a measured peak gain of 14 dB. Thereceiver module has a gain of 9 dB at 2.4 GHz. By comparingthe performance of the LNA and the receiver modules, verygood rejection of the adjacent frequency bands is observed inthe receiver module, validating the efficacy of the BPF. Themeasured response of the receiver module correlates well withthe results of the 3-D EM simulations. The dimensions of thereceiver module are 5.5 mm × 2 mm × 0.16 mm. Comparedwith current wire-bonded LNA packages without a filter [14],this receiver module, including the filter, is more than 1.5×smaller in volume. The receiver module thus demonstrated isthe thinnest known RF receiver organic package for WLANapplications, demonstrated to date.

REFERENCES

[1] R. R. Tummala and J. Laskar, “Gigabit wireless: System-on-a-packagetechnology,” Proc. IEEE, vol. 92, no. 2, pp. 376–387, Feb. 2004.

[2] R. Vaidya, D. Gupta, M. Bhakuni, and R. Prince, “A miniature lowcurrent fully integrated front end module for WLAN 802.11b/g appli-cations,” in Proc. IEEE CSIC Symp., Oct. 2007, pp. 1–4.

[3] H. Morkner, M. Karakucuk, G. Carr, and S. Espino, “A full duplex frontend module for WiFi 802.11.n applications,” in Proc. EuWiT, Oct. 2008,pp. 162–165.

[4] J. Ji, Y. Li, J. Fang, and Y. Fei, “Modeling and realization of a widebandLNA based on LTCC technology,” in Proc. ICMMT, vol. 1. Apr. 2008,pp. 378–381.

[5] B. C. Ham et al., “A GPS/BT/WiFi triple-mode RF FEM using Si-and LTCC-based embedded technologies,” in IEEE MTT-S Int. Microw.Symp. Dig., Jun. 2012, pp. 1–3.

[6] M.-C. Wu and S.-J. Chung, “A small SiP module using LTCC 3Dcircuitry for dual band WLAN 802.11 a/b/g front-end solution,” inTopical Meeting Silicon Monolithic Integr. Circuits RF Syst. Dig. Papers,Jan. 2006, p. 4.

[7] S. Dalmia, V. Govind, J. Dekosky, V. Sundaram, G. White, andM. Swaminathan, “Design and implementations of RF systems and sub-systems in LCP-type multilayer technology,” in Proc. 56th Electron.Compon. Technol. Conf., 2006, p. 5.

[8] T. Kamgaing, E. Davies-Venn, and K. Radhakrishnan, “A compact802.11 a/b/g/n WLAN front-end module using passives embedded in aflip-chip BGA organic package substrate,” in IEEE MTT-S Int. Microw.Symp. Dig., Jun. 2009, pp. 213–216.

[9] M. Brunnbauer, E. Furgut, G. Beer, and T. Meyer, “Embedded waferlevel ball grid array (eWLB),” in Proc. 33rd IEEE/CPMT IEMT Symp.,Nov. 2008, pp. 1–6.

[10] C. Durand et al., “High performance RF inductors integrated in advancedfan-out wafer level packaging technology,” in Proc. IEEE 12th TopicalMeeting SiRF, Jan. 2012, pp. 215–218.

[11] B.-W. Lee et al., “Chip-last embedded active for system-on-package(SOP),” in Proc. 57th ECTC, May/Jun. 2007, pp. 292–298.

[12] V. Sridharan et al., “Ultra-miniaturized WLAN RF receiver with chip-last GaAs embedded active,” in Proc. IEEE 61st ECTC, May 2011,pp. 1371–1376.

[13] Y. Suzuki et al., “Low cost system-in-package module using nextgeneration low loss organic material,” in Proc. IEEE 62nd ECTC,May/Jun. 2012, pp. 1412–1417.

[14] BGA622 Datasheet: Silicon Germanium Wide Band Low Noise Ampli-fier, Infineon, Neubiberg, Germany, 2008.

[15] TQM3M7001 802.11a/b/g Dual-Band, Low Noise Amplifier Module,TriQuint, Hillsboro, OR, USA, 2004.

[16] Sonnet EM Suite, Sonnet Software Inc., Onondaga, NY, USA, 2013.[17] A. Choudhury et al., “Low temperature, low profile, ultra-fine pitch

copper-to-copper chip-last embedded-active interconnection technol-ogy,” in Proc. 60th ECTC, Jun. 2010, pp. 350–356.

[18] Advanced Design System (ADS), Agilent EEsof EDA, Agilent, SantaClara, CA, USA, 2009.

[19] S. Min et al., “Filter integration in ultra thin organic substrate via 3Dstitched capacitor,” in Proc. Electr. Design Adv. Packag. Syst. Symp.,2009, pp. 1–4.

Srikrishna Sitaraman received the B.E. degree inelectronics and communications engineering fromAnna University, Chennai, India, in 2010, and theM.S. degree in electrical and computer engineeringfrom the Georgia Institute of Technology, Atlanta,GA, USA, in 2012, where he is currently pursuingthe Ph.D. degree with the 3-D Systems PackagingResearch Center.

He was with Intel Corporation, Phoenix, AZ, USA,as a Packaging Engineering Intern in 2012. Hiscurrent research interests include modeling, design,

and demonstration of ultraminiaturized high-performance wireless LAN radiofrequency packages using 3-D organic and glass substrates.

Yuya Suzuki received the degree from the Univer-sity of Tokyo, Tokyo, Japan, in 2007, focusing onpolymer solar cell.

He was with Zeon Corporation, Tokyo, where hewas involved in polymer science. He is currentlywith the Packaging Research Center, Georgia Insti-tute of Technology, Atlanta, GA, USA, as a VisitingEngineer. His main interests are polymer synthesis,polymer processing, and organic–inorganic hybridmaterials. His current research interests include thedevelopment of glass interposer and passive embed-

ded RF module using low-loss polymer material.

Fuhan Liu is an Associate Program Manager ofMultilayer RDL Research with the 3D SystemsPackaging Research Center, Georgia Institute ofTechnology, Atlanta, GA, USA. He is currentlyinvolved in the research and development of system-on-a-package integrations, ultrafine pitch redistrib-ution layer low-cost glass interposer and package,low-cost organic interposer and package, low-costlow-CTE ultrathin high I/Os chip-embedded fan-outpackage, and embedded actives, passives, and opto-electronics integration technologies. He has devel-

oped and demonstrated various pioneer and leading edge technologies,including 1.5–5-um copper circuit traces multilayer RDL on glass, organic,and silicon packages using low-cost PCB and packaging facilities andprocesses, 1–2 metal layer low-CTE (2–4 ppm/0 C) package substrate withmore than 500 I/Os chip assembly with overall package thickness less than100 um, chip-last embedded IC chip in high-performance organic package for1–110-GHz multiband applications, high-bandwidth integrated optoelectronicssystems with optical interconnect and high-density electrical interconnect,and multispectral imaging using CMOS imager with mosaic filter for bioapplication. He has been involved in the area for more than 18 years.


Nitesh Kumbhat received the B.Tech. degree inmetallurgical and materials engineering from IITRoorkee, Roorkee, India, and the M.S. degree inmaterials science and engineering with a specializa-tion in microelectronics packaging from the GeorgiaInstitute of Technology (Georgia Tech), Atlanta, GA,USA, in 2003 and 2005, respectively.

He was with Intel, Phoenix, AZ, USA, from 2005to 2007, as a Package Technology DevelopmentEngineer, where he was involved in cutting-edgeflip-chip mobile chipset package technology devel-

opment. He was with the Packaging Research Center at Georgia Tech as aResearch Engineer from 2008 to 2012, where he led the interconnectionsresearch. He joined Avago Technologies, Singapore, in 2012, and has beeninvolved in the area of MEMS packaging. He has experience with substratefabrication and chip-embedding technologies, finite element analysis, flip-chipassembly, and reliability analysis. He has several publications in journals,conferences, and magazines. His current research interests include interactionsbetween MEMS devices and packages.

Sung Jin Kim received the B.S. and M.S. degreesfrom Kookmin University, Seoul, Korea.

He has over 18 years of experience in the pack-aging industry as a Researcher, Developer, andTeam Manager with Amkor Technology, Gwangju,Korea, the Vice President at UTAC Corporation,Hsinch, Taiwan, the Managing Director at DaeduckElectronics Company, Ltd., Ansan, Korea, and theBusiness Unit Head at Foxconn Advanced Technol-ogy, Taipei, China. He built four factories in Asiafrom the scratch to full production for packaging,

IC substrate, and embedded technology. He developed and delivered theworld’s first 0.48-mm thickness multichip stacked lead frame package forNAND flash memory applications in 2004, lead system-in-package (SiP)development for system miniaturization, and Rmask substrate (no solder masktype substrate) development for JEDEC L-1 reliability packages in 2003,and directed board-on-chip package development using liquid elastomer dieattach material with liquid encapsulation for DRAM applications in 2001. Heis the inventor of many international patents for plastic BGA, stacked CSP,and SiP fields. He is currently with 3D Systems Packaging Research Center,Georgia Institute of Technology, Atlanta, GA, USA, where he is developingand commercializing leading-edge research programs with industry partners.He also teaches packaging courses and mentors graduate students.

Venky Sundaram received the B.S. degree from IITBombay, Mumbai, India, and the M.S. and Ph.D.degrees in materials science and engineering fromthe Georgia Institute of Technology (Georgia Tech),Atlanta, GA, USA.

He is the Director of Research and Industry Rela-tions with the 3D Systems Packaging Research Cen-ter at Georgia Tech. He is the Program Directorfor the Low-Cost Glass Interposer and Packagesindustry consortium with more than 25 active globalindustry members. He is a globally recognized an

expert in packaging technology and the Co-Founder of Jacket Micro DevicesInc., Decatur, GA, USA, an RF/wireless startup acquired by AVX. Heholds more than 15 patents and more than 100 publications. His currentresearch interests include system-on-a-package technology, 3-D packaging andintegration, ultrahigh-density interposers, embedded components, and systemsintegration research.

Dr. Sundaram is the Co-Chairman of the IEEE CPMT Technical Committeeon High Density Substrates, and is in the Executive Council of IMAPS asthe Director of Education Programs. He was a recipient of several best paperawards.

Rao Tummala (F’93) received the B.S. degree fromthe Indian Institute of Science, Bangalore, India, andthe Ph.D. degree from the University of Illinois atUrbana-Champaign, Champaign, IL, USA.

He is a Distinguished and Endowed Chair Pro-fessor, and the Founding Director of the NationalScience Foundation’s Engineering Research Centerat the Georgia Institute of Technology (GeorgiaTech), Atlanta, GA, USA, where he is involved inMoore’s law for system integration. Prior to joiningGeorgia Tech, he was an IBM Fellow, involved in

the first plasma display and multichip electronics for mainframes and servers.He has authored about 500 technical papers, holds 74 patents and inventions,and authored the first modern Microelectronics Packaging Handbook, the firstundergrad textbook Fundamentals of Microsystems Packaging, and the firstbook introducing the system-on-package technology.

Prof. Tummala is a member of the National Academy of Engineering andthe Past President of the IEEE Components, Packaging, and ManufacturingTechnology Society and the International Microelectronics and PackagingSociety. He was a recipient of many industry, academic, and professionalsociety awards, including the Industry Week’s Award for improving U.S.competitiveness, the IEEE’s David Sarnoff Award, the IMAPS’ Dan HughesAward, the Engineering Materials Award from the American Society forMicrobiology, and the Total Excellence in Manufacturing Award from SME.He was also a recipient of the Distinguished Alumni Awards from theUniversity of Illinois, the Indian Institute of Science, and Georgia Tech in2011. He was also a recipient of the Technovisionary Award from the IndianSemiconductor Association and the IEEE Field Award for contributions inelectronics systems integration, and cross-disciplinary education.

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