12/8/2004 EE 42 fall 2004 lecture 41 1

Lecture #41: Active devices

• This week we will be reviewing the material learned during the course

• Today: review– Active circuits– Digital logic– CMOS transistors

12/8/2004 EE 42 fall 2004 lecture 41 2

Example of the Load-Line MethodLets hook our 2K resistor + 2V source circuit up to an LED (light-emitting diode), which is a very nonlinear element with the IV graph shown below. Again we draw the I-V graph of the 2V/2K circuit on the same axes as the graph of the LED. Note that we have to get the sign of the voltage and current correct!!

I

2

4

(ma)

V (Volt)5

Solution: I = 0.7mA, V = 1.4V

I

+

-

V

+

-2V

2K

LEDLED

At the point where the two graphs intersect, the voltages and the currents are equal, in other words we have the solution.

12/8/2004 EE 42 fall 2004 lecture 41 3

Simplification for time behavior of RC Circuits Before any input change occurs we have a dc circuit

problem (that is we can use dc circuit analysis to relate the output to the input).

We call the time period during which the output changes the transient

We can predict a lot about the transient behavior from the pre- and

post-transient dc solutions

time

volt

age

input

time

volt

age

output

Long after the input change occurs things “settle down” …. Nothing is changing …. So again we have a dc circuit problem.

12/8/2004 EE 42 fall 2004 lecture 41 4

RC RESPONSEExample – Capacitor uncharged: Apply voltage step of 5 V

• We know this because of the pre-transient dc solution (V=0) and post-transient dc solution (V=5V).

• Clearly Vout starts out at 0V ( at t = 0+) and approaches 5V.

time

Vin

0

0

5

Vout

Input node Output node

ground

R

CVin

Vout+

-

So we know a lot about Vout during the transient - namely its initial value, its final value , and we know the general shape .

12/8/2004 EE 42 fall 2004 lecture 41 5

LOGIC GATE DELAY DTime delay D occurs between input and output: “computation” is not instantaneous Value of input at t = 0+ determines value of output at later time t = D

A

B

F

0

1

1

0

Logic State

t

t

D0

0

Input (A and B tied together)

Output (Ideal delayed step-function)

Actual exponential voltage versus time.

Capacitance to Ground

F

12/8/2004 EE 42 fall 2004 lecture 41 6

t

t

t

Logic state

2

0

SIGNAL DELAY: TIMING DIAGRAMS

Show transitions of variables vs time

1

0

t 2 3

Note that C changes two gate delays after A switches.

Note B changes one gate delay after A switches

A B C D

A

B

D

C

Note that D changes three gate delays after A switches.

Oscilloscope Probe

12/8/2004 EE 42 fall 2004 lecture 41 7

EXAMPLE OF THE USE OF DEPENDENT SOURCE IN THE MODEL FOR AN AMPLIFIER

V0 depends only on input (V+ V-)

)VV(AV0

+

AV+

V

V0

Differential Amplifier

AMPLIFIER SYMBOL

+

+

V0AV1

+

V1

Ri

Circuit Model in linear region

AMPLIFIER MODEL

See the utility of this: this Model when used correctly mimics the behavior of an amplifier but omits the complication of the many many transistors and other components.

12/8/2004 EE 42 fall 2004 lecture 41 8

NODAL ANALYSIS WITH DEPENDENT SOURCESExample circuit: Voltage controlled voltage source in a branch

Write down node equations for nodes a, b, and c.(Note that the voltage at the bottom of R2 is “known” so current flowing down from node a is (Va AvVc)/R2.)

R5

R4 VAA+

ISS

R3R1 Va Vb

+ AvVc

R6

Vc

R2

0R

VVR

VAVR

VV

3

ba

2

cva

1

AAa

0R

VVRV

RVV

5

cb

4

b

3

ab SS

6

c

5

bc IRV

RVV

CONCLUSION:

Standard nodal analysis works

12/8/2004 EE 42 fall 2004 lecture 41 9

NODAL ANALYSIS WITH DEPENDENT SOURCESFinding Thévenin Equivalent Circuits with Dependent Sources Present

Method 1: Use Voc and Isc as usual to find VT and RT (and IN as well)

Method 2: To find RT by the “ohmmeter method” turn off only the independent sources; let the dependent sources just do their thing.

12/8/2004 EE 42 fall 2004 lecture 41 10

NODAL ANALYSIS WITH DEPENDENT SOURCESExample : Find Thévenin equivalent of stuff in red box.

With method 2 we first find open circuit voltage (VT) and then we “measure” input resistance with source ISS turned off.

You verify the solution:

ISS

R3Va

+ A v V cs

R6

Vc

R 2

A)-1(RRR

)AR(RRIV

632

326SSTH

A)-1(RRR

)R(RRR

632

362TH

12/8/2004 EE 42 fall 2004 lecture 41 11

EXAMPLE: AMPLIFIER ANALYSISUSING THE AMPLIFIER MODEL WITH Ri = infinity:

Assume the voltage between the inputs is zero, and then figure out if that is consistent, or if the amplifier will hit a rail.

Method: We substitute the amplifier model for the amplifier, and perform standard nodal analysis

solution: RIN = VO/VIN = A1

A)R(1R SF

SF

F

A)R(1R

AR-

+

AV1

-

+V1

V-

V+

V0

RF

RSVIN

+ A

V-

V+V0

RF

RSVIN

12/8/2004 EE 42 fall 2004 lecture 41 12

OP-AMPS AND COMPARATORS

A very high-gain differential amplifier can function either in extremely linear fashion as an operational amplifier (by using negative feedback) or as a very nonlinear device – a comparator. Let’s see how!

+

+

V0AV1

+

V1

Ri

Circuit Model in linear region)VV(AV0

+

AV+

V

V0

Differential Amplifier

“Differential” V0 depends only on difference (V+ V-)

“Very high gain” A But if A ~ , is the output infinite?

The output cannot be larger than the supply voltages. It will limit or “clip” if we attempt to go too far. We call the limits of the output the “rails”.

12/8/2004 EE 42 fall 2004 lecture 41 13

WHAT ARE I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN DIFFERENTIAL AMPLIFIER ?

Example: Amplifier with gain of 105, with max V0 of 3V and min V0 of 3V.

VIN(V)1 2 3

V0 (V)

0.1

0.2

3 2 1

.2

(a)V-V near origin

3

(b)V-V over wider range

VIN(V)10 20 30

V0 (V)

1

30 20 10

21

23

upper “rail”

lower “rail”

+ V0

+

VIN

• Circuit model gives the essential linear part

• But V0 cannot rise above some physical voltage related to the positive power supply VCC (“ upper rail”) V0 < V+RAIL

• And V0 cannot go below most negative power supply, VEE i.e., limited by lower “rail” V0 > V-RAIL

12/8/2004 EE 42 fall 2004 lecture 41 14

THE RAILS

The output voltage of an amplifier is of course limited by whatever voltages are supplied (the “power supplies”). Sometimes we show them explicitly on the amplifier diagram, but often they are left off.

+

AV+

V

)VV(A V0=

Differential Amplifier

If the supplies are 2V and 0V, the output cannot swing beyond these values. (You should try this experiment in the lab.) For simplicity we will use the supply voltages as the rails.

So in this case we have upper rail = 2V, lower rail = 0V.

+

AV+

V

)VV(A V0=

VDD=2V

VSS=0

12/8/2004 EE 42 fall 2004 lecture 41 15

I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN DIFFERENTIAL AMPLIFIER (cont.)

VIN(V)1 2 3

V0 (V)

1

2

3 2 1

23

1

3

(c)Same V0 vs VIN over even wider range

3

(b)V-V over wide range

VIN(V)10 20 30

V0 (V)

1

30 20 10

21

23

upper “rail”

lower “rail”

Example: Amplifier with gain of 105, with upper rail of 3V and lower rail of 3V. We plot the V0 vs VIN characteristics on two

different scales

12/8/2004 EE 42 fall 2004 lecture 41 16

These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND, NOR, and EXCLUSIVE OR.

Logic Gates

A

BC=A·BAND C =

A

BNAND BA

C = NORA

BBA

NOTA A

ORA

BC=A+B

EXCLUSIVE OR

A

BBAC

12/8/2004 EE 42 fall 2004 lecture 41 17

Evaluation of Logical Expressions with “Truth Tables”

The Truth Table completely describes a logic expression

In fact, we will use the Truth Table as the fundamental meaning of a logic expression.

Two logic expressions are equal if their truth tables are the same

12/8/2004 EE 42 fall 2004 lecture 41 18

Some Useful Theorems

1)

2)

3)

4)

5)

6)

7)

8)

9)

1 AA

0 AA

C)(BACABA

ABC CBA

AB BA

BABA

BABA } de Morgan’s Laws

ABC CBA

AB BA

Each of these can be proved by writing out truth tables

Communicative

Associative

Distributive

Defined from form of truth tables

12/8/2004 EE 42 fall 2004 lecture 41 19

Synthesis

Designing the combinatorial logic circuit, con’t

Starting with any SUM-OF-PRODUCTS expression:

Y = ABC+DEF we can rewrite it by “inverting” with De Morgan:

Method 3: NAND GATE SYNTHESIS. If we may use De Morgan’s theorem we may turn the sum-of-products expression into a form directly implementable entirely with NAND gates. (We also need the NOT function, but that is accomplished by a one-input NAND gate). function.

The NAND realization, while based on DeMorgan’s theorem, is in fact much simpler: just look at the sum of products expression and use one NAND for each term and one to combine the terms.

(DEF) (ABC)Y

AB

YC

DE

F

Clearly this expression is realized with three NAND gates: one three-input NAND for , one for

, and one two-input gate to combine them:(ABC)

(DEF)

12/8/2004 EE 42 fall 2004 lecture 41 20

Synthesis

Designing the combinatorial logic circuit, con’t

Two Examples of SUM-OF-PRODUCTS expressions:

Method 3: NAND GATE SYNTHESIS (CONTINUED).

BABA X (X-OR function)

A

X

B

(No connection)

CBAABCY

A

Y

B C

We could make the drawings simpler by just using a circle for the NOT function rather than showing a one-input NAND gate

12/8/2004 EE 42 fall 2004 lecture 41 21

Controlled Switch Model of Inverter

The idea: If input is 3V then top switch open, bottom one closed. And if input is 0V, bottom switch is open, and top switch closed. Thus we connect the output (through one of the resistors RP or RN) to either ground or VDD.

Input OutputRN

-

+

SP is closed if VIN < VDD by 2V

RP

-

+

+

-

+

-

VDD = 3V

VSS = 0V

SN

SP

SN is closed if VIN > VSS by 2V

VIN VOUT

Note top, type P, switch is “upside down”

12/8/2004 EE 42 fall 2004 lecture 41 22

CMOS

Both NMOS and PMOS on a single silicon chip

NMOS needs a p-type substrate

PMOS needs an n-type substrate

But we can build in the same substrate by changing doping type

oxide

n-well

p p

GDG DSS

p-well

n n

We can butt the p and n together, or even let, for example the entire non n-well region be p type.

12/8/2004 EE 42 fall 2004 lecture 41 23

Basic CMOS Inverter

Inverter

IN OUT

VDD p-ch

VDD

OUT

IN

n-ch

CMOS Inverter

GROUND

IN

OUT

VDD

N-WELL

NMOS Gate

PMOS Gate

Al “wires”

GROUND

IN

OUT

VDD

N-WELL

NMOS Gate

PMOS Gate

Al “wires”

Example layout of CMOS Inverter

12/8/2004 EE 42 fall 2004 lecture 41 24

GROUND

IN

OUT

VDD

N-WELL

NMOS Gate

PMOS Gate

Al “wires”

12/8/2004 EE 42 fall 2004 lecture 41 25

n-typemetal metaloxide insulator

metal

p-type

metal

gate

source

drain

n-type

- +

VGS

- +

VDS

IDIG

G

DS

ID

IG

- VDS +

+

VGS_

NMOS Transistor

12/8/2004 EE 42 fall 2004 lecture 41 26

G

DS

ID

IG

- VDS +

+

VGS_

NMOS I-V Characteristic

• Since the transistor is a 3-terminal device, there is no single I-V characteristic.

• Note that because of the insulator, IG = 0 A.

• We typically define the MOS I-V characteristic as

ID vs. VDS for a fixed VGS.

• The I-V characteristic changes as VGS changes.

12/8/2004 EE 42 fall 2004 lecture 41 27

triode mode

cutoff mode (when VGS < VTH(N))

saturation mode

VDS

ID

VGS = 3 V

VGS = 2 V

VGS = 1 V

VDS = VGS - VTH(n)

NMOS I-V Curves

12/8/2004 EE 42 fall 2004 lecture 41 28

Saturation in a MOS transistor• At low Source to drain voltages, a MOS transistor looks

like a resistor which is “turned on” by the gate voltage• If a more voltage is applied to the drain to pull more

current through, the amount of current which flows stops increasing→ an effect called pinch-off.

• Think of water being sucked through a flexible wall tube. Dropping the pressure at the end in order to try to get more water to come through just collapses the tube.

• The current flow then just depends on the flow at the input: VGS

• This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source.