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The first real-world event example deals with a 15 kV breaker failure that occurred at a

Texas utility in summer 2002, which outlines the importance of overlapping zones of

protection.

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This slide shows the extensive damage to the cabinet caused by the 15 kV breaker failure.

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This slide shows how the 87B CT secondary wires melted as a result of the fault.

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For a fault on the bus at F1, the feeder relays do not see the fault and do not provide a

blocking input to the bus main relay. After waiting three cycles for a block to arrive, the bus

main relay trips to clear the bus fault.

For a fault at F2 on the feeder, the feeder relay sees that fault and provides a blocking input

to the bus main relay. The definite-time-overcurrent elements are not allowed to trip, giving

the feeder relay time to clear the fault first.

Various details of the fast bus trip scheme handle scenarios such as feeder relay failure,

feeder breaker failure, and so on.

For more information, see the SEL Application Guide titled, “Faster Distribution Bus

Tripping With the SEL-251/251C Relays,” by Mark Feltis. It is available at

www.selinc.com.

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Can you draw a logic diagram or traditional dc control schematic to represent this trip

logic?

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The trip logic in the bus main relay can be represented as a traditional direct current (dc)

control schematic. The 62 device represents the timer element S. The TSPU is the

programmable pickup time delay of 3 cycles. The output contact shown with the 62 timer

represents the Relay Word bit ST, which is the output of the timer.

For more information about fast bus tripping schemes, refer to SEL Application Guide

titled, “Faster Distribution Bus Tripping With the SEL-251/251C Relays,” by Mark Feltis.

It is available at www.selinc.com.

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Open the event file with a text editor and cut and paste the analog and digital event data

from the ER-triggered (1st) Bus Main event report into the TR-triggered (2nd) Bus Main event report. Save as a new event report name (…combined.txt).

Bus 2 Main Relay # 5539 Date: 5/26/6 Time: 6:56:55.620 [ copy

time from 1st event ]

FID=SEL-151C-R412-V656np0eqy-D940506-E2

Currents Voltages P Q N I Out In

A pri V pri

555T5 55 555 D B T13A 135

IR IA IB IC VA VB VC 100C0 10 100 E K &&&L &&&

LMIH LH M R C24R 246

-39 -409 -10 389 -12426 745 11844 ..... .. ... . . .... ..5

-49 214 -477 209 6393 -14084 7605 ..... .. ... . . .... ..5

39 409 10 -384 12421 -735 -11854 ..... .. ... . . .... ..5

49 -219 477 -209 -6398 14084 -7595 ..... .. ... . . .... ..5

[ 10 more cycles of 1st event report here]

[followed by 11 cycles of data from 2nd event report, followed by summary and

settings]

4189 -457 7249 -2612 -10681 1860 1601 pTTZp p. ppp . . .... 2.5

5901 156 -764 6504 6312 24 966 pTTZp p. ppp . . .... 2.5

-4184 448 -7234 2608 10667 -1860 -1610 pTTZp p. ppp . . T... 2.5

-5848 -156 788 -6480 -6316 -24 -976 pTTZp p. ppp . . T.3. 2.5

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Now that the time error is accounted for, the two events line up nicely. The three-phase

voltages from the bus main and the feeder are all shown on analog channel two. Knowing

that the time reference between the bus main and the feeder is accurate, the true time

difference between the feeder output A2 closing and bus main input IN2 asserting is about

6 milliseconds.

Had the dc wiring matched the settings (i.e., the feeder output A2 being wired to bus main

input IN6 as intended), the feeder breaker would have operated first and the fast bus trip

scheme of the bus main breaker would have been correctly blocked.

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