7/27/2019 16-Bit Binary Multiplication Using High Radix Analog Digits

1/5

16-bit Binary Multiplication Using High Radix

Analog Digits

Mitra Mirhassani

and Majid AhmadiRCIM Lab

Department of Electrical and

Computer Engineering

University of Windsor

Windsor, ON, CANADA, N9B 3P4

Email: mirhass@uwindsor.ca

Graham A. Jullien

ATIPS LabDepartment of Electrical and

Computer Engineering

University of Calgary

Calgary, AB, CANADA, T2N 1N4

Abstract In this paper, a binary multiplier based on theContinuous Valued Number System (CVNS), and consistingof arrays of current mode modulo adders, is discussed. TheContinuous Valued Number System uses analog current modecircuitry, with attendant very low system noise, to create arith-metic units with arbitrary equivalent digital precision. A seriesof analog digits, computing over arbitrary radix rings is used,in a forward correction mode, to achieve this comparable digitalaccuracy despite the fact that the implementation employs onlyrelatively simple analog circuits. To reduce the area and powerrequirements in CVNS multipliers, columns of partial productsare added in higher radices. In this paper, details of the designand implementation of a 16-bit binary multiplier in radix-4CVNS are provided.

I. INT ROD UC TI ON

Efficient logic circuit design is a fundamental task in the de-

sign of high performance devices. For arithmetic implemented

in System-on-Chip (SoC) technologies, there are increasingdemands on higher speed, limiting area, and system and cross-

talk noise. Most modern arithmetic processors are built with

architectures that have been well-established in the literature,

with many of the latest innovations devoted to special logic

circuits and the use of advanced technologies. Specifically, the

design of multipliers is critical in digital signal processing ap-

plications, where a high number of multiplications is required.

There are a wide variety of methods for multiplication with

complexity order n and log(n) gate delay. Array multipliersoffer regular layout, and are generated by a regular array of full

adders and half adders [1][7]. In this paper the design and

implementation of an array multiplier using the Continuous

Valued Number System (CVNS) is explored.The CVNS [8] has a potential advantage to reduce the

wiring complexity and the number of active devices required

in arithmetic circuits. The number system can provide an

alternative path in development of new types of arithmetic

and signal processing units. Classical analog circuit blocks

are used to construct the multiplier with arbitrary precision.

Despite its analog nature, the CVNS theory in fact produces

familiar arithmetic structures. While addition in the CVNS is

digit wise, multiplication is based on the array multiplication

structure.

The CVNS array multiplier consists of a regular arrange-

ment of addition operations and exploits the CVNS redun-

dancy. The term Array Multiplier is derived from the arraystructure of a collection of adders, where they are laid out on

a two-dimensional plane. The basis of the array multiplication

are integer residue scaling and residue addition. Such an

approach is used in developing the digital multiplier discussed

in this paper. The proposed multiplier is designed into the

target 0.18m CMOS technology and favourably comparedwith standard binary multipliers in the same technology.

II. CONTINUOUS DIGITS

Any value within a boundary such as |P| M from apositional number system with radix B, can be mapped to aset of associated CVNS digits, i, in radix-.

FCVNS : P CVNS

P FCVNS(P) = i (1)

The CVNS values, which are the ensemble of the CVNS

digits can be written as a vector as follows:

(, 1,...,1, 0|1, 2,...,) (2)

where i ( i ) represents digits of the correspondingCVNS number. In order to simplify out notation, letters from

the English alphabet to represent numbers in a weighted format

and then you use its Greek letter to indicate that the number

is now in CVNS format.

The CVNS digits are obtained by a general expression

applying the modulus operation:

i =pM

.BLi+1

0 i < L (3)

and digits with indices higher than L are obtained as follows:

i>L =

i1

0 i