174 ieee transactions on computer-aided design of...

174 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 1, JANUARY 2008

Reduction of Parametric Failures in Sub-100-nmSRAM Array Using Body Bias

Saibal Mukhopadhyay,Member, IEEE, Hamid Mahmoodi, Member, IEEE, and Kaushik Roy, Fellow, IEEE

Abstract—In this paper, we present a postsilicon-tuning tech-nique to improve parametric yield of SRAM array using bodybias (BB). First, we show that, although parametric failures inSRAM are due to local random intradie variations, the parametricfailures increase at extreme interdie corners. Next, we show thatproper BB can reduce different types of parametric failures.Finally, we show that adaptive application of BB to differentdies, based on their interdie corners, reduces the total numberof parametric failures in those dies. This helps to repair thefaulty dies at different interdie corners, thereby improving SRAMyield. We show that postsilicon-tuning using BB can result insignificant yield enhancement for SRAM (8%–25% in predictive70-nm technology).

Index Terms—Body bias (BB), parametric failures, SRAM,yield.

I. INTRODUCTION

LOCAL RANDOM (or intradie) Vt variation due to randomdopant fluctuation (RDF) introduces device mismatch in

an SRAM cell, resulting in functional failures, namely, read,write, access, and hold failures, collectively known as param-etric failures [1], [2]. The presilicon-design methods, such astransistor sizing, optimization of memory architecture, etc., canreduce the cell-failure probability [2]. If the number of param-etric failures in an SRAM die is small enough, it can be repairedusing available redundancy (optimized at the presilicon-designstage) [2], [3]. However, if the number of failures is too large,it may not be repaired using available redundancy. This leadsto yield degradation. Along with local random variation, thedevices in different SRAM dies also suffer from global die-to-die variations. Thus, it is important to understand the impact ofglobal variation on SRAM failures.

In this paper, we analyze the impact of global die-to-die vari-ation on different types of parametric failures. We show that theglobal die-to-die (or interdie) variation in device parameter (forexample, Vt) does not introduce any mismatch; the differenttypes of parametric failures can increase at different interdiecorners. In particular, read and hold failures dominate the pa-

Manuscript received November 30, 2005; revised October 24, 2006. Thiswork was supported in part by the Semiconductor Research Corporation underGrant 1078.001, by Gigascale System Research Center, by IBM, and by IntelCorporation. This paper was recommended by Associate Editor F. N. Najm.

S. Mukhopadhyay is with the School of Electrical and Computer Engineer-ing, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA (e-mail:[email protected]).

H. Mahmoodi is with the School of Engineering, San Francisco StateUniversity, San Francisco, CA 94132 USA (e-mail: [email protected]).

K. Roy is with the School of Electrical and Computer Engineering, PurdueUniversity, West Lafayette, IN 47907 USA (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCAD.2007.906995

Fig. 1. Yield-improvement strategy in SRAM array.

rametric failures in SRAM dies from low-Vt corners, whereasdies from high-Vt corners mostly suffer from write and accessfailures. Thus, after manufacturing (postsilicon), if read/holdfailures can be reduced in low-Vt dies and write/access failurescan be reduced in high-Vt dies, then the overall SRAM yieldcan be significantly improved. To explore the possibility of suchpostsilicon repair, we study the impact of body bias (BB) on dif-ferent cell failures. Our analysis shows that reverse BB (RBB)reduces read/hold failures, whereas forward BB (FBB) reducesaccess/write failures. Based on this observation, we developed apostsilicon adaptive-repair technique for SRAM (Fig. 1). Aftermanufacturing, first, the SRAM dies are divided into low-Vt,nominal-Vt, and high-Vt corners. Next, RBB is applied to diesshifted to low-Vt corners to reduce read/hold failures, whileFBB is applied to high-Vt dies to reduce write/access failures.This reduces the total number of parametric failures in a faulty

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MUKHOPADHYAY et al.: REDUCTION OF PARAMETRIC FAILURES IN SUB-100-nm SRAM ARRAY USING BB 175

Fig. 2. SRAM cell storing “0” at node R.

SRAM die, making it repairable using available redundancy.Note that the use of adaptive BB (ABB) in bulk-CMOS hasbeen earlier proposed to improve the yield of logic design [4],[5]. However, in this paper, for the first time, we study theeffect of BB on the parametric failures in SRAM and showthe effectiveness of ABB on SRAM yield. Moreover, processvariations also increase the leakage spread in an SRAM array.The proposed postsilicon-tuning technique helps to reduce theleakage spread, thereby decreasing the number of chips withhigh leakage (i.e., better leakage yield). The proposed schemeis applied to an SRAM array optimally sized using the methodpresented in [2] (Fig. 1). We observed that the proposed schemecould result in significant yield improvement (8%–25% forpredictive 70-nm devices).

II. BACKGROUND

In this section, we briefly discuss the different failure mech-anism in an SRAM cell.

A. Failure Mechanisms of SRAM Cell

The random variation in the device threshold voltage due toRDF results in parametric failures in SRAM cell [1], [2]. The Vtvariation in the cell transistors can be considered as independentGaussian random variables with the standard deviation given by

σδVti= (qTox/εox)

√NSUBWdm/3LW (1)

where Tox is the oxide thickness, Wdm is the width of the deple-tion region, and NSUB is the doping concentration in substrate.The parametric failures in an SRAM cell are principally due tothe following four mechanisms.1) Read Failure: Read failure occurs if the data stored in

an SRAM cell flips while reading the cell. If the voltage riseat the node (“R” in Fig. 2) storing “0” (i.e., VREAD in Fig. 2)rises to a value higher than the trip point of the inverter PL–NL(VTRIPRD), then the data stored in the cell flips. A higher

difference between voltage rise at the node (“R” in Fig. 2)storing “0” (VREAD) and the trip point of the inverter PL–NL(VTRIPRD)VTRIPRD reduces the read-failure probability(PRF) [2].2) Write Failure: Write failure occurs if a cell cannot be

flipped while writing. While writing “0” to the node L storing“1,” the voltage at L needs to be discharged below the trip pointof the inverter PR–NR. Time required for this event (write time,TWRITE) is an indicator of write-failure probability (PWF).Lower TWRITE indicates lower PWF [2].3) Access Failure: Access failure happens if the voltage

difference developed between 2-b lines (for example, ∆BIT)at the time of sense amplifier firing (for example, TACCESS)is lower than the offset voltage of the sense amplifier (forexample, ∆MIN). This leads to an incorrect sensing of the data.A higher discharging current (read current) through the nodestoring “0” (i.e., through AXR–NR in Fig. 2) indicates loweraccess-failure probability (PAF).4) Hold Failure: The destruction of the cell content in the

standby mode at a lower supply voltage is known as hold-stability failure [2]. Considering Fig. 2, stronger PL and lowerleakage for NL holds the node “L” more strongly at cellsupply, which reduces minimum data retention or hold voltage(VDDHmin). On the other hand, higher trip point of PR–NRmakes the cell easier to flip, thereby increasing VDDHmin. Ahigher VDDHmin increases hold-failure probability (PHF) [2].

B. Estimation of Failure Probability and Yield

The probabilities of different failure events and the overallcell failure (PF) can be estimated using the sensitivity-basedmethod proposed in [2]. The failure probability of column(PCOL) is defined as the probability that any of the cells (outof NROW cells) in that column fails. Assuming column redun-dancy, the probability of failure of a memory chip (PMEM),designed with NCOL number of columns and NRC number ofredundant columns, is defined as the probability that more thanNRC (i.e., at least NRC + 1) columns fail. Hence, PCOL andPMEM are given by [2]

PCOL=1−(1−PF)N

PMEM=NCOL∑

i=NRC+1

(NCOL

i

)P iCOL(1−PCOL)NCOL− i. (2)

To estimate the yield of an SRAM design, Monte Carlosimulations for interdie distributions of Vt (assumed to beGaussian) need to be performed. For each of the interdie valuesof the parameters (for example, VtINTER), we estimate PF,PCOL, and PMEM, considering the intradie distribution of δVt.Finally, the yield is defined as

Yield = 1 −(

NINTER∑INTER=1

PMEM(VtINTER)/

NINTER

)(3)

where NINTER is the total number of interdie Monte Carlosimulations (i.e., total number of SRAM chips).



Fig. 3. Effect of intradie variation on failure probability. (a) Variation in cell-failure probability. (b) Variation in PMEM with PF. (c) Variation in memory-failureprobability.

C. Memory Leakage Distribution

The total leakage of an SRAM cell in bulk-silicon technologyis composed of the subthreshold, the gate, and the junction-tunneling leakage, as shown in Fig. 2 [9], [10]. Consideringrandom intradie variation in Vt, the leakage of different cells(LCell) in a memory can be modeled as independent lognormalrandom variables [11]. The mean (µCell) and the standard de-viation (σCell) can be estimated using Taylor series expansion[2]. Using the central-limit theorem, the distribution of theoverall memory leakage (LMEM) (summation of leakage of allthe cells, for example NCell) can be assumed to be Gaussianwith mean (µMEM) and the standard deviation (σMEM) givenby [11]

µMEM = NCellµCell and σMEM =√

NCellσCell. (4)

Hence, the probability that LMEM is less than the maximumallowable limit (LMAX) is given by

PLeakMEM=P [LMEM<LMAX]=Φ(

LMAX−µMEM

σMEM

). (5)

Considering the interdie Vt variation, the ratio (LSuccess) ofthe number of chips that meet the above leakage bound to thetotal number of chips can be obtained as

LSuccess=

(NINTER∑INTER=1

PLeakMEM(VtINTER)/

NINTER

). (6)

An increase in LSuccess represents a design with a lowerleakage spread.

III. ADAPTIVE REPAIR OF SRAM ARRAY

An increase in random intradie Vt variation increases thecell- and memory-failure probabilities [1], [2]. In this section,we analyze the impact of interdie variation of Vt on differenttypes of parametric failures in an SRAM cell.

A. Analysis Methodology and Simulation Environment

We have designed an SRAM cell using predictive 70-nmdevices from Berkley Predictive Technology Model (BPTM)augmented with voltage-controlled current sources to model

the gate and the junction-tunneling current [10], [12]. First,considering only random within-die Vt variation due to RDF,the SRAM-cell structure is optimized using the methods pro-posed in [2] to minimize the cell-failure probability at nominalinterdie corner. Next, we applied a certain amount of interdie Vtshift (for example, ∆VtINTER) to all the transistors in the cell.This represents the cells of an SRAM die with interdie Vt shiftof ∆VtINTER. In the next step, we apply random within-die Vtshift (following Normal distribution with standard deviation ofσVt−INTRA) in the different transistors of that cell to estimatePF, PCOL, and PMEM at that interdie corner (using [2]). SPICEsimulation is used to estimate the sensitivities of cell parameters(such as VREAD, VTRIPRD, TWRITE, ∆BIT, and VDDHmin) toVt variations in different transistors.

B. Effect of Interdie Variation on Failures

A negative ∆VtINTER increases the read and the hold fail-ures [Fig. 3(a)]. To analyze read failure, consider expressionsfor VTRIPRD and VREAD with an interdie Vt shift (∆VtINTER)of cell transistors (assuming simple long-channel model of thedevice current) [13]

VTRIPRD=VTRIP(0)+∆VtINTER

√(βNL/βPL)−1√(βNL/βPL)+1

(7a)

VREAD=VREAD(0)−∆VtINTER

(1±

√βNR/βAXR√

1+βNR/βAXR

).

(7b)

Due to larger size and higher mobility of the NL ascompared to PL, β

NL/β

PL> 1. Consequently, VTRIPRD

reduces at a negative interdie Vt shift. VREAD increasesat a negative ∆VtINTER, as the saturation current throughAXR increases at a faster rate than the liner current ofNR with a reduction of Vt. Hence, a negative interdie Vtshift reduces (VTRIPRD − VREAD), thereby increasing theread failures. The negative Vt shift exponentially increasesthe leakage through the transistor NL. Although, it alsolinearly increases the current of the “ON” PMOS (in linearregion if VDD > VthPMOS), since NMOS current increasesexponentially, current ration between PMOS and NMOS



Fig. 4. Impact of ABB.

reduces. Hence, the node “L” is less strongly held at VDDH

at hold mode, resulting in a higher hold failure. In case of theSRAM arrays in the high-Vt process corners, the access failuresand the write failures are high [Fig. 3(a)]. This is principallydue to the reduction in the current drive of the access transistors.The hold failure may also increase at the high-Vt corners, as thetrip point of the inverter PR–NR increases with positive Vt shift.However, it is expected to be much lower than the write/accessfailures at the high-Vt corner. The arrays in the high-Vt corneralso have negligible read-failure probabilities. Hence, theoverall cell failure increases both at low- and high-Vt cornersand is minimum for arrays in the nominal corner [Fig. 3(a)].

From (2), it can be observed that PMEM depends on PCOL

through a binomial distribution. Therefore, beyond a thresholdvalue of PCOL (which depends on PF, NRC, and NCOL), asmall change in PCOL results in a large change in PMEM (fromnearly zero to nearly one) [Fig. 3(b)]. Hence, the memory-failure probability is either very high (≈1 in regions A and Cin Fig. 3(c), which represents a large interdie shift in Vt) orvery low [≈0 in region B in Fig. 3(c)]. Physically, in regionB, although the cell/column-failure probability is not zero, anumber of faulty columns are small enough so that the arraycan be repaired using redundancy. The reasons for high PMEM

in region A is due to more read and hold failures (low-Vtcorner), whereas that in region C is due to more access andwrite failures.

C. Adaptive-Repair Scheme for Yield Enhancement

Assume that PMEM = 1 in regions A and C (PA and PC)and PMEM = 0 in region B (PB), and the number of memorychips in regions A, B, and C are NA, NB , and NC , respectively(Fig. 4). Using (3), the yield can be obtained as

Yield = 1 −(

PANA + PBNB + PCNC

NA + NB + NC

)

=NB

NA + NB + NC. (8)

Therefore, if read/hold failures are reduced for dies in regionA (lower NA) and write/access failures are reduced for dies

Fig. 5. Impact of BB on RDF (BPTM 70 nm).

in region C (lower NC), the ∆Vt(inter) window for region Bwill be increased (higher NB) (Fig. 4). Essentially, this willshift a fraction of faulty dies from regions A and C to region B(nonfaulty). Note that if a faulty die is shifted from region Ato region B, the number of cells failing due to access and writefailures may increase. However, since most of the failures in afaulty die from region A are due to read/hold failures, total num-ber of faulty cells will reduce. Consequently, the die will havea higher probability of getting repaired using redundancy (i.e.,PMEM reduces). There might be instances where the new faults,due to access/write, appear in such a way that the die cannot berepaired (i.e., number of faulty columns might be larger thannumber of redundant columns). But a low value of PMEM inregion B ensures that the probability of this event is very small.Hence, if a large number of dies are shifted from regions Aand C to B, most of them will become nonfaulty, resultingin a higher yield. Note that this scheme does not reduce thelocal variation (e.g., RDF) itself. Rather, it reduces the global(die-to-die) variation to lessen the effect of local variation.

IV. EFFECT OF BB ON CELL FAILURE

In Section III, we observed that shifting the dies from low-and high-Vt corners to a nominal-Vt corner can improve yield.Body biasing can be an effective postsilicon-tuning techniqueto achieve this goal. Therefore, in this section, we discussthe impact of RBB and FBB on parametric failures. First,consider the effect of BB on Vt variation due to RDF. RBBincreases the width of the depletion region (Wdm), therebyincreasing the standard deviation of the Vt due to RDF [see(1)] (Fig. 5). However, overall change in the Vt variation withBB is not very significant.

A. Effect of BB on Cell Failure

BB modifies the Vt of a transistor—RBB increases the Vt,whereas FBB reduces it—which modifies the probability ofdifferent failure events. To simplify the analysis, consider onlythe application of BB to the NMOS transistors of an SRAM cellat the nominal interdie Vt corner.



Fig. 6. Impact of BB on parameters responsible for different failure events.(a) VREAD and VTRIPRD (read failure). (b) TWRITE (write failure).(c) ∆BIT (access failure). (d) VDDHmin (hold failure).

1) Access Failure: Since FBB reduces the Vt of the accesstransistors (larger discharging current), it also increases thebit differential obtained at the time of sense amplifier firing[Fig. 6(a)]. Hence, FBB reduced the access failure, whereasRBB increases it [Fig. 7(b)]. The sensitivity-based methodpresented in [2] can accurately predict the distribution of bitdifferential at different BB, as shown in Fig. 7(a).2) Read Failure: Application of RBB increases the Vt of

NMOS transistors. Hence, following the discussion inSection III-B, RBB reduces VREAD and increases VTRIPRD

[Fig. 6(b)], resulting in lower read-failure probability[Fig. 7(b)].3) Write Failure: Application of FBB reduces the Vt of the

access transistors, which increases the current (charging forAXR and discharging for AXL) through them, resulting inlower write time (TWRITE). Although FBB reduces the trippoint of PR–NR, the current increase through access transistorshas a stronger impact [Fig. 6(c)]. Hence, FBB reduces thewrite-failure probability, whereas RBB increases it [Fig. 7(b)].TWRITE is a stronger function of BB in cells designed withstronger PMOS [Fig. 6(c)].4) Hold Failure: Higher Vt with RBB reduces the leakage

through the transistor NL, which tends to increase VDDHmin.However, higher trip point of NR–PR (due to higher Vt of NR)reduces VDDHmin [2]. Similarly, higher FBB reduces the trippoint of PR–NR, but it also increases the leakage of NL. Thus,application of either large FBB or RBB increases VDDHmin

[Fig. 6(d)]. The BB required for minimum VDDHmin dependson the relative strength of pull-down and pull-up devices,as shown in Fig. 6(d). However, due to large sensitivity ofleakage to Vt variation, the variation in VDDHmin reduces withRBB. Hence, overall, RBB reduces the hold-failure probability[Fig. 7(b)].5) Overall Cell Failure and Optimum BB (OBB): Since

RBB and FBB modify different failures in different directions,

the effect of BB on overall cell failure depends on the transistorsizes. For example, for cells with a large access and a weakPMOS transistor (larger read failure at zero BB or ZBB), mini-mum cell failure is observed at the RBB. If the cell is designedwith a weak access transistor (higher access and write failures),then minimum cell failure is observed at the FBB. Hence, theapplication of the OBB (selected “a priori” before fabrication)can be used to minimize the cell-failure probability of anSRAM cell under a leakage constraint. However, simulationresults of an SRAM cell (optimally sized using [2]) in predictive70-nm technology show that the reduction in the overall failureprobability with OBB is not very significant [two to eight timesdepending on the σVt and area constraint, Fig. 7(c)]. This isbecause the optimal sizing tends to reduce the failure events insuch a way that cell failure at ZBB is very close to the minimumvalue.

B. Effect of BB on Leakage

The total cell leakage is composed of subthreshold, junction-tunneling, and gate-leakage components. FBB increases thesubthreshold leakage of a cell, whereas RBB reduces it[9]. In scaled technologies with large halo doping near thedrain/substrate and source/substrate junction, RBB can signifi-cantly increase the junction-tunneling leakage [9], [10] (Fig. 8).The gate leakage of the cell is due to both overlap and gate-to-channel tunneling. The overlap tunneling is insensitive to BB,whereas the gate-to-channel leakage marginally increases withFBB. Hence, the gate leakage of the cell is less sensitive to BB(Fig. 8) [9], [10]. Moreover, the application of a high forwardbias may turn on the source–substrate junction diode resultingin a significant increase in the leakage [9]. Hence, the maximumFBB and RBB that can be applied to a cell are determined bythe effect of BB on the cell leakage. For the 70-nm device withsmaller junction leakage, the leakage bound on the maximumRBB is not very critical and only a leakage bound for maximumFBB exists [Fig. 8(a)]. However, junction leakage increasesin more scaled devices due to the presence of higher “halo”doping. To understand this, we estimated the leakage of SRAM,designed using predictive 50-nm (Leff ∼ 32 nm) devices from[14], with reasonably high “halo” doping (required for reducingthe subthreshold leakage). The 50-nm device is first designed inthe device simulator MEDICI [15]. Next, using the parameter-extraction tool AURORA [16], the BSIM4 [17] parameters forthe device were extracted for SPICE simulations. Junction leak-age was modeled using voltage-controlled current sources inSPICE. Fig. 8(b) shows that, for a 50-nm device, large junction-tunneling leakage results in a maximum limit on allowableRBB. Hence, with technology scaling, cell leakage is expectedto impose upper bounds on both FBB and RBB.

V. YIELD ENHANCEMENT USING BB

It is observed in Section IV that FBB reduces write/accessfailures, whereas RBB reduces read/hold failures. In Section III,we observed that reduction of read/hold failures at the low-Vt corner and reduction of access/write failures at the high-Vtcorner could improve SRAM yield under interdie and intradie



Fig. 7. Effect of BB on parametric failures. (a) Comparison of Monte Carlo and sensitivity-based method in predicting bit-differential distribution with BB(similar accuracy is also observed for parameters related to other failures). (b) Cell failures with BB. (c) Failure reduction with OBB.

Fig. 8. Impact of BB on leakage at (a) 70 and (b) 50 nm.

variations. Using these observations, we propose an adaptiveapplication (postsilicon) of BB to improve SRAM yield. Wepropose to apply RBB in SRAM dies from low interdie Vtcorners (region A in Figs. 3(c) and 4) to reduce read/holdfailures. Although it may increase write/access failures in thosedies, the total number of failures is reduced as the dominantfailure mechanisms were read and hold failures. Similarly, theapplication of FBB to SRAM dies from high interdie Vt cornersreduces dominant access/write failures, thereby reducing thetotal number of failures. FBB at high-Vt corners increases readfailures; however, since read failures are significantly lowerin the high-Vt corner, it does not impact the total number offaults. FBB tends to increase hold failure by increasing leakageof NL. Since leakage is very low in the high-Vt corner, thiseffect is negligible. Moreover, in high-Vt corners, hold failuresare principally due to increase in the trip point of the inverterPR–NR. Since the application of FBB to NMOS reduces thetrip point of the inverter PR–NR, FBB even has a positiveimpact on hold failure at the high-Vt corner. Thus, overallimpact of FBB on hold failure at the high-Vt corner is notvery high. Note that the same BB is applied globally andstatically (not dynamic) to the entire die. The global applicationof BB counters the global (die-to-die) variation in a die andreduces the parametric failures caused by local (within-die)variation.

Let us consider the application of ABB to an SRAM array(NCOL = 128, NROW = 128, and NRC = 10) designed using70-nm BPTM devices [12]. The SRAM cells are initially op-timally sized to reduce the failure probability at nominal Vtand ZBB. ABB is applied to the SRAM arrays with optimallysized cells to evaluate its impact on yield. As explained earlier,the application of ABB widens region B (i.e., the region withPMEM ∼ 0), as shown in Fig. 9(a). In this particular case, anFBB of 0.2 V is applied for ∆Vt(inter) > 75 mV, and anRBB of 0.2 V is applied for ∆Vt(inter) < −75 mV (i.e., three-level ABB). Three-level ABB significantly improves designyield (8%–25% for σVt(inter) = 80−160 mV), as shown inFig. 9(b). Increasing the number of bias levels (which increasesthe design cost) improves the yield further. However, the ap-plication of OBB (selected “a priori” before fabrication for∆Vt(inter) = 0 and applied to dies at all ∆Vt(inter) values)does not result in considerable yield improvement. The im-provement in yield with ABB increases with an increase in theinterdie and intradie variability [Fig. 9(b) and (c)]. The applica-tion of ABB also reduces the interdie leakage spread, as RBBreduces the array leakage (subthreshold) in the low-Vt corner,whereas FBB increases it at the high-Vt corner [Fig. 10(a)].Hence, ABB improves the number of chips that satisfy the givenleakage bound (i.e., LSuccess) [Fig. 10(b)]. An increase in thenumber of the bias levels increases LSuccess [Fig. 10(b)].



Fig. 9. Impact of ABB on memory-failure probability. (a) PMEM ∼ interdie Vt shift, and yield versus standard deviation of (b) interdie and (c) intradie Vt shift.

Fig. 10. Impact of ABB on leakage (a) reduction in leakage spread (b) improvement in LSuccess.

VI. DISCUSSIONS

In Sections III–V, we explained the effectiveness of postsili-con tuning using BB in improving SRAM yield. In this section,we discuss several key implementation issues related to theproposed yield-enhancement scheme. We have implemented aself-repairing SRAM using the proposed scheme in 130-nmbulk-CMOS technology. The design details and hardware re-sults are presented in [18].

A. Quantized ABB

The yield-enhancement scheme proposed in Section V usesa quantized ABB scheme with one (or two) RBB and FBBvalues, instead of continuous positive- and negative-bias values.Moreover, this scheme does not require the estimation of exactinterdie Vt shift of a die. It only needs to detect whethera die falls in region A, B, or C. Hence, a feedback-basedanalog system with continuous-output on-chip bias generators(to apply proper BB to exactly nullify an interdie Vt shift)is not required. Digital-selection logic and fixed RBB/FBBgenerators can be sufficient for this scheme that significantlyreduce the design complexity [18]. Since the BB need to beselected from only three possible choices, it is feasible to useoff-chip biases (which are more stable). Note that to repair adie in region A (or C), we only need to shift it to region B

and not to the ∆VtINTER = 0 point [Fig. 3(c)]. Furthermore,the dies which are in region B do not require any bias even if∆VtINTER �= 0. Thus, it is not required to detect and nullify theexact ∆VtINTER shift, which implies that an analog solution isnot required. Due to the reasonably wide ∆VtINTER windowfor region B [∼200 mV in Fig. 3(c)], it is very unlikely thatBB will shift a die from region A to C (or vice versa, whichcan be called overcompensation). This eliminates the need forcontinuous-feedback system and ensures that a large (limitedby the leakage) RBB and FBB can be applied safely to regionsA and C. Moreover, the steep nature of the PMEM versus∆VtINTER function near the region boundaries suggests thata small shift (< 50 mV) in ∆VtINTER is enough to save alarge number of dies. It is possible to have such a Vt shiftwith large BBs (which is safe as explained above) even inscaled technologies where body effect is small. The earlierdiscussion explains why quantized ABB scheme is effective forthe proposed technique.

B. Vt Binning for ABB

We propose two alternative on-chip approaches for Vt bin-ning as follows: 1) monitoring the leakage of the memoryand 2) monitoring the cycle time (frequency) of a long ringoscillator (RO). Due to large variation in the leakage of amemory cell (due to the intradie Vt variation), it is difficult



Fig. 11. Leakage distribution of (a) single cell and (b) 16 000 cells for low,nominal, and high interdie Vt.

Fig. 12. Frequency distribution of (a) 3-stage RO and (b) 297-stage RO.

to distinguish between cells in the low- and high-Vt corners[Fig. 11(a)]. However, if the leakage of a large array (larger than1 kb) is monitored, the effect of local random variation [i.e.,σMEM/µMEM in (4)] significantly reduces, and only the effectof global variation remains [Fig. 11(a)]. Similarly, the effect oflocal random (intradie) variation is high in the frequency of aRO with small number of stages [Fig. 12(a)]. But if a long RO isconsidered, local delay variations of individual inverters tend tocancel each other. Consequently, delay of a long RO is primarilydetermined by the global variation [Fig. 12(a)]. Hence, arrayleakage or delay of long RO is a good indicator of the interdieVt corner even under a large intradie variation.

C. Selection of BB Voltage

The selection of FBB and RBB voltage to be applied to low-and high-Vt chips depends on several parameters. Increasingthe magnitude of BB improves the yield as more dies fromregions A and C can be shifted to region B. But if the bias valueis too high, then overcompensation can reduce yield. Similarly,higher bias values tend to reduce the leakage spread, therebyimproving LSuccess. But too large FBB significantly increasesthe subthreshold leakage of high-Vt dies, whereas too largeRBB can result in large junction leakage in low-Vt dies. Bothof these may reduce LSuccess. For example, Fig. 13(a) showsthat, for SRAM cells designed with 70-nm BPTM transistors,yield and LSuccess increase with an increase in the magnitudeof the BB voltages (considering three-level ABB). However, forthe 50-nm transistor (Section IV-B), which has larger junctionleakage, the application of a large RBB increases the cell leak-age, resulting in a lower LSuccess. The large junction leakagealso increases the hold failures in the low-Vt dies with RBB.Moreover, for the same redundancy, due to higher intradievariation, the width of region B is expected to be smaller forthe 50-nm technology. Consequently, overcompensation at high

bias levels also becomes more probable. Due to these factors,yield degradation can also be observed at higher bias values.This analysis suggests that proper optimization of FBB andRBB levels are required to maximize the benefit of the proposedmethod. Note that, in this analysis, we assumed the same mag-nitude for FBB and RBB. Different values for FBB and RBBwill provide an opportunity for optimizing them separately.

D. Scalability of the Proposed Scheme

The effectiveness of the proposed scheme with technologyscaling depends on the following device characteristics.

1) The sensitivity of the device Vt to BB (body effect)—Ahigher sensitivity improves the effectiveness.

2) The sensitivity of the total cell leakage with BB—Alower sensitivity of cell leakage to BB improves theeffectiveness.

Let us consider the predictive 70- and 50-nm devices afore-mentioned to understand the impact of the above two char-acteristics. Since the junction leakage is low in the 70-nmdevice, the maximum allowable BB is high. The sensitivityof Vt to BB is also reasonably high [200-mV BB results inapproximately 80-mV shift in Vt, Fig. 13(c)]. On the otherhand, higher short-channel effect in the predictive 50-nm de-vice requires a very strong halo to maintain a reasonable“off” current (suggested by the International Roadmap forSemiconductors [19]). The high “halo” doping improves thebody effect, and it is possible to achieve body effect similarto the 70-nm device [Fig. 13(c)]. But, due to high “halo”doping, the junction-tunneling leakage is high, which reducesthe maximum allowable RBB [Fig. 13(b)]. Consequently, weobserved that the yield improvement (as compared to the ZBBcondition) with the given RBB/FBB levels is comparable for70 and 50 nm (22% and 17%, respectively, for ±0.2 V inFig. 13). However, the maximum possible yield enhancement ishigher for the 70-nm device (∼32% with ±0.5 V) as comparedto 50 nm (∼17% with ±0.2 V). The above analysis suggeststhat, with proper device optimization and proper BB levels, theproposed scheme remains effective in improving SRAM yieldwith technology scaling. However, lower body effect and largerjunction leakage in scaled technologies reduce the achievableyield enhancement.

E. NMOS and PMOS BB

In this paper, we have primarily considered NMOS BB foradaptive repair. However, application of NMOS BB requirestriple-well process. On the other hand, PMOS BB can beapplied even in standard dual-well process. FBB to PMOSincreases its strength, which helps to reduce both read (higherVTRIPRD) and hold (node storing “1” is more strongly heldto VDD) failures. RBB to PMOS reduces its strength, whichhelps to improve write failures. Thus, PMOS BB can modifyread, write, and hold failures. But it does not change accessfailure. Hence, the yield enhancement using only PMOS BBis less efficient. If both PMOS and NMOS BB are used,then the effectiveness improves significantly. RBB to NMOSand FBB to PMOS increase trip point [Fig. 14(a)], thereby



Fig. 13. Selection strategy for BB: Effect of BB value on leakage and yield for (a) 70 nm, (b) 50 nm, and (c) sensitivity of Vt to BB.

Fig. 14. Impact of biasing both NMOS and PMOS BB. (a) VTRIPRD. (b) TWRITE. (c) VDDHmin.

improving the read failure. Similarly, for write failure, applyingFBB to the NMOS and RBB to the PMOS (which reduces itsstrength) reduces the write time [Fig. 14(a)]. For hold failures,application of RBB to NMOS and FBB to PMOS results in alower possible VDDHmin [Fig. 14(c)]. Hence, the application ofBB in PMOS and NMOS in opposite directions can be mosteffective in reducing cell failures.

F. Noncorrelated Interdie Shift for PMOS and NMOS

In this paper, we considered the conditions where interdie Vtshift of PMOS and NMOS are correlated, i.e., both moves tohigh- or low-Vt corners. This is justified when major source ofinterdie shift is variable in lithography parameters. However,other sources, such as global variation in p-type and n-typedoping density, can result in noncorrelated Vt shift for PMOSand NMOS. Let us now discuss the modification required to theproposed scheme to consider the scenarios where interdie Vt ofPMOS and NMOS shifts in opposite directions.

1) High-Vt PMOS and low-Vt NMOS significantly increaseread failures as VTRIPRD reduces (weak PL and strongNL) and VREAD increases. The degradation will be higherthan the case when both are becoming low-Vt. Similarly,hold failure will also significantly increase along withincreased leakage of NL; strength of PL holding the node“1” is also reduced. Arrays shifted to this corner canbe repaired using RBB for NMOS and FBB for PMOS.Access failure will be similar to the case when both arelow-Vt, as PMOS does not impact access time. However,

write failure will be better than the low-Vt corner, asweaker PL helps write operation.

2) High-Vt NMOS and low-Vt PMOS increase access fail-ure (weak NMOS) similar to the high-Vt case. At thiscorner, write failure is worse than the high-Vt corner,since weak AXL coupled strong PL can significantlyincrease the write time. To repair this scenario, FBB toNMOS and RBB to PMOS are required. Both read andhold failures will be significantly reduced (better than thehigh-Vt corner).

From the above discussion, we can observe that, if NMOSand PMOS Vt moves in the same direction, using only NMOSBB may be sufficient. However, if the Vt shifts are in oppositedirection, both PMOS and NMOS BBs are necessary. Hence,we believe that, if hardware resources permit, using both PMOSand NMOS BB is most efficient to repair SRAM arrays shiftedto different interdie corners.

VII. CONCLUSION

Technology scaling and increasing intradie parameter vari-ations increase parametric failures in SRAMs. In this paper,we have analyzed the effect of interdie variation on parametricfailures (read, write, access, and hold) in memory. Our analysisshows that read/hold failures are higher in SRAM dies shiftedto low interdie Vt corners, whereas write/access failures arehigher in dies shifted to high-Vt corners. Therefore, reducingread/hold failures in low-Vt dies while reducing access/writefailures in high-Vt dies can be effective in improving SRAM



yield. We further show that this can be achieved by applyingRBB to low-Vt dies (RBB reduces read/hold failures) and FBBto high-Vt dies (FBB reduces access/write failures). Simulationresults show that the adaptive repair of SRAM array using BBcan result in 8%–25% yield improvement in predictive 70-nmtechnology. Hence, we believe that BB can be used for postsil-icon adaptive repair/tuning of SRAM array resulting in bettermemory yield in nanometer technologies.

REFERENCES

[1] A. Bhavnagarwala et al., “The impact of intrinsic device fluctuations onCMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36, no. 4,pp. 658–665, Apr. 2001.

[2] S. Mukhopadhyay et al., “Modeling of failure probability and statisticaldesign of SRAM array for yield enhancement in nanoscaled CMOS,”IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 12,pp. 1859–1880, Dec. 2005.

[3] M. Horiguchi et al., “A flexible redundancy technique for high-densityDRAMs,” IEEE J. Solid-State Circuits, vol. 26, no. 1, pp. 12–17,Jan. 1991.

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[5] J. T. Kao et al., “A 175-MV multiply-accumulate unit using an adaptivesupply voltage and body bias architecture,” IEEE J. Solid-State Circuits,vol. 37, no. 11, pp. 1545–1554, Nov. 2002.

[6] K. Itoh, VLSI Memory Chip. New York: Springer-Verlag, 2001.[7] K. Osada et al., “Universal-Vdd 0.65–2.0-V 32-kB cache using a voltage-

adapted timing-generation scheme and a lithographically symmetricalcell,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1738–1744,Nov. 2001.

[8] B. Wicht et al., “Yield and speed optimization of a latch-type voltagesense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.

[9] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. NewYork: Cambridge Univ. Press, 1998.

[10] S. Mukhopadhyay et al., “Accurate estimation of total leakage innanometer-scale bulk CMOS circuits based on device geometry and dop-ing profile,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,vol. 24, no. 3, pp. 363–381, Mar. 2005.

[11] A. Papoulis, Probability, Random Variables and Stochastic Process.New York: McGraw-Hill, 1991.

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Saibal Mukhopadhyay (S’99–M’07) received theB.E. degree in electronics and telecommunicationengineering from Jadavpur University, Calcutta,India, in 2000 and the Ph.D. degree in electrical andcomputer engineering from Purdue University, WestLafayette, IN, in 2006.

He was with the IBM T. J. Watson Research Cen-ter, Yorktown Heights, NY, as a Research Staff Mem-ber, working on high-performance circuit design.Since September 2007, he has been with the Schoolof Electrical and Computer Engineering, Georgia In-

stitute of Technology, Atlanta, as an Assistant Professor. His research interestsinclude analysis and design of low power and robust circuits in nanometertechnologies. He is a coauthor of more than 50 papers in refereed journals andconference proceedings.

Dr. Mukhopadhyay was the recipient of the IBM Ph.D. Degree FellowshipAward for 2004 and 2005. He was also the recipient of the SRC TechnicalExcellence Award in 2005, the Best in Session Award at the 2005 SRCTECNCON, and the Best Paper Awards at the 2003 IEEE Nano and the 2004International Conference on Computer Design.

Hamid Mahmoodi (S’00–M’06) received the B.S.degree in electrical engineering from Iran Universityof Science and Technology, Tehran, Iran, in 1998, theM.S. degree in electrical and computer engineeringfrom the University of Tehran, Tehran, in 2000, andthe Ph.D. degree in electrical and computer engi-neering from Purdue University, West Lafayette, IN,in 2005.

He is currently an Assistant Professor of elec-trical and computer engineering with the Schoolof Engineering, San Francisco State University,

San Francisco, CA. His research interests include design of low-power, robust,and high-performance circuits and architectures for nanoscale technologies. Hehas more than 50 publications in journals and conferences and five patentspending.

Dr. Mahmoodi was the recipient of the Best Paper Award at the 2004International Conference on Computer Design and the 2006 IEEE Circuits andSystems Society Very Large Scale Integration Transactions’ Best Paper Award.

Kaushik Roy (S’90–M’90–SM’95–F’02) receivedthe B.Tech. degree in electronics and electricalcommunications engineering from the Indian In-stitute of Technology, Kharagpur, India, and thePh.D. degree from the Electrical and ComputerEngineering Department, University of Illinois atUrbana–Champaign, Urbana, in 1990.

He was with the Semiconductor Process and De-sign Center, Texas Instruments, Dallas, where heworked on field-programmable gate-array architec-ture development and low-power circuit design. He

was the Chief Technical Advisor of Zenasis Inc. and Research Visionary BoardMember of Motorola Laboratories in 2002. Since 1993, he has been withthe Electrical and Computer Engineering Faculty, School of Electrical andComputer Engineering, Purdue University, West Lafayette, IN, where he iscurrently a Professor, a University Faculty Scholar, and holds the Roscoe H.George Chair of Electrical and Computer Engineering. His research interestsinclude very large scale integration (VLSI) design/computer-aided design fornanoscale Silicon and non-Silicon technologies, low-power electronics forportable computing and wireless communications, VLSI testing and verifica-tion, and reconfigurable computing. He has published more than 400 papersin refereed journals and conferences. He is the holder of eight patents. He isCoauthor of two books on low-power CMOS VLSI design (John Wiley andMcGraw Hill).

Dr. Roy was the recipient of the National Science Foundation Career Devel-opment Award in 1995, the IBM faculty partnership award, the AT&T/LucentFoundation Award, the 2005 Semiconductor Research Corporation (SRC)Technical Excellence Award, the SRC Inventors Award, and the Best PaperAwards at the 1997 International Test Conference, the IEEE 2000 InternationalSymposium on Quality of IC Design, the 2003 IEEE Latin American TestWorkshop, the 2003 IEEE Nano, the 2004 IEEE International Conferenceon Computer Design, the 2006 IEEE/Association for Computing MachineryInternational Symposium on Low Power Electronics and Design, and the2005 IEEE Circuits and System Society Outstanding Young Author Award(with Chris Kim), and the 2006 IEEE TRANSACTIONS ON VLSI SYSTEMS.He has been with the Editorial Board of IEEE DESIGN AND TEST, IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON

VLSI SYSTEMS. He was Guest Editor for Special Issue on low-power VLSIin the IEEE DESIGN AND TEST in 1994 and in the IEEE TRANSACTIONS

ON VLSI SYSTEMS in June 2000 and the Institution of Electrical EngineersProceedings—Computers and Digital Techniques in July 2002.


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