1908 ieee journal of solid-state circuits, vol. 41, no. 8...

1908 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer WithContinuous-Time Wide-Bandwidth Delay Line

in 0.25-�m CMOSXiaofeng Lin, Member, IEEE, Jin Liu, Member, IEEE, Hoi Lee, Member, IEEE, and Hao Liu, Student Member, IEEE

Abstract—This paper presents an adaptive finite impulse re-sponse (FIR) equalizer with continuous-time wide-bandwidthdelay line in CMOS 0.25- m process for 2.5-Gb/s to 3.5-Gb/s datacommunications. To achieve wide bandwidth, fractionally spacedstructure is used and an inverter with active-inductor load designis proposed as the delay cell of the tap delay line. Close loop adap-tation of the fractionally spaced FIR equalizer is demonstratedusing a low-power and area-efficient pulse extraction methodas on-chip error detector. Measurement results show that theproposed adaptive equalizer achieves over 75% horizontal eyeopening when the channel loss at the half-data-rate frequencyvaries from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s datarate, the equalizer achieves 68% horizontal eye opening when thechannel loss is about 9.3 dB at the half-data-rate frequency. Theadaptive equalizer including the FIR filter and the error detectoroccupies 0.095 mm2 die area and dissipates 95 mW at 2.5-Gb/sdata rate from 2.5-V voltage supply.

Index Terms—Adaptive equalizers, CMOS analog integratedcircuits, continuous time filters, data communication.

I. INTRODUCTION

I N HIGH-SPEED data communications with data ratesover 1 Gb/s, receiver equalization has become an essential

building block to mitigate the inter-symbol interference (ISI)problem, which is due to limited bandwidth of low cost channelmaterials. Several equalization methods have been developed.The passive RLC high-pass filter [1] is a very low-power andefficient method, but, has little flexibility for adaptation. Onthe other hand, weighted parallel or serial combinations ofanalog active filters [2]–[10] offer low-power and area-efficientsolutions. A differential pair with either source degenerationcapacitor and/or passive load inductors is usually used to realizean active high-pass filter. Another approach is to use finite im-pulse response (FIR) filters, which offer wide ranges of transferfunctions digitally adjustable by tap coefficients. Digital FIRfilters have been widely used for equalization when data ratesare below 1 Gb/s. Nevertheless, digital FIR filtering requires ahigh-speed data converter. An alternative technique is to usesample and hold circuits (S&H) as the tap delay line [11]–[16]

Manuscript received December 5, 2005; revised March 3, 2006.X. Lin is with Texas Instruments Incorporated, Dallas, TX 75243 USA

(e-mail: [email protected]).J. Liu, H. Lee, and H. Liu are with the Department of Electrical Engineering,

Erik Jonsson School of Engineering and Computer Science, University of Texasat Dallas, Richardson, TX 75083-0688 USA (e-mail: [email protected];[email protected]; [email protected]).

Digital Object Identifier 10.1109/JSSC.2006.875302

to achieve several hundreds of Mb/s rate. Time interleavedstructure of parallel S&H cells with different sampling phasescan be used to further improve the data throughput to severalGb/s [17]–[24]. Decision feedback equalizers (DFE) [25]–[31]use tap delay line as well, however, since the input signal of thedelay line is one bit digital signal, it is much simpler than thedelay line used in feedforward FIR equalizer. In the latter case,the input signal to the delay line is the received signal, which isgenerally treated as an analog signal due to ISI. The major issuewith the DFE is the time constraints for the decision feedbackloop [32]. In addition, the DFE is part of the CDR loop. If theISI is severe, the received signal quality is poor, and the clockand data recovery circuits tend to fail together. In recent years,FIR filter with passive inductor delay line [33]–[36] achievesup to 40-Gb/s data rate. However, the use of on-chip inductorsin the tap delay line consumes large die area. To improve thearea efficiency, analog active tap delay line without inductorslooks attractive [37], [38]. However, since the group delay ofan active delay stage is related with the bandwidth, symbol-ratedelay usually cannot offer enough bandwidth. A fractionallyspaced FIR equalizer using an active inductor-less tap delay linehas been developed [39] to improve the delay line bandwidthabove 1 GHz from several hundreds of megahertz. However,the bandwidth of the delay line is still limited by multiple polesin each current-mirror based delay unit.

In this paper, inverter-based tap delay with active-in-ductor-load (INV-AIL) [40] is proposed for the fractionallyspaced equalizer (FSE). With the proposed delay line, anadditional zero is introduced by an active inductor load in eachdelay cell compared with the previous design [39]. Therefore,the speed of the equalizer has been enhanced to 3.5 Gb/s from1 Gb/s. In addition, close-loop adaptation of the fractionallyspaced FIR equalizer is demonstrated using a low-power andarea-efficient pulse extraction method [41] as on-chip errordetector. The paper is organized as follows. Section II willdiscuss the circuit design of the FIR filter, while Section IIIwill describe the adaptation issues of the equalizer. The experi-mental results and conclusion are presented in Sections IV andV, respectively.

II. CIRCUIT DESIGN OF THE FIR FILTER

A. FIR Filter Architecture

In this design, a fractionally spaced FIR equalizer is used;each tap delay provides a delay of 1/4 symbol period. The frac-tionally spaced delay line provides wider bandwidth compared

0018-9200/$20.00 © 2006 IEEE

LIN et al.: ADAPTIVE FIR EQUALIZER WITH CONTINUOUS-TIME WIDE-BANDWIDTH DELAY LINE IN 0.25- m CMOS 1909

Fig. 1. Block diagram of the proposed four-tap FIR filter.

with symbol rate delay line [39]. Fig. 1 shows the block dia-gram of the proposed four-tap fractionally spaced FIR filter. Itconsists of three delay stages, plus one dummy delay at the endof the delay line to provide similar load for the previous stage.The delay cells in front of the tap delay line are for DC biasingpurpose, which will be explained in detail in Section II-B. Themultiplying digital-to-analog (D/A) converters (MDAC) serveas multipliers. The current outputs of the MDACs are directlyconnected together to sum the current. Then, the differential cur-rent signals are converted to voltage signals through the loadresistors. A common-mode feedback circuit (CMFB) tunes twopairs of current sources to set the output common-mode voltage.The last stage of the filter is a limiting amplifier.

B. Tap Delay

The previous 1-Gb/s filter design [39] used a current mirrorwith a current-mode second-order biquad as delay cells, as wellas fractionally spaced delay to increase the bandwidth of thedelay line. However, the multiple poles reduce the bandwidth ofthe delay line. In this design, an inverter with an active inductorload is proposed as a delay cell to enhance the bandwidth of thedelay line. As a result, for the same CMOS 0.25- m process,the speed of the equalizer has been greatly enhanced to 3.5 Gb/sfrom 1 Gb/s. In this design, each tap delay consists of four delaycells; the dummy delay stage shown in Fig. 1 is also realized bya delay cell.

Fig. 2 shows the schematic of a delay cell; it is composedof an inverter with active inductor load (INV-AIL). The tran-sistors MN2 and MP2 provide low resistive load. As a result,the delay cell has a small voltage gain (designed to be close tounity), and does not function as a high-gain inverter. This is il-lustrated by the DC voltage transfer function of the delay cellin Fig. 3. The dotted line with unity slope is for comparison oflinearity with the voltage transfer curve in the solid line. It alsoshows that the input and output swing ranges are from 0.8 Vto 1.7 V. Within this wide range, the delay cell provides closeto unity small-signal gain. The transistors MP3 and MN3 in thegate connection of MN2 and MP2 realize two active inductors toincrease the bandwidth of the delay cell. The inverter with com-plementary MP1 and MN1 provides better linearity and wider

Fig. 2. INV-AIL delay cell.

Fig. 3. Large-signal voltage transfer function of the INV-AIL delay cell.

input common mode range, compared with a single-transistorinverting amplifier. In this design, the common-mode level is setby shorting the output of a delay cell with its input. In addition,on-chip bias helps to reduce the capacitance and impedance dis-continuity on the signal transmission path.

Fig. 4 shows the small-signal model of the delay cell, where, , , and are the transconductance of the

transistors MN1, MP1, MN2, and MP2, respectively.


Fig. 4. Small-signal model of the INV-AIL delay cell.

and are the gate capacitors of transistors MN2 and MP2,respectively. and are the channel resistors of MP3and MN3, which work in the deep triode region. is the totalchannel conductance of MN1, MP1, MN2, and MP2, andis the load capacitance, which equals to the input capacitanceof next delay stage. From small-signal analysis, the voltagetransfer function is as follows:

(1)

The low-frequency gain is, where can

be ignored in the denominator. We define as the averageof and , and as the average of and .Since it is desired to have unit gain for each tap delay, the designrequires the following equation to be satisfied:

(2)

Further, in order to simplify the analysis, we assume thefollowing condition and define a new term to represent

and :

(3)

As a result, the transfer function of the delay cell is approxi-mated as follows:

(4)This equation shows that the non-zero channel resistance of

MN3 and MP3 introduces a zero to the transfer function. When, which is equivalent to the case when the gates of

MN2 and MP2 are open and both transistors turn off, the transferfunction changes into . This isthe transfer function of a simple inverter. When , whichis equivalent to the case when the gates of MN2 and MP2 areshorted and both transistors work as active resistors, the transferfunction changes into

. This is the transfer function of unit gain first-orderlow-pass filter.

Further, as the is mainly the gate capacitor of the nextstage and a unit-gain delay cell required (2) to be satisfied, wehave

(5)

Replacing (5) into (4), the voltage transfer function becomes

(6)

where can be ignored in the denominator. This transfer func-tion has one zero, , and two poles, and , as follows:

(7)

(8)

(9)

The zero in the numerator helps improve the bandwidth.Since the factor in the denominator is , the rela-tionship between and also affects the transfer function.Fig. 5 shows the transfer function with normalized and

values. As increases, the increased factor enhancesthe bandwidth. Also shown in the figure is the transfer functionwithout the zero for the case of . Without the zero,the bandwidth is significantly smaller.

The circuits were designed in CMOS 0.25- m technologiesand simulated using Cadence Spectre. The simulation result ofone tap delay stage, shown in Fig. 6(a), illustrates that the zerointroduces a peak and the 3 dB bandwidth is around 4 GHz.Fig. 6(b) is the group delay response of one tap delay stage.Fig. 7 presents the tap delayed waveforms from simulation.Tap 1 is the input data to the delay line, Tap 2, Tap 3, and Tap4 are the delayed waveforms after one-, two-, and three-stagetap delay. Because of the peaking in the transfer function, theamplitude of the tap delay signal increases with the number oftap delay stages. The amount of delay of each stage is approx-imately 100 ps, as shown in the plot. Here, the input signal isa data waveform, instead of a sinusoidal waveform. Delayinga data waveform is more difficult than delaying a sinusoidalwaveform, since a data waveform has a richer spectrum up tosymbol rate frequency and a sinusoidal waveform has a singlefrequency.

The group delay of the delay cell can be adjusted by the gatevoltages of MN3 and MP3. In this design, the gate of MN3 isconnected to and the gate of MP3 is connected to Gnd. Asmentioned above, cascading of such four delay cells provides


Fig. 5. Bandwidth enhancement.

Fig. 6. Simulated (a) bandwidth and (b) group delay of one tap delay stage.

approximately 100 ps time delay from simulation. Since the FIRfilter is fractionally spaced, some variation of the tap delay doesnot change the filter transfer function significantly within thesignal bandwidth of interest. This is illustrated in Fig. 8. Thedotted curve represents the data spectrum. For symbol period of

, the first null of the data spectrum is . Most of

Fig. 7. Tap delayed waveforms: Tap 1 is the input signal of the tap delay line,Tap 2, Tap 3, and Tap 4 are the delayed signals after one-, two-, and three-stageof tap delay.

Fig. 8. Effect of tap delay variation on the transfer functions of fractionallyspaced equalizers.

the data signal power is below this frequency. The solid curverepresents the transfer function of the FSE. The FSE shown onthe top plot is spaced, thus, the tap delay .Correspondingly, the transfer function of the FSE has an effec-tive sampling frequency of . The FSEtransfer function folds at half of . The bottom plot showsan additional FSE transfer function when the tap delay deviatesfrom the desired , specifically, . As a re-sult, the effective sampling frequency is higher than fourtimes the data bandwidth, and the transfer function is stretchedout. However, due to over-sampling, the FSE transfer functionwithin the signal bandwidth does not change significantly. Inaddition, this change can be compensated by adjustment of tapcoefficients.


Fig. 9. The 4-bit MDAC.

C. Multiplier

The multiplier is implemented by an MDAC. Fig. 9 showsthe schematics of the MDAC and the encoder of a tap coeffi-cient. The MDAC multiplies the tap delayed signal, “In”, withthe tap coefficients represented by digital bits. In this design,each coefficient has 4 bits, the MSB is a sign bit which directsthe output signal of MDAC to the positive output port “outa”or the negative port “outb”, as shown by the encoder block.Other three bits set the gain of the MDAC. The transistors whosegates are connected to the coefficients are connected as cas-cade switches above the transistors whose gates are controlledby the “In” signal. This topology prevents the signal in “outa”and “outb” from coupling to the input though gate-drain capaci-tance. Since the input signal is also the input of next delay stage,such coupling deteriorates the quality of the equalized signal.The sources of the input devices are connected to the ground di-rectly, thus, the input gate capacitances are independent of theMDAC coefficients. The load capacitance at the MDAC outputnode increases with the number of MDACs (or the number oftaps), which limits the bandwidth of the FIR filter. Fig. 10 showsa simulation result on the linearity of the MDAC. The differen-tial output signal between “outa” and “outb” is the product ofthe input signal, “In”, and the tap coefficients. Here, three LSBsare used, since the MSB is a sign bit. There is minor saturationwhen the input level is close to either ends of 0.8 V and 1.7 V.

D. Common-Mode Feedback Circuit and Limiting Amplifier

A CMFB circuit, shown in Fig. 11, sets the common-modevoltage level at the output of the MDAC. The differential am-plifier composed of M1 to M4 controls the upper bypass currentsources, M9 and M10, and the differential amplifier composedof M5 to M8 controls the lower bypass current sources, M11and M12. To prevent current flowing directly through upper andlower current sources, the input of M5 is connected to VP, in-stead of the output common voltage, . When the level

Fig. 10. Linearity of the MDAC.

is near power supply, VP is high and turns off the upper bypasscurrent sources, while the lower bypass current sources are on.On the other hand, when the output common-mode voltage leveldecreases toward the ground, VP drops and causes VN to dropas well. As a result, the lower bypass current sources are shutoff, while the upper bypass current sources are turned on. In ad-dition, different reference voltages, Vrefa and Vrefb, are used tofurther reduce the overlapping area when the two bypass currentsources are turned on. In order to turn off M11 and M12 whenM9 and M10 are on, the reference voltage of the M5–M6 pair,Vrefb, is set to be higher than , whereis the threshold voltage of M9 and M10. As a result, when M9and M10 are turned on or VP is lower than , VNis low to turn off M11–M12. Fig. 12 shows the schematics ofthe limiting amplifier, which is the same topology as that usedin [39].

III. ADAPTATION

Fig. 13 illustrates the three essential blocks of an adaptiveFIR equalizer—the FIR filter, the error detector, and the adapta-


Fig. 11. Common-mode feedback circuit.

Fig. 12. Limiting amplifier.

Fig. 13. Block diagram of an adaptive equalizer.

tion controller. The error detector generates an error signal (costfunction) such that when the error is minimized, the equalizedsignal has wide open eyes with low bit error rate (BER). Basedon the error signal, the adaptation controller generates a set ofcoefficients for the FIR filter.

Fig. 14 shows the block diagram of the error detector usingpulse extraction method [41]. The pulse extraction circuit iscomposed of a symbol period delay unit, an inverter and an AND

gate. It extracts a pulse for every rising edge of the input signalA. The DC component of the pulse extractor output, signal B, isthe weighted integration of the input signal power spectrum; theweight factor is equivalent to a bandpass filter bank [41]. Com-paring the power spectrum of the equalized signal with a ref-erence signal using the pulse extraction method generates theerror signal. It is not necessary for the reference signal to bethe same as the original transmitted data, neither is it necessary

Fig. 14. Block diagram of the error detector using pulse extraction.

for the reference signal to be synchronized with the receivedsignal. The reason is that the error is the spectrum differenceof the equalized signal and the reference signal. As a result, thereference signal can be locally generated as long as it has thesame power spectrum as the originally transmitted data. This isusually readily available in a transceiver.

The adaptation part is not in the critical signal path, thus,the speed requirement is relaxed and the power consumption islower. Based on the error signal, the adaptation controller gen-erates the tap coefficients using generic search algorithms, suchas random weight change algorithm [42] or serial perturbationalgorithm [43]. Generally, the influences of the tap coefficientsto the FIR filter frequency response are not orthogonal, whichcould lead to multiple local minimum points in the error spaceof the frequency spectrum. In this design, the four coefficientsare limited to a fixed pattern to ensure conver-gence of the tuning process. The first tap is always the inverseto the fourth tap and the third tap remains zero. Such patternresults in only one global minimum point to guarantee conver-gence of the tuning process [41]. In addition, this also reducesthe complexity of the adaptation controller. In this design, eachtap provides a delay of 1/4 symbol period. Thus, the first andfourth tap coefficients, and , mainly define the high fre-quency response around the signal bandwidth, while mainlysets the DC and low-frequency responses.

This pattern deviates from the normal linear phase FIR filter,which requires the coefficient pattern of . Thefrequency magnitude responses of FIR filters with these two pat-terns are compared in Fig. 15, specifically one set of coefficients


Fig. 15. Frequency responses of FIR filters with coefficients [7 3 0 � 7] and[7 3 � 3 � 7], and a typical channel transfer function.

Fig. 16. Comparison of the equalized signals by filters with coefficients[7 3 0 � 7] and [7 3 � 3 � 7].

is and the other set is . Also shown in thefigure is the frequency response of a typical PCB trace channel.Although the linear phase pattern has a linear phase or constantgroup delay, it also results in zero amplitude response at DCfrequency since the sum of the coefficient equal to zero. Fromthe attenuation curve of the transmission channel, due to its ex-ponential attenuation relationship with frequency, the low-fre-quency components suffer very little loss. As a result, a DC zeroof a linear phase filter overly attenuates low-frequency compo-nents and distorts the equalized waveform. This is illustrated inFig. 16, which compares the equalized waveforms by the twoFIR filters. The dotted line is for the linear phase equalizer andthe solid line is for the equalizer with the proposed pattern. Thearrows identify locations where the low-frequency componentsare overly attenuated. In the case of first arrow from the left, theequalizer with the proposed coefficient pattern recovers severalconsecutive zeros. While the linear phase equalizer overly atten-uates the low-frequency components in these consecutive zerosand distorts the waveform from the desired shape. In addition,

Fig. 17. Adaptation procedure.

this also causes timing jitter as indicated around the thresholdlevel.

Fig. 17 shows the adaptation process used in this equalizer.The process starts with setting initial condition and calculatingthe spectrum information of a reference signal, Spec , andspectrum information of the equalized signal, Spec . Thesetwo values are generated from the error detector using pulseextractor followed by a low-pass filter. In each tuning period,the error detector computes the absolute difference between thespectrum information of the equalized signal and the referencesignal. The error signal is first compared with a preset toler-ance value, . If it is smaller than the tolerance value, theadaptation process stops, otherwise it will continue. The nextstep is to compare the current calculated error, Error_curr, withthe error calculated in the previous period, Error_prev. If thecurrent error is smaller than the previous one, it is changed inthe same direction (i.e., the status is unchanged). If the currenterror is larger, the status is updated by status status .With the pre-fixed coefficients pattern, there are only two co-efficients need to be updated. As a result, there are in total fourstatuses, corresponding to the increasing and decreasing of twotaps. When the status equals 5, it is set back to 1. This processrepeats until the error is smaller than the tolerance value.


Fig. 18. Chip micrograph.

Fig. 19. Test setup.

Fig. 20. Measured S21 parameters of PCB traces.

IV. MEASUREMENT RESULTS

The adaptive equalizer was fabricated in a standard CMOS0.25- m process with single-poly, six-metal, and N-well tech-nologies. Fig. 18 shows the chip micrograph with dimensions.The die size of the FIR filter is 0.085 mm . The error detector,including a pulse extraction circuit and a low-pass RC filter,occupies 0.01 mm . Fig. 19 shows the setup used to test theequalizer. An Anritsu pulse pattern generator MP1763B gener-ates a differential 2 1 pseudo random bit sequence (PRBS)as the transmitted data. The channel includes custom fabri-cated PCB trace (FR4 material) composed of two differentialmicrostrip transmission lines with characteristic impedance of50 , coaxial cables, and SMA connectors. The received signalis AC-coupled to the FIR filter. To test the adaptation perfor-mance of the adaptive equalizer, the length of the PCB trace is

Fig. 21. Tuning process of the 2.5-Gb/s adaptive equalizer for the 80-inch PCBtrace.

Fig. 22. Measured eye diagrams of (a) the received signal and (b) the equalizedsignal for 2.5-Gb/s data transmission over the 80-inch PCB trace.

varied from 20 to 120 inches. The measured S21 parameters ofthe differential PCB traces with different lengths are plotted inFig. 20. The adaptation controller is implemented using FPGAto allow flexibility for evaluating different search algorithms.The reference spectrum, Spec , was calculated by passing arandom sequence through an on-chip pulse extraction followedby a low-pass filter. The BER is measured with Anritsu errordetector MP1764A and the eye diagram is measured with aTektronix 20GS/s digital phosphor oscilloscope.

Fig. 21 shows the adaptation process of the equalizer for80-inch PCB trace. The channel attenuation for 80-inch PCBtrace is about 12 dB at the half-data-rate frequency of 1.25 GHz.After four iterations, the absolute error drops to a significantly


Fig. 23. Measured (a) horizontal and (b) vertical eye openings of the signals be-fore and after equalization for 2.5-Gb/s data transmission over various channellengths.

Fig. 24. Transfer function of the adapted equalizers for different PCB channels.

small value. Fig. 22 shows the measured eye diagrams of thereceived signal and the equalized signal; the voltage scale forboth plots is 100 mV per unit. While the eye diagram of thereceived signal is totally closed, the equalized eye has about80% horizontal opening and 65% vertical opening area toachieve BER of less than 10 . Fig. 23 shows the measuredhorizontal and vertical eye openings of the received and equal-ized signals as the channel length is varied from 10 inches to120 inches at 2.5-Gb/s data rate. This shows that the equalizercan achieve over 75% horizontal eye opening at 2.5-Gb/s data

Fig. 25. Measured eye diagrams of (a) the received signal and (b) the equalizedsignal for 3-Gb/s data transmission over the 80-inch PCB trace.

rate when the channel attenuation varies from 4 dB to 21 dBat the half-data-rate frequency of 1.25 GHz. The compensationrange can be increased by increasing the number of taps andthe number of bits in each tap.

To compare the equalizer gains after adaptation to differentPCB channels, we used the actual tap coefficients achievedafter adaptation to draw a group of equalizer transfer func-tions in Matlab as shown in Fig. 24. According to the designspecification and circuit simulation results, the equalizer is a

spaced equalizer. Therefore, the sampling frequencyfor 2.5-Gb/s data rate is 10 GHz. Thus, the transfer functionfolds at 5 GHz. If the actual tap delay deviates from the ex-pected value, the actual transfer function will be stretched orcompressed as illustrated in Fig. 8. The gains of these equalizertransfer functions shown in Fig. 24 match well with the channelattenuation characteristics shown in Fig. 20. This verifies thatthe adaptation process is successful.

We also test the performance of the equalizer at 3-Gb/s and3.5-Gb/s data rate. Fig. 25 shows the measured results com-paring the eye diagrams of the received and the equalized sig-nals at 3 Gb/s over an 80-inch PCB trace channel. While theeye diagram of the received signal after the 80-inch PCB traceis completely closed, the equalized signal has about 72% hori-zontal eye opening and 63% vertical eye opening. The channelattenuation for the 80-inch PCB trace is about 15 dB at thehalf-data-rate frequency of 1.5 GHz. Fig. 26 shows the mea-sured results at 3.5-Gb/s data rate over a 40-inch PCB tracechannel. The channel attenuation for the 40-inch PCB trace is


Fig. 26. Measured eye diagrams of (a) the received signal and (b) the equalizedsignal for 3.5-Gb/s data transmission over the 40-inch PCB trace.

TABLE IPERFORMANCE SUMMARY

about 9.3 dB at the half-data-rate frequency of 1.75 GHz. Thereceived signal has completely closed eyes and the equalizedsignal has about 68% horizontal eye opening and 45% verticaleye opening. Table I summarizes the performance of the adap-tive equalizer.

V. CONCLUSION

This paper has presented an adaptive FIR equalizer with con-tinuous-time wide-bandwidth delay line. Using the proposedINV-AIL delay cells and fractionally spaced delay line struc-ture, the bandwidth of the delay line is enhanced to achieve3.5-Gb/s data rate in standard 0.25- m CMOS technologies.Also presented is a low-power area-efficient adaptation tech-nique using pulse extraction method to detect the spectrum ofthe equalized signal. Experimental results show that the equal-

izer can successfully adapt to channel loss of 4 dB to 21 dB athalf-data-rate frequency for 2.5-Gb/s data rate and channel lossis about 9.3 dB at the half-data-rate frequency for 3.5-Gb/s data.The FIR filter and the error detector occupy 0.095 mm of diearea and consume 95 mW from 2.5-V supply at 2.5-Gb/s datarate.

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Xiaofeng Lin (S’02–M’04) received the B.S. degreein physics from Tsinghua University, Beijing, China,in 1997, and the M.S. and Ph.D. degrees in electricalengineering from the University of Texas at Dallas in2003 and 2004, respectively.

He joined Texas Instruments Incorporated, Dallas,TX, in 2004 and has been involved with the design ofhigh-speed serial link transceivers and mixed-signalGb/s equalizers.

Jin Liu (S’97–M’99) received the B.S. degree inelectronics and information systems from Zhong-shan University, China, in 1992, the M.S. degree inelectrical and computer engineering from the Uni-versity of Houston, Houston, TX, in 1995, and thePh.D. degree in electrical and computer engineeringfrom the Georgia Institute of Technology, Atlanta, in1999.

She joined the University of Texas at Dallas as anAssistant Professor in 1999 and is currently an Asso-ciate Professor at the same university. Her research

interests are high-speed communication circuits, sensor interface circuits, andsystem integration/miniaturization. Current projects include adaptive equaliza-tion and clock/data recovery circuits for high-speed data communications, low-power CMOS motion detection imagers, power and data transmission circuitsfor battery-less and wireless sensors, and high-speed A/D converters.

Dr. Liu is an associate editor of IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS PART II, EXPRESS BRIEFS.

Hoi Lee (S’00–M’05) received the B.Eng. (FirstClass Honors), M.Phil., and Ph.D. degrees in elec-trical and electronic engineering from the HongKong University of Science and Technology, HongKong, China, in 1998, 2000, and 2004, respectively.

In January 2005, he joined the Department ofElectrical Engineering, University of Texas atDallas, Richardson, TX, as an Assistant Professor.His research interests include low-voltage low-poweranalog and mixed-signal circuit techniques, powermanagement integrated circuits and biomedical

integrated systems for neural prostheses.Dr. Lee was the recipient of the Best Student Paper Award at the 2002 IEEE

Custom Integrated Circuits Conference.

Hao Liu (S’04) received the B.S. degree in electricalengineering from Wuhan University of Technology,Wuhan, China, in 1996, and the M.S. degree inelectrical engineering from the University of Texasat Dallas in 2002, where he is currently workingtoward the Ph.D. degree.

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