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M.Tech. Degree Examination, Dec.2013 I Jan.20l4GMOS VLSI Design

hrs.

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change in control input and for change in switched input.

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Note: Answer any FIVE full questions.

Derive the expression for the threshold voltage of a MOS transistor and explain the

significaace of different parameters present in the equation. (10 Marks)

Briefly .*p,F*- the fo llowing terms :

i) Punch tlirough , ,. ,ii

il) Impact ionization. _ir , ] . ^ (06 Marks)

Suppose Voo: l'.2Y andvt: 0.4V. Determine Vo,1in Fig.Q,'l(c) fori) V;, : 0V ; ii) Vi,= 0.6V ; iii) Vi" : 0.9V ; iv) V;n : 1.2Y. Neglect the bodyeffect.

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a. Consider the nMOS transistor in a 0.6pm process::with gate oxide thickness of 100A'. The

doping level is Nn:2, I0'' cm-3 and the nominal threshold voltage is 0.7V. The body istied to ground with a substrate contact. How much does the threshold change at room

b. Define noise margin and its significance in the design of an inverter base circuit. (07 Marks)c. With relevant""response curves explain the transmission gate:: Oqlput characteristics for

3 a. Eesciibe in detail twin tub CMOS process of fabrication.b. Derive the expressions for rise time and fall time of a CMOSc. Obtain the scaling factors for the following:

D Gate capacitance (C*)ii) Maximum operating frequency (fo).

iii) Power dissipation per unit area (Pu).

iv) Gate delay (T6).

4 a. Explain the phenomenon of charge storage and charge leakage and obtain the expression forthe holding time tmra. (10 Marks)

b. How do clocked SR and JK latch operate? Draw relevant waveforms. Draw NANDimplementation cut for both. (10 Marks)

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5 a. Calculate the Cin and Cout values of capacitance for the structure represented in Fig.Q.5(a).(08 Marks)

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b. Derive the threshold voltage Vl for 2 input NOR gate. :'.

c. Draw nMOS and CMGS version of the circuit to realize

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the following Boolean expression.

(04 Marks)

(10 Marks)(05 Marks)

(10 Marks)(10 Marks)

(10 Marks)

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6a.b.

c.

7a.b.

8a.b.

Analyze a nMOS current mirror cirouit. (05 Marks)Explain the general principle of band gap reference and hence obtain the expression for Vss.

List out advantages of CMOS over nMOS.

Mention the causes of latch up and guidelines for avoiding latch up.

c. Describe different clock distribution schemes.

Describe charge sharing and its solution in brief. (05 Marks)Show how domino CMOS logic gate can be cascaded with static CMOS logic gates and alsomention the limitation of the same. , .t (05 Marks)

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Max. Marks:100,]

(15 Marks)(05 Marks)

(10 Marks)(10 Marks)

(10 Marks)(10 Marks)

(10 Marks)(10 Marks)

(10 Marks)(10 lllarks)

(10 Marks)(10 Marks)

Time: 3 hrs.Note: Answer uny FIYE full questions.

I a. What is Moore's law? What are the limitations impose by small device geometrics.

M.Tech. Degree Examination, Dec.2013 I Jan-2O14

SOG Design

b. Compare system-on-based, system-on-chip and system-on-package.

2 a. What is short channel effect? Explain.b. What is scaling? What are its types? Explain constant voltage scaling.

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3 a. Consider an n-channel MOS process with the following parameters : substrate doping

ilicon sate doping =2x1020cm-3, gatedensity No =10'ucm'3, polysilicon gate doping de,1sit1 )r!*-".)

oxide thickness tox : 50 oxide-interface fixed gl-rarge^density N6y : 4 x 1010 "m' and

source and drain difhrsion doping density Np =,'f'6lz c*'. In addition, the channel region is

implanted with p-type impurities (impurity concentration N1 : 2x10"cm-2) to adjust the

threshold voltage. The junction depth of the source and drain diffusion regions is

x.i : 1.0 pm.Plot the variation of the zero-bias threshold voltage Vro es a function of the

channel length (assume that Vps = Vss : 0 and the threshold voltage without the channel

b. Explain : (i) Canonical SOC design (ii) Soft IP versus Hard IP. (10 Marks)

4 a. Explain waterfall versus spiial system design flow.b. Explain system design process. 'i '','.

5 a. What is flash memory? Explain NOR flash memory cell and pompare with NAND flash

memory cell. (10 Marks)

b. What is DRAM? Explain with the design. (10 Marks)

a. What is network topology? Explain.b. WMt are switching strategies? Explain packet switching and its types.

a. What are the limitations of traditional ASIC design?

b. Explain extensible processors as an alternative to RTL.

a. Explain design of timing closure: logic design issues.

b. What is routing? Explain NOC routing and its schemes.

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12EC118

(06 Marks)

(06 Marks)

(04 Marks)

(06 Marks)

(08 Marks)(06 Marks)

(06 Marks)(08 Marks)(06 Marks)

M.Tech. Degree Examination, Dec.2013 I Jan.2ol4Advanced Embedded System

Time: 3 hrs. Max. Marks:100Note: Answer any FIVEfull questions.

I a. Distinguish between Big-Endian and Little-Endian processors, with an example. , (06 Marks)

b. Explain the different types of RAM used for embedded system design. (08 Marks)

c. Describe the role of Brown-Out protection circuit. (06 Marks)

2 a. Explain,the operation of the 12C on-board communication interface; with a discussion on

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the sequenee of operations required.Discuss ZigBee network model.Explain the important operationalsystem design.

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quality attributes to be ,considered in any embedded': " (06 Marks)

a. Compare dataflow graph"(DFG) and control data flowgraph (CDFG) model. (06 Marks)

b. Design an embedded system for driver/passenger 'seat belt warning' in an automotive usingFSM model implement wait state using timer, ,, (08 Marks)

c. What is UML? What are the fundamental building blocks of UML? Explain sequence

diagram, with an example.

Discuss "super-loop" based embedded firm ware design.

c. What is "inline assemblv"?.:..::.

Explain the round ,obin pro..ss scheduling.

With a neat diagram, explain the conversion process of a high level language to machinelanguage. Also explain the advantages of high level language based development. (10 Marks)

Three processes P1,'Pi, P3 with estimated completion time 10;, J, 7 ms respectively enters theready queue togbtlier. Calculate Waiting Time (WT) and Turn Around Time (TAT) for eachprocess. Also calculate average WT and average TAT in SJF (Shortest Job First) algorithm.

c. Differentiate between threads and processes.

6 a. What is dead lock? Explain Coffman conditions favoring dead locks. (06 Marks)

b, ,, What is semaphore? Compare 'binary semaphore' and 'counting semaphore'. (06 Marks)i, Describe the role of device driver in the OS context. (08 Marks)

1 a. List down the features of simulator based debugging andi simulator firmware debugging.

also discuss the advantages of

b. Explain the 'Boundary Scan' based hardware debugging.c. Describe the role of 'Monitor program' in frmware debugging.

Write short notes on:a. RPC (Remote Procedure call).b. PLD (Programmable Logic Devices).c. Java for embedded development.d. Object-OrientedModel. (20 Marks)

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I a. Discuss the importance of verification in VLSI design. Why formal methods are a preferred(10 Marks)(05 Marks)(05 Marks)

(10 Marks)(05 Marks)(05 Marks)

way of verification?b. How verification time may be reduced?c. What is reconvergent model of verification? Give some examples.

2a.Describe1ittinqproceSS,withhelpoffollowingcode:module abc (a, b, c); ":';""tt:'t":t

input a. b:output c:reg c:

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b. Compare testing and verification.c. Briefly explain the model checking pto'Cess.

3 a. Explain the terms:i) FSM coverage"ii) Statement coverage andiii) Transition coverage.

M.Tech. Degree Examination, Dec.2013 /Jan.20l4

VLSI Design Verification

Note: Answer any FIVEfull questions.

Write a test for the following FSM. State any assumptions made.

What are code metrics? Give some examples.Discuss how ASIC verification is performed.

For the following code, write verification code.module HA (a, b, c, s)

input a, b;output c, s;

reg c, s;

xor (s, a, b);and (c, a, b);

end module

(10 Marks)(05 Marks)(05 Marks)

Highlight its statement coverage.

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b. Give schematic of a typical RC timing model of a CMOS gate.c. What is unateness of a signal? Explain with suitable waveforms.

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Give an example of timing description of an output pin inNDLM format.

Discuss the effect of IR drop in signal integrity.Give an overview of design sign off process.

Discuss various timing parameters used in a static timing analysis.::Describe setup and hold times.

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verification specification document. Describe its functionality and(10 Marks)(05 Marks)

What is the need for parasitic extraction and how it is used in back annotation? (05 Marks)

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Whflengging of variables is critical for drawing a ROBDD?Draw R@Op for the function f = abc + a'bc'+ ab'c + ab'c'

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What are Slffi;polvers?\\.tf j

Write short notes"@lury FOUR:Equivalence checkilig_. :.ti\

Event based simulators ", i,

Design rules for digital VLSI.,:'', .

Waveform skew measurements .'-'...,

Antenna effects during plasma etch. ,,,,,4:'1 ",

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, Note: 1. Answer anJ) FIVEfull questions.2. Assume suitable data wherever required.-^' '_-:*-'-'.'- *-"-*:-- -'-:--- ' --'-' :'--'. - -'r-"' -3. Mention top level blocks with input-output,poris.

1 a. Design the logic circuit shown in Fig.Q.1(a) for a night light that is lit only when the switchis ON and the light sensor shows that it is dark. The logic is to be realized using 2:1 MUXonly. If there are three lamps in the room controlled using the same logic, how do youmodify the circnit shown in Fig.Q.1(a). (10 Marks)

Time: 3 hrs.

b.

2a.

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b. Write a verilog code for l0:1 multiplexer using case statement.

3 a. Design a 4-brt unsigned combinational multiplier using 4-bit adder.b. Discuss fixed point and floating point number format with example.

M.Tech. Degree Examination, Dec.2013 I Jan.20l4Digital System Design Using Verilog

With the help of a detailed flow chart, discuss VLSI design flow. Mention the importance ofeach step in design flow. (t0 Marks)

Ink jet printer have six catridge's for different colored ink: Black, Cyan, Magenta, Yellow,Light Cyan and Light Magenta. A multibit signal in such a printer indicates selection of oneof the colors. To print tlre colors stored in different drums drivers need to be enabled foreach of the colors.i) Devise a minimal length code for the signal selection repre.senting each color.ii) Design the logic shown in Fig.Q.2(a) that can enable the'corresponding driver based

on the multibit signal.ii| If the number of colors are increased from 6 to 8, discuss the necessary changes to be

,,m6de to the multibit signal and the logic. (10 Marks)

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write verilog code for a positive edge triggered flip-flop with clock enable, positive logic

asynchronous preset and clear and both u.tiu. high and active low outputs' It is illegal for

boih preset and clear to be active together' r , (10 Marks)

Oerelop a datapath to perform coLplex multiplication of two complex numbers a and. !represented u, u : u, i lal ana b : br + jbi. The data path need to perform sequential

.o-pt.* multiplication, *ith shared ,.roui.., and register to store intermediate. results'

Mention the control signals for the sequential datapath and discuss its working p'i":.lPlt-'{10 Marks)

rDesign a 64Kx 16bit composite -:::? using 16K x .8

bit.memory component' (10 Marks)

Dev, a verilog code foi a32 x 7 bit Rom, that can store the data shown in Table Q.5(b).

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6 a. Discuss the internal architecture of'FP'GA'highlighting the functionality of each modules'.. (10 Marks)

b. Define signal integrity, discuss giound bounce issue in signal integrity and mention the(10 Marks)technique adopted to reduce ground bounce effect,

7 a. With a neat block diagr discuss the organization of a high performance embedded

computer with multipleltuses. '' ' (08 Marks)

b. Write instructions tlrat increment a 16-bit unsigned inte$er stored in memory. The address of

the least signifieanr'bye is in 12. The most significant byt€ is.il the next memoti#iijl?},:.. i

c. Discuss ttrO. l ortance of cache memory, how is cache memo,rX,used in a embedded

processof.".'' i (06Marks)

g a. Discuis physical design flow and mention the importance

ceslgn.b. ,Briehy discuss serial interface standards for I/O devices.

, o,' Develop verilog code for 4-bit counter'

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able Q.5(bAddress Content Address Content

0 00000011 00000112 00001 1 1

3 0001111"., 4 0011111

;5 0111111

6 1111111

7 1.111 1 10

8 1111100

9 111100010-f5 0000000'"1,6,31 1010101

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(10 Marks)

of floor planning in PhYsical(06 Marks)(06 Marks)(08 Marks)

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