1um cmos process baseline electrical test summary

D.K. Brown Georgia Tech Microelectronics Research Center 1

1um CMOS Process BaselineElectrical Test Summary

Georgia Tech

Microelectronics Research Center


Summary Package Outline

• Overall Summary - pages 3 - 8

• Front End Summary - pages 9 - 65– test structure description and methodology

– theoretical expected value

– measured value results

• Back End Summary - pages 66 - 110– test structure description and methodology

– theoretical expected value

– measured value results


CMOS Baseline summary

• Overall Summary of CMOS baseline– NMOS transistor yield is 30% for 3um < L < 25um. Below 3um yield falls to 20% due to

punch-thru.– PMOS transistor yield is 25% for 3um < L < 25um. Below 3um yield falls to 5% due to

punch-thru.– Many front end parameters have median values close to target however standard

deviation is high as can be seen in % pass on summary page or in the raw data throughout the presentation.

– Contact parameters are the most off target and would be the first area to address in improving the CMOS line. (Contact experiment has since been completed. See separate presentation summary for results).

• What is the baseline?– The baseline consists of 5 batches with a total of 37 wafers. Each batch was processed

individually and separately between 2001 - 2003 timeframe in the MiRC cleanroom.– Batch 6 showed the best overall performance across all parameters and notably had a

60% NMOS transistor yield and 70% PMOS transistor yield.


Front & Back End Summary

Contact parameters are the parameters which are most off target, followed by field oxide thickness, NMOS threshold voltage, and M1 serpentine Resistance.


Overall Transistor Yield

0

0.05

0.1

0.15

0.2

0.25

0.3

PM

OS

% p

ass

0 5 10 15 20 25 30

L

5

10

50

W

0.15

0.2

0.25

0.3

0.35

% p

ass

0 5 10 15 20 25 30

L

5

10

50

W

NMOS PMOS

Note that transistor yield shows a dependency on channel length. For channel lengths = 3um and greater yield is fairly constant. For channel lengths 2um and lower, the yield degrades due to punchthru.

Transistor Yield is defined as threshold voltage, saturation current, and off current all being in control limits for a given die. The % of good die on a wafer can then be calculated and averaged over all of the batches.


NMOS & PMOS Off Current (A)W=10 m, L=varying, Log10 scale

LOG

10(S

ourc

e Le

akag

e C

urre

nt)

-9

-8

-7

-6

-5

-4

-3

-2

-1

1 1.3 1.5 2 3 5 10 25

L

LOG

10(S

ourc

e Le

akag

e C

urre

nt)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

1 1.3 1.5 2 3 5 10 25

L

punch-thru

Below channel length of 3um, the OFF state current increases rapidly. The current shown is the current from the source due to the bias at the drain. Therefore it is punch-thru. (This data is from batch 6 wafer 6 and is typical of the baseline.)

NMOS PMOS


NMOS & PMOS IDS VS. VDS CURVESW/L = 10um/3um

0.00

0.25

0.50

0.75

1.00

1.25

1.50ID

S (

mA

)

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

VDS

1

2

3

4

5

6

abs(VGS)

PMOS NMOS

IDS vs. VDS curves are shown from one of the better performing batches (Batch 6 wafer 1) from a W/L = 10um/ 3um transistor.At, VDS=VGS=5V, NMOS and PMOS saturation current is 1.14mA and 0.35mA respectively.Normalizing for transistor width (W=10um), NMOS and PMOS saturation currents are 0.114mA/um and 0.035mA/um respectively.


Subthreshold Slope and Drain InducedBarrier Lowering (DIBL)

1e-8

1e-7

1e-6

1e-5

1e-4

LO

G S

CA

LE

IDS

.00 .20 .40 .60 .80 1.00

VGS

0.1

5

VDS

1e-9

1e-8

1e-7

1e-6

1e-5

abs(

ID)

-2.4 -2.2 -2 -1.8 -1.6 -1.4

VGS

-5

-0.1

VDS

PMOS NMOS

Sub-threshold curves are shown from one of the better performing batches (Batch 6 wafer 1).NMOS and PMOS sub-threshold slopes are both 150mV/decade.

NMOS and PMOS DIBL are 10mV/V and 20mV/V respectively.


Front End Parameter Summary

• Front End Parameters which are analyzed in this presentation are listed below and are covered on slides 7-61.

– N+, P+, Poly sheet resistance– Poly CD– Poly COMB leakage– Poly serpentine resistance– NMOS & PMOS gate oxide thickness– N-Well & P-Well field oxide thickness– NMOS & PMOS

• Threshold Voltage• Saturation & Linear current• Off current


N+ Sheet Resistance Structure

1

2 4 6 8 10

3 5 7 9

“wide” structure (216.5 m long x 4.5 m wide)

Van der pauw structure

There are two N+ sheet resistance measurements made. One is made on the “wide” structure, the other is made on the Van der pauw structure. A maximum current of 100mA is forced (IF) between pads 9 and 1 with an applied 1V, and a voltage drop is measured (VM) at

pads given in the table below.

IFH IFL VMH VML Calc

Wide 9 1 6 3 RS = {(VMH - VML ) / IFH} / (216.5/4.5)

Van der pauw 9 1 4 2 RS = {(VMH - VML ) / IFH} * ( / ln 2 )


N+ Sheet Resistance Theoretical Value

The N+S/D As Implant has a dose of 5.74E19/cm3 and a junction depth of 1.6um after 1 hour of annealing at 950C.

Arsenic Diffusion

1.E+13

1.E+14

1.E+15

1.E+16

1.E+17

1.E+18

1.E+19

1.E+20

1.E+21

1.E+22

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02

depth (cm)

do

se (

cm-3

)

As N+S/D (t=1sec)

As N+S/D (t=1hr)

B11 Vt (t=1sec)

B11 Vt (t=1hr)

p- substrate

p- substrate + Vt(1hr)

xj=1.6um


N+ Sheet Resistance Theoretical Value

= q(nn + pp)

for N-type material,

qnn

1/{(1.6E-19 C)(5.74E19 cm-3 )(~23* cm2/V-s)}

4.7E-3 cm

Rs = / xj

1/

For N+S/D, a 5E15, 160keV As implant is used, and a 1 hr anneal at 950C is performed

Therefore n = 5.74E19 cm-3 and xj = 1.6m

= (4.7E-3 cm) / (1.6E-4 cm)

Rs = 29.6 / �*P.M.Rousseau, et.al., ”A Model for Mobility Degradation in Highly Doped Arsenic Layers”, IEEE Transactions on Electron Devices, vol. 43, p.2025, 1996.


VD

P: N

+ sh

eet r

ho (

Ohm

s/sq

)

0

20

40

60

80

100

120

140

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7

3 4 5 6 8

wafer within batch

N+ Sheet Resistance (/) Measured ValueVan der Pauw Method, Target = 30 /

VD

P: N

+ sh

eet r

ho (

Ohm

s/sq

)

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

0 to 150 / Scale

Target = 30 / �


WID

E: N

+ sh

eet r

ho (

Ohm

s/sq

)

0

20

40

60

80

100

120

140

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M4 M7

3 4 5 6 8

wafer within batch

N+ Sheet Resistance (/) Measured Value Wide structure method, Target = 30 /

WID

E: N

+ sh

eet r

ho (

Ohm

s/sq

)

1e-1

1e+1

1e+3

1e+5

1e+7

1e+9

1e+118e+11

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

0 to 150/Scale

Target =

30 /


1e-4

1e-3

1e-2

1e-1

1e+0

1e+1

1e+2

1e+3

1e+4

1e+5

1e+6

1e+7

1e+8

1e+9

1e+10

1e+11

1e+12

1e+13

1e+14

VD

P: N

+ sh

eet r

ho (

Ohm

s/sq

)

1e-4 1e-2 1e+0 1e+2 1e+4 1e+6 1e+8 1e+10 1e+12 1e+14

WIDE: N+ sheet rho (Ohms/sq)

3

4

5

6

8

batch

N+ Sheet Resistance (/) Measured ValueVan der pauw Method compared to Wide Method

Unity line

The Van der pauw method data seems aberrant as it is several orders of magnitude higher than the Wide method and it appears to get worse with higher resistance values. It seems that the Wide method is more accurate as it produces more values closer to the theoretical target. In either case, both methods show there are many die with excessively high sheet resistance.

Theoretical

Target = 30 /


N+ Sheet Resistance (/ ) Measured ValueSummary

Mean = 47.8 / Target = 30 / Average % Pass = 63%

Using the Wide Method data, the mean of all the wafer medians is 47.8 /, excluding wafers with values marked in red.Using a LCL = 3 and UCL = 150, the average % of good die for a given wafer is 61% (no wafers excluded).


P+ Sheet Resistance Structure

1

2 4 6 8 10

3 5 7 9

“wide” structure (217 m long x 4.5 m wide)


There are two P+ sheet resistance measurements made. One is made on the “wide” structure, the other is made on the Van der pauw structure. A maximum current of 100mA is forced (IF) between pads 9 and 1 with an applied 1V, and a voltage drop is measured (VM) at

pads given in the table below.


Wide 9 1 6 3 RS = {(VMH - VML ) / IFH} / (217/4.5)

Van der pauw 9 1 4 2 RS = {(VMH - VML ) / IFH} * ( / ln 2 )


P+ Sheet Resistance Theoretical Value

= q(nn + pp)

for P-type material,

qpp

1/{(1.6E-19 C)(4.6E20 cm-3 )(~35* cm2/V-s)}

3.9E-4 cm

Rs = / xj

1/

For P+S/D, a 5E15, 30keV B11 implant is used,Therefore n = Cp = 4.6E20 cm-3 and xj = 0.100m

= (3.9E-4 cm) / (1E-5 cm)

Rs = 39 / �*G.Masetti, et.al., ”Modeling of Carrier Mobility Against Carrier Concentration in Arsenic-, Phosphorus-, and Boron-Doped Silicon”, IEEE Transactions on Electron Devices, vol. 30, p.764, 1983.


P+ Sheet Resistance (/)Van der Pauw Method, Target = 39 /

VD

P: P

+ sh

eet r

ho (

Ohm

s/sq

)

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

0 to 120 /

Scale

VD

P: P

+ sh

eet r

ho (

Ohm

s/sq

)

0102030405060708090

100110120

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Target = 39 /


P+ Sheet Resistance (/)Wide structure method, Target = 39 /

WID

E: P

+ sh

eet r

ho (

Ohm

s/sq

)

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

WID

E: P

+ sh

eet r

ho (

Ohm

s/sq

)

0102030405060708090

100110120

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

0 to 120 /

Scale

Target = 39 /


P+ Sheet Resistance (/) Measured ValueVan der pauw Method compared to Wide Method

1e-4

1e-3

1e-2

1e-1

1e+0

1e+1

1e+2

1e+3

1e+4

1e+5

1e+6

1e+7

1e+8

1e+9

1e+10

1e+11

1e+12

1e+13

1e+14

VD

P: P

+ sh

eet r

ho (

Ohm

s/sq

)

1e-4 1e-2 1e+0 1e+2 1e+4 1e+6 1e+8 1e+10 1e+12 1e+14

WIDE: P+ sheet rho (Ohms/sq)

3

4

5

6

8

batch

Unity line

Theoretical Target = 39 /



P+ Sheet Resistance (/) Measured ValueSummary

Mean = 49.3 /Target = 39 /Average % Pass = 48%

Using the Wide Method data, the mean of all the wafer medians is 49.3 /, excluding wafers with values marked in red.Using a LCL = 3 and UCL = 120, the average % of good die for a given wafer is 48% (no wafers excluded).


Poly Sheet Resistance Structure

1

2 4 6 8 10

3 5 7 9

“wide” structure (217 m long x 6 m wide)


“narrow 1 CD” structure (202.5 m long x 2 m wide)

“narrow 2 CD” structure (245 m long x 2 m wide)



Van der pauw

9 1 4 2 RS = {(VMH - VML ) / IFH} * ( / ln 2 )

Narrow 1 CD

9 1 7 5 CD = (202.5* RSWIDE) / {(VMH - VML ) / IFH}

Narrow 2 CD

9 1 10 8 CD = (245*RSWIDE) / {(VMH - VML ) / IFH}

“narrow 1 CD”

“narrow 2 CD”


Poly Sheet Resistance Theoretical Value

Rs = 49 / �


Poly Sheet Resistance (/)Van der Pauw Method, Target = 49 /

VD

P: P

L sh

eet r

ho (

Ohm

s/sq

)

1e-1

1e+1

1e+3

1e+5

1e+7

1e+9

1e+11

1e+13

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

VD

P: P

L sh

eet r

ho (

Ohm

s/sq

)

0

20

40

60

80

100

120

140

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

0 to 150 /

Scale

Target = 49 /


Poly Sheet Resistance (/)Wide structure method, Target = 49 /

WID

E: P

L sh

eet r

ho (

Ohm

s/sq

)

1e-1

1e+1

1e+3

1e+5

1e+7

1e+9

1e+11

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

WID

E: P

L sh

eet r

ho (

Ohm

s/sq

)

0

20

40

60

80

100

120

140

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

0 to 150 /

Scale

Target = 49 /


Poly Sheet Resistance (/) Measured ValueVan der pauw Method compared to Wide Method

1e-4

1e-3

1e-2

1e-1

1e+0

1e+1

1e+2

1e+3

1e+4

1e+5

1e+6

1e+7

1e+8

1e+9

1e+10

1e+11

1e+12

1e+13

VD

P: P

L sh

eet r

ho (

Ohm

s/sq

)

1e-4 1e-3 1e-2 1e-1 1e+01e+1 1e+21e+31e+4 1e+51e+61e+7 1e+81e+9 1e+11 1e+13

WIDE: PL sheet rho (Ohms/sq)

3

4

5

6

8

batchUnity line

Theoretical Target = 49 /



Poly Sheet Resistance (/) Measured ValueSummary

Mean = 44.3 /Target = 49 /Average % Pass = 53%

Using the Wide Method data, the mean of all the wafer medians is 44.3 /, excluding those wafers with values marked in red.Using a LCL = 3 and UCL = 150, the average % of good die for a given wafer is 53% (no wafers excluded).


Poly CD Narrow #1 & #2 (m)Target = 2m

CD

PLN

AR

R1

(um

)

1e-41e-3

1e-21e-1

1e+01e+1

1e+21e+3

1e+41e+51e+6

1e+7

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

3

4

5

6

8

batchC

DP

LNA

RR

2 (u

m)

1e-41e-3

1e-11e+0

1e+2

1e+41e+5

1e+71e+8

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

Full Scale


Poly CD Narrow #1 & #2 (m)Target = 2m

CD

PLN

AR

R1

(um

)

0

1

2

3

4

5

6

7

8

9

10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

3

4

5

6

8

batch

CD

PLN

AR

R2

(um

)

0

1

2

3

4

5

6

7

8

9

10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

0 to 10mScale

0 to 10mScale


0

1

2

3

4

5

6

7

8

9

10

CD

PLN

AR

R2

(um

)

0 1 2 3 4 5 6 7 8 9 10

CDPLNARR1 (um)

3

4

5

6

8

batch

Poly CD Narrow #1 & #2 comparison

Unity line

Target = 2 m

There does not appear to be a printing bias between CD Narrow 1 & 2.


Poly CD Narrow Summary

Mean = 3.4 mTarget = 2 mAverage % Pass = 56%

The mean of all the wafer medians is 3.4 m, excluding those wafers with values marked in red.Using a LCL = 0.1 m and UCL = 6 m, the average % of good die for a given wafer is 56% (no wafers excluded).


Poly COMB & Serpentine Structure

1 3 5 7 9

2 4 6 8 10

COMB & Serpentine #1 COMB & Serpentine #2

(duplicate of #1)

serpentineleftcomb

right comb

Poly CD = 2mSpace = 2mserpentine length = 6,764m


Poly COMB & SerpentineParameter Hi Lo Conditions Unit Valid Hi Valid Lo

RPLSERP1 1 6 Force 1V. Measure I. Calculate R. Compliance = 0.1A

Ohms Inf 10

IPLCOMB1U 3 1, 6 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

IPLCOMB1L 4 1, 6 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

RPLSERP2 5 10 Force 1V. Measure I. Calculate R. Compliance = 0.1A

Ohms Inf 10

IPLCOMB2U 7 5, 10 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

IPLCOMB2L 8 5, 10 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

The serpentine poly line is connected to pad 5 & 10 on structure #2 and pad 1 & 6 on structure #1. The purpose of the serpentine structure is to measure its resistance and monitor for “opens” due to incomplete patterning. The serpentine is long and winding in order to make it susceptible to lithography and etch patterning problems.

A poly comb lies on either side of the serpentine poly. The comb is electrically isolated from the serpentine line. The purpose of the comb is to measure leakage current between it and the poly serpentine and monitor for “shorts”. Shorts would be caused by remaining poly electrically connecting the comb to the poly serpentine line. On structure #2, pads 7 & 9 connect to the comb to the left of the serpentine and pad 8 connects to the comb to the right of the serpentine. On the structure #1, pad 3 connects to the comb on the left of the serpentine, and pads 2 & 4 connect to the comb on the right of the serpentine.


Poly COMB leakage (A)Target = 1E-12 A

A good die from Batch 3, Wafer 4 was compared to a bad die from Batch 5 wafer 4. The findings are presented on the next slide.

IPLC

OM

B1L

1e-15

1e-13

1e-11

1e-9

1e-7

1e-5

1e-3

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch

3

4

5

6

8

batch


Poly COMB Good vs. Bad comparison

BADGOODBatch 3, wafer 4, die (5,8) Batch 5, wafer 4, die (4,6)

Space visible betweenPoly lines.

Space not visible between Poly lines. Lines are shorted together. CONCLUSION: Polysilicon lithography either underdeveloped or underexposed. Not a problem with Etching.


Poly COMB Summary

Mean = 1.3E-12 ATarget = 1E-12 AAverage % Pass = 66%

The mean of all the wafer medians is 1.3E-12A, excluding those wafers with values marked in red.Using a LCL = 0 and UCL = 1E-9, the average % of good die for a given wafer is 66% (not excluding any wafers).


Poly Serpentine Resistance ()Target = 166 k

RP

LSE

RP

1

1e+21e+31e+41e+51e+61e+71e+81e+9

1e+101e+111e+121e+131e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch

Poly CD = 2mserpentine length = 6,764m

6,764m /2m = 3,382 �

3,382 * (49 � /) = 166k

Target = 166k


Poly Serpentine Resistance () Summary

Median = 184 kTarget = 166 kAverage % Pass = 33%

The median of all the wafer medians is 184 k, excluding wafers whose values are marked in red.Using a LCL = 16 k and UCL = 497 k , the average % of good die for a given wafer is 47% (not excluding any wafers).


Gate & Field Oxide Structure

1 3 5 7 9

2 4 6 8 10

Gate S D Well Calc

NMOS Gate Oxide 5 3 4 10 Capacitance is measured at +/-5VDC (inversion/accumulation) with 25mVAC @ 100kHz. Thickness is calculated using C=A/t.

P-Well Field Oxide 6 7 8 10 “

PMOS Gate Oxide* 5 3 4 10 “

N-Well Field Oxide* 6 7 8 10 “

*The PMOS Gate & N-Well Field structures are in a row adjacent to the row shown above with an identical layout except for it is in an N-Well region and the S/D diffusion is P+.

100 m x 100 m


NMOS Inversion Gate Oxide Thickness (Å)Target = 300 Å

TIN

GO

X

1e+2

1e+36e+2

4e+2

2e+2

1e+46e+3

4e+3

2e+3

2e+4

3e+4

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9

3 4 5 6

wafer within batch

3

4

5

6

batch

TIN

GO

X

200

300

400

500

600

700

800

900

1000

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9

3 4 5 6

wafer within batch

Full Scale

200 to 1000 ÅScale


NMOS Inversion Gate Oxide Thickness Summary

Mean = 320 ÅTarget = 300 ÅAverage % Pass = 37%

The mean of all the wafer medians is 320 Å, excluding the wafers with values in red.Using a LCL = 200 Å and UCL = 400 Å, the average % of good die for a given wafer is 37%, not excluding any wafers.


PMOS Inversion Gate Oxide Thickness (Å)Target = 300 Å

TIP

GO

X

1e+2

1e+36e+2

4e+2

2e+2

1e+46e+3

4e+3

2e+3

2e+4

3e+4

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9

3 4 5 6

wafer within batch

TIP

GO

X

200

300

400

500

600

700

800

900

1000

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9

3 4 5 6

wafer within batch

Full Scale

200 to 1000 ÅScale


PMOS Inversion Gate Oxide Thickness Summary




N and P-Well Accumulation Field Oxide Thickness (Å)Target = 6500 Å

TAN

FO

X

1e+3

1e+4

7e+3

5e+3

3e+3

2e+3

2e+4

3e+4

4e+4

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9

3 4 5 6

wafer within batch

P-Well

N-Well

TAP

FO

X

1e+3

1e+46e+3

4e+3

2e+3

1e+5

6e+4

4e+4

2e+4

2e+5

11 13 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9

3 4 5 6

wafer within batch

6500 ÅTarget

6500 ÅTarget


N-Well Accumulation Field Oxide Thickness Summary




P-Well Accumulation Field Oxide Thickness Summary




Transistor Structure

1 3 5 7 9

2 4 6 8 10

All NMOS & PMOS transistors have the same basic layout as above for W= 5, 10, & 50 um.

Each row contains a unique L. Shown above is L = 25m. The variations of L are 1, 1.3, 1.5, 2, 3, 5, 10, 25 m.

So there are 2 (NMOS/PMOS) x 8(various L) = 16 rows. In each row there are 3 transistors, so there are 3 x 16 = 48 unique transistors.


NMOS & PMOS Threshold Voltage (V)W=5 m, L=varying*

NM

OS

Vt

-3

-2

-1

0

1

2

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

PM

OS

Vt

-4

-3

-2

-1

0

1

2

3

4

3 11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.5 2 3 25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

1

1

24 25 3 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

*For each wafer L varies from left to right in the following order: 1, 1.3, 1.5, 2, 3, 5, 10, 25 m.



NM

OS

Vt

-3

-2

-1

0

1

2

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3 2 3 5 10

25 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

PM

OS

Vt

-4

-3

-2

-1

0

1

2

3

4

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch




NM

OS

Vt

-3

-2

-1

0

1

2

11

.31

.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3 2 3 10

25 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25 1

1.3

1.5 2 3 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

PM

OS

Vt

-4

-3

-2

-1

0

1

2

3

4

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3 2 3 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch



NMOS Vt value and % Pass by Channel Width/Length

-0.2

-0.1

0

0.1

0.2

0.3

0.4

NM

OS

Vt

Med

ian

valu

e

0 5 10 15 20 25 30

L

5

10

50

W

0.4

0.45

0.5

0.55

0.6

0.65

0.7

NM

OS

Vt

% p

ass

0 5 10 15 20 25 30

L

5

10

50

W

Yield degrades below L=3m

W=50m is offset towards 0

Mean = 147 mVTarget = 0.7 VAverage % Pass = 55%

The mean of all the wafer medians is 147 mV, excluding the wafers with values in red.Using a LCL = 0V and UCL = 3V, the average % of good die for a given wafer is 55%, not excluding any wafers.


PMOS Vt value and % Pass by Channel Width/Length

-1.2

-1

-0.8

-0.6

-0.4

-0.2

PM

OS

Vt

Med

ian

valu

e

0 5 10 15 20 25 30

L

5

10

50

W

0.35

0.4

0.45

0.5

0.55

0.6

0.65

PM

OS

Vt

% p

ass

0 5 10 15 20 25 30

L

5

10

50

W

Yield degrades below L=3m

Mean = -608 mVTarget = -0.7VAverage % Pass = 48%

The mean of all the wafer medians is -608 mV.Using a LCL = -3V and UCL = 0V, the average % of good die for a given wafer is 48%. No wafers were excluded in either calculation.


NMOS & PMOS Saturation Current (A)W=5 m, L=varying*, Log10 scale

NM

OS

ID

SA

T

-12-11-10-9-8-7-6-5-4-3-2-10

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

PM

OS

ID

SA

T

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch



NMOS & PMOS Saturation Current (A) W=10 m, L=varying*, Log10 scale

NM

OS

ID

SA

T

-14

-12

-10

-8

-6

-4

-2

0

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

3

4

5

6

8

batch

PM

OS

ID

SA

T

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch



NMOS & PMOS Saturation Current (A) W=50 m, L=varying*, Log10 scale

NM

OS

ID

SA

T

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch

PM

OS

ID

SA

T

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 7 8 wafer

3 4 5 6 8 batch



NMOS IDsat value and % Pass by Channel Width/Length

-5

-4.5

-4

-3.5

-3

-2.5

NM

OS

Med

ian(

Log(

abs(

IDsa

t))

0 5 10 15 20 25 30

L

5

10

50

W

0.7

0.75

0.8

0.85

0.9

NM

OS

% p

ass

0 5 10 15 20 25 30

L 2

5

10

50

W

A % Pass was calculated using a LCL of 1E-6A.


PMOS IDsat value and % Pass by Channel Width/Length

-4.5

-4

-3.5

-3

-2.5

-2

PM

OS

Med

ian(

Log(

abs(

IDsa

t))

0 5 10 15 20 25 30

L

5

10

50

W

0.75

0.8

0.85

0.9

PM

OS

% p

ass

0 5 10 15 20 25 30

L 2

5

10

50

W

A % Pass was calculated using a LCL of 1E-6A.


NMOS & PMOS Off Current (A)W=5 m, L=varying*, Log10 scale

NM

OS

Dra

in L

ea

kag

e

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 wafer

3 4 5 6 8 batch

PM

OS

Dra

in L

eaka

ge

-14

-12

-10

-8

-6

-4

-2

0

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 wafer

3 4 5 6 8 batch

3

4

5

6

8

batch




NM

OS

Dra

in L

ea

kag

e

-12-11-10-9-8-7-6-5-4-3-2-10

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 wafer

3 4 5 6 8 batch

PM

OS

Dra

in L

ea

kag

e

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 wafer

3 4 5 6 8 batch




NM

OS

Dra

in L

ea

kag

e

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 wafer

3 4 5 6 8 batch

PM

OS

Dra

in L

ea

kag

e

-13

-11

-9

-7

-5

-3

-1

11

.31

.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25 1

1.3

1.5 2 3 5 10

25

L

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 6 7 8 wafer

3 4 5 6 8 batch



NMOS IOFF value and % Pass by Channel Width/Length

-10

-9

-8

-7

-6

-5

-4

-3

Med

ian(

Log1

0(ab

s(LD

)))

0 5 10 15 20 25 30

L

5

10

50

W

0.4

0.5

0.6

0.7

0.8

NM

OS

%p

ass

0 5 10 15 20 25 30

L

5

10

50

W

A % Pass was calculated using an UCL of 1E-6A.


PMOS IOFF value and % Pass by Channel Width/Length

-7

-6

-5

-4

-3

-2

Med

ian(

Log1

0(ab

s(LD

)))

0 5 10 15 20 25 30

L

5

10

50

W

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

%pa

ss

0 5 10 15 20 25 30

L

5

10

50

W

A % Pass was calculated using an UCL of 1E-6A.


Overall Transistor Yield

0

0.05

0.1

0.15

0.2

0.25

0.3

PM

OS

% p

ass

0 5 10 15 20 25 30

L

5

10

50

W

0.15

0.2

0.25

0.3

0.35

% p

ass

0 5 10 15 20 25 30

L

5

10

50

W

NMOS PMOS

Overall Transistor Yield was calculated by requiring each die to pass the control limits for Vt, Idsat, and Ioff simultaneously.


W=10m Transistor Yield by Batch

NMOS

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

%pa

ss

0 5 10 15 20 25

L

3

4

5

6

8

batch

PMOS

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

%pa

ss

0 5 10 15 20 25

L

3

4

5

6

8

batch


Back End Parameter Summary

• Back End Parameters which are analyzed in this presentation are listed below and are covered on slides 63-106.

– N+, P+, Poly, single contact resistance

– N+, P+, Poly contact chain resistance

– Single VIA1 and chain VIA1 resistance

– M1 and M2 sheet resistance and CD’s

– M1 comb leakage and serpentine resistance


N+ Contact Resistance Structure

1 3 5 7 9

2 4 6 8 10


N+ Contact Resistance 1

9 1 3 2 R = (VMH - VML ) / IFH


9 1 5 4 R = (VMH - VML ) / IFH


9 1 7 6 R = (VMH - VML ) / IFH


9 1 10 8 R = (VMH - VML ) / IFH

3m x 3m contact


N+/P+ Contact Resistance Theoretical Value

DB NBc e

TqA

kR /)

**(

3

2*4**

h

kqmA

)(

)()(

2

2

cmA

cmRr cc

using ND=6E20cm-3 and B=0.72*

281.1 cmERc 289 cmEA

Then rc = 0.1 is the target N+ and Poly contact resistance. (Since Poly has

similar sheet resistance as N+, the Schottky Barrier height and doping is assumed to be close to the same and therefore the Poly Contact resistance is also assumed to be close to the same.)

*W.R.Runyan, K.E.Bean, Semiconductor Integrated Circuit Processing Technology, 1st edition, p.522-524, 1990.

using NA=4.6E20cm-3 and B=0.58*

Then rc = 1 is the target P+ contact resistance.


N+ Contact Resistance ()Target = 0.1

RN

+CO

N1

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

N+ Contact Resistance is very high.


N+ Contact Resistance Value and % Pass

Mean = 2E9 Target = 0.1 Average % Pass = 8%

The mean of all the wafer medians is 2E9 .Using a LCL = 0.001 and UCL = 100, the average % of good die for a given wafer is 8%.


N+ Contact Chain Structure

1 3 5 7 9

2 4 6 8 10

VH, IH VL, IL Calc

N+ Contact Chain Resistance 1 1 2 R = (VH - VL ) / IH





104 contacts

There are 104 contacts, 100.2 squares of N+ diffusion, and 77.8 squares of M1. Using the theoretical values of N+ contact resistance, N+ sheet resistance and M1 sheet resistance found elsewhere in this document the theoretical target value for N+ contact chain is 5.0k.


N+ Contact Chain Resistance ()Target = 5k

RN

+CC

1

1e+1

1e+2

1e+3

1e+4

1e+5

1e+6

1e+7

1e+8

1e+9

1e+10

1e+117e+11

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch

3

4

5

6

8

batch


N+ Contact Chain Resistance Value and % Pass

Mean = 6E10 Target = 5 kAverage % Pass = 28%

The mean of all the wafer medians is 6E10 .Using a LCL = 1k and UCL = 100k , the average % of good die for a given wafer is 28%.


P+ Contact Resistance Structure

1 3 5 7 9

2 4 6 8 10


P+ Contact Resistance 1

9 1 3 2 R = (VMH - VML ) / IFH


9 1 5 4 R = (VMH - VML ) / IFH


9 1 7 6 R = (VMH - VML ) / IFH


9 1 10 8 R = (VMH - VML ) / IFH


P+ Contact Resistance ()Target = 1

P+ Contact Resistance is very high.

RP

+CO

N1

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch


P+ Contact Resistance Value & % Pass

Mean = 6E8 Target = 1Average % Pass = 15%

The mean of all the wafer medians is 6E8 .Using a LCL = 0.1 and UCL = 100 , the average % of good die for a given wafer is 15%.


P+ Contact Chain Structure

1 3 5 7 9

2 4 6 8 10

VH, IH VL, IL Calc

P+ Contact Chain Resistance 1 1 2 R = (VH - VL ) / IH





There are 104 contacts, 100.2 squares of P+ diffusion, and 77.8 squares of M1. Using the theoretical values of P+ contact resistance, P+ sheet resistance and M1 sheet resistance found elsewhere in this document the theoretical target value for N+ contact chain is 4.0k.


P+ Contact Chain Resistance ()Target = 4 k

RP

+CC

1

1e+1

1e+2

1e+3

1e+4

1e+5

1e+6

1e+7

1e+8

1e+9

1e+10

1e+116e+11

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch


P+ Contact Chain Resistance Value and % Pass

Mean = 5.3E10 Target = 4 kAverage % Pass = 52%

The mean of all the wafer medians is 5E10 .Using a LCL = 1k and UCL = 100k , the average % of good die for a given wafer is 52%.


Poly Contact Resistance Structure

1 3 5 7 9

2 4 6 8 10


Poly Contact Resistance 1

9 1 3 2 R = (VMH - VML ) / IFH


9 1 5 4 R = (VMH - VML ) / IFH


9 1 7 6 R = (VMH - VML ) / IFH


9 1 10 8 R = (VMH - VML ) / IFH


Poly Contact Resistance ()Target = 0.1

RP

LCO

N1

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

3

4

5

6

8

batch


Poly Contact Resistance Value and % Pass

Mean = 2.4E10 Target = 0.1Average % Pass = 11%

The mean of all the wafer medians is 2.4E10 .Using a LCL = 0.1 and UCL = 100 , the average % of good die for a given wafer is 11%.


Poly Contact Chain Structure

1 3 5 7 9

2 4 6 8 10

VH, IH VL, IL Calc

Poly Contact Chain Resistance 1 1 2 R = (VH - VL ) / IH





There are 104 contacts, 100.2 squares of Poly, and 77.8 squares of M1. Using the theoretical values of Poly contact resistance, Poly sheet resistance and M1 sheet resistance found elsewhere in this document the theoretical target value for Poly contact chain is 4.9k.


Poly Contact Chain Resistance ()Target = 4.9 k

RP

LCC

1

1e+11e+21e+31e+41e+51e+61e+71e+81e+9

1e+101e+111e+12

7e+12

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch


Poly Contact Chain Resistance Value and % Pass

Mean = 1.3E11 Target = 4.9kAverage % Pass = 22%

The mean of all the wafer medians is 1.3E11 .Using a LCL = 1k and UCL = 100 k, the average % of good die for a given wafer is 22%.


M1 Sheet Resistance Structure

1 3 5 7 9

2 4 6 8 10



“narrow 1 CD”

“narrow 2 CD”



Van der pauw

9 1 4 2 RS = {(VMH - VML ) / IFH} * ( / ln 2 )

Narrow 1 CD

9 1 7 5 CD = (203* RSWIDE) / {(VMH - VML ) / IFH}

Narrow 2 CD





M1 & M2 Sheet Resistance Theoretical Value

3.4E-6 cm*

Rs = / xj

= (3.4E-6 cm) / (6000 E-8 cm)

Rs = 56.7 m/ for M1�

*W.R.Runyan, K.E.Bean, Semiconductor Integrated Circuit Processing Technology, 1st edition, p.535, 1990.

For Aluminum with 1% Silicon, the resistivity is

for M2, xj = 8000Åso Rs = 42.5 m/ �


M1 Sheet Resistance (m/ �)Van der Pauw Method, Target = 56.7 m/�

VD

P: M

1 sh

eet r

ho (

mO

hms/

sq)

30

40

50

60

70

80

90

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

VD

P: M

1 sh

eet r

ho (

mO

hms/

sq)

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale

30 to 90 m/ �Scale


M1 Sheet Resistance (m/ �)Wide Structure Method, Target = 56.7 m/�

WID

E: M

1 sh

eet r

ho (

mO

hms/

sq)

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

WID

E: M

1 sh

eet r

ho (

mO

hms/

sq)

30

40

50

60

70

80

90

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale



M1 VDP Sheet Resistance Value and % Pass

Mean = 57.2 m/�Target = 56.7 m/�Average % Pass = 70%

The mean of all the wafer medians is 57.2 m/, �excluding the wafers with values in red.Using a LCL = 10 m/ � and UCL = 100 m/ � , the average % of good die for a given wafer is 70%, not excluding any wafers.


M1 CD Narrow #1 & #2 (m)Target = 3m

CD

M1N

AR

R1

(um

)

0

1

2

3

4

5

6

7

8

9

10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

CD

M1N

AR

R2

(um

)

0

1

2

3

4

5

6

7

8

9

10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch


M1 CD Value and % Pass

Mean = 4.1 mTarget = 3 m Average % Pass = 47%

The mean of all the wafer medians is 4.1 m, excluding the wafers with values in red.Using a LCL = 1 m and UCL = 5.5 m , the average % of good die for a given wafer is 47%, not excluding any wafers.


M1 COMB/SERP Structure

1 3 5 7 9

2 4 6 8 10

serpentineleftcomb

right comb

COMB & Serpentine #1

COMB & Serpentine #2 (duplicate of #1)

M1 CD = 3mSpace = 3mserpentine length = 4,504m


M1 COMB/SERP

Parameter Hi Lo Conditions Unit Valid Hi Valid Lo

RM1SERP1 1 6 Force 1V. Measure I. Calculate R. Compliance = 0.1A

Ohms Inf 10

IM1COMB1U 3 1, 6 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

IM1COMB1L 4 1, 6 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

RM1SERP2 5 10 Force 1V. Measure I. Calculate R. Compliance = 0.1A

Ohms Inf 10

IM1COMB2U 7 5, 10 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12

IM1COMB2L 8 5, 10 Force 1V. Measure I. Compliance = 0.1A

Amps 0.1 1E-12


M1 COMB leakage (A) Target = 1E-12A

IM1C

OM

B1L

1e-15

1e-13

1e-11

1e-9

1e-7

1e-5

1e-3

1e-1

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch


M1 COMB leakage Value and % Pass

Mean = 1E-12ATarget = 1E-12AAverage % Pass = 82%

The median of all the wafer medians is 1E-12A.Using a LCL = 0 and UCL = 1E-9, the average % of good die for a given wafer is 82%.


M1 Serpentine Resistance ()Target = 85

RM

1SE

RP

1

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch

RM

1SE

RP

1

10

30

50

70

90

110

130

150

170

190

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch

Full Scale

10 to 200 Scale


M1 Serpentine Resistance Value and %Pass

Mean = 200 Target = 85 Average % Pass = 63%

The mean of all the wafer medians is 200 , excluding the wafers with values in red.Using a LCL = 10 and UCL = 450 , the average % of good die for a given wafer is 63%, not excluding any wafers.


M2 Sheet Resistance Structure

1 3 5 7 9

2 4 6 8 10



“narrow 1 CD”

“narrow 2 CD”





Van der pauw

9 1 4 2 RS = {(VMH - VML ) / IFH} * ( / ln 2 )

Narrow 1 CD

9 1 7 5 CD = (203* RSWIDE) / {(VMH - VML ) / IFH}

Narrow 2 CD



M2 Sheet Resistance (m/ �)Van der Pauw Method, Target = 42.5 m/�

VD

P: M

2 sh

eet r

ho (

mO

hms/

sq)

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

1e+16

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

VD

P: M

2 sh

eet r

ho (

mO

hms/

sq)

30

40

50

60

70

80

90

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale


Batch 4 & 5 did not receive M2 processing



M2 Sheet Resistance (m/ �)Wide Structure Method, Target = 42.5 m/�

WID

E: M

2 sh

eet r

ho (

mO

hms/

sq)

1e-4

1e-2

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

WID

E: M

2 sh

eet r

ho (

mO

hms/

sq)

30

40

50

60

70

80

90

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

Full Scale





M2 VDP Sheet Resistance Value and % Pass

Mean = 45.8 m/ �Target = 42.5 m/ �Average % Pass = 92%

The mean of all the wafer medians is 45.8 m/, �excluding batch 4 &5.Using a LCL = 10 m/ � and UCL = 100 m/ �, the average % of good die for a given wafer is 92%, excluding batch 4 &5.



M2 CD Narrow #1 & #2 (m)Target = 3m

CD

M2N

AR

R1

(um

)

0

1

2

3

4

5

6

7

8

9

10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

CD

M2N

AR

R2

(um

)

0

1

2

3

4

5

6

7

8

9

10

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch




M2 CD Narrow #1 Value and % Pass

Mean = 3.0 m

Target = 3 m

Average % Pass = 54%

The mean of all the wafer medians is 3.0 m, excluding the wafers with values in red.Using a LCL = 1 m and UCL = 5.5 m , the average % of good die for a given wafer is 54%, excluding batch 4 & 5 only.



M2 to M1 Via Structure

1 3 5 7 9

2 4 6 8 10


VIA Resistance 1

9 1 3 2 R = (VMH - VML ) / IFH

VIA Resistance 2

9 1 5 4 R = (VMH - VML ) / IFH

VIA Resistance 3

9 1 7 6 R = (VMH - VML ) / IFH

VIA Resistance 4

9 1 10 8 R = (VMH - VML ) / IFH

M2 M1


M2 to M1 Via Resistance ()Target = 0.1

RM

1CO

N1

1e-1

1e+1

1e+3

1e+5

1e+7

1e+9

1e+11

1e+13

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch

3

4

5

6

8

batch


RM

1CO

N1

0

5

10

15

20

11 13 16 24 25 3 4 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M2 M7

3 4 5 6 8

wafer within batch


Full Scale

0 to 20 Scale


M2 to M1 Via Resistance ()

Mean = 13.7 Target = 0.1 Average % Pass = 53%

The mean of all the wafer medians is 13.7 , excluding the wafers with values in red.Using a LCL = 0.1 and UCL = 100 , the average % of good die for a given wafer is 53%, excluding batch 4 & 5 only.



M2 to M1 Via Chain Resistance Structure

1 3 5 7 9

2 4 6 8 10

VH, IH VL, IL Calc

Via Chain Resistance 1 1 2 R = (VH - VL ) / IH





There are 104 VIA’s, 77.8 squares of M1, and 104 squares of M2. Using the theoretical values of VIA resistance, M1 & M2 sheet resistance found elsewhere in this document the theoretical target value for VIA chain is 19.


M2 to M1 Via Chain Resistance ()Target = 19

RM

1CC

1

1e+0

1e+2

1e+4

1e+6

1e+8

1e+10

1e+12

1e+14

11 24 25 3 10 16 21 4 6 10 11 2 3 4 5 6 7 9 1 12 2 5 6 7 8 9 1 2 3 6 7 8 M7

3 4 5 6 8

wafer within batch


M2 to M1 Via Chain Resistance Value and % Pass

Mean = 4E11 Target = 19 Average % Pass = 0.4%

The mean of all the wafer medians is 13.7 , excluding the wafers with values in red.Using a LCL = 0.1 and UCL = 100 , the average % of good die for a given wafer is 53%, excluding batch 4 & 5 only.

1um cmos process baseline electrical test summary

Documents

um transistor

pmos transistor yield

um yield falls

greater yield

pmos dibl

end parameters

nmos threshold voltage

pmos saturation currents