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1. Given the following Verilog code, what value of "a" is displayed?

always @(clk)

egin

a ! #

a $ ! 1#

%display(a)#end

&nswer

Verilog used four'level deep ueue for the current siulation tie*

1. &ctive events (locking stateents).

+. nactive events (- delays, etc).

. /on'locking assign updates (non'locking stateents).

0. onitor 2vents (%display, %onitor).

3o %display(a)# displays .

+. 4hat is the difference etween a ! -1 # and -1 a ! # ?&nswer

n a ! -1 # current value of "" will e assigned to "a" after 1 units of tie (like transport delay). n -1 a

! # the siulator will e5ecute a ! # after 1 units of tie (like inertial delay).

. 6et "a" e a it reg value.initialegina $ ! 711#a ! -8 7#

a $ ! -1 7111#a $ ! - 711#a ! -+ 71#a $ ! -8 711#end4hat will e the value of "a" at tie ,8,1,... units till 0 units of tie?&nswer

' 11

8 '

1 '

18 ' 111

+ ' 111+8 ' 1

' 11

8 ' 11

0 ' 11

(9his helps in understanding the concepts of locking and non'locking stateents).

0. 4rite a verilog code to swap contents of two registers with and without using a teporary register.&nswer

http://showhide%28%27div1%27%29/http://showhide%28%27div2%27%29/http://showhide%28%27div3%27%29/http://showhide%28%27div4%27%29/http://showhide%28%27div2%27%29/http://showhide%28%27div3%27%29/http://showhide%28%27div4%27%29/http://showhide%28%27div1%27%29/

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4ith a teporary register*

always @ (posedge clock)

egin

tep:reg!#

!a#a!tep:reg#

end

4ithout using a teporary register*

always @ (posedge clock)

egin

a $ ! #

$ ! a#

end

8. 4hat is the difference etween*c ! check ? a * # andif(check) c ! a#else c ! #&nswer

9he ?* erges answers if the condition is 757, so if check ! 175, a!+71, and c!+711, then c ! +715. 4here

as if else treats 5 or ; as false case, so always c ! .

1 ps signify in a verilog code?&nswer

t eans the unit of tie is 1ns and the precision>accuracy will e up to 1ps.

. what is the use of defpara?&nswer

Aaraeter values can e changed in any odule instance in the design with the keyword defpara.

B. 4hat is a sensitivity list?&nswer

&ll input signals that cause a re'coputation of out to occur ust go into the always @(...), which as a group

are called as sensitivity list.

C. n a pure coinational circuit is it necessary to ention all the inputs in sensitivity list? f yes, why? fnot, why?&nswer

Des, in a coinational circuit, if an input at one of the input terinals changes then the gate re'coputes

its output. Eence to ake it happen in our design, it is ust to put all input signals in sensitivity list.

1. Eow to generate sine wave using verilog coding style?&nswer

http://showhide%28%27div5%27%29/http://showhide%28%27div6%27%29/http://showhide%28%27div7%27%29/http://showhide%28%27div8%27%29/http://showhide%28%27div9%27%29/http://showhide%28%27div10%27%29/http://showhide%28%27div5%27%29/http://showhide%28%27div6%27%29/http://showhide%28%27div7%27%29/http://showhide%28%27div8%27%29/http://showhide%28%27div9%27%29/http://showhide%28%27div10%27%29/

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9he easiest and efficient way to generate sine wave is using FHIFalgorith.

http://en.wikipedia.org/wiki/CORDIChttp://en.wikipedia.org/wiki/CORDIChttp://en.wikipedia.org/wiki/CORDIC