2. cmos scaling & limitations
TRANSCRIPT
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S Kanjanachu2. CMOS Scaling & limitations uchai
gRationale for scaling:Economics: $/chipEngineering: speed, performanceProblems: S/D, Gate, Oxide, Interconnection…
Scaling: DefinitionScaling: Overview
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S Kanjanachu
Scaling: Exampleuchai
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S Kanjanachu
Scaling: Constant Field vs Constant Voltageuchai
ttox
Lg
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VDD
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S Kanjanachu
Scaling: Short-Channel EffectsuchaiShort−Channel Effect (SCE)Long−Channel
V
Scaling VDD and VT
VDD
2102-5844 Intro to NanoelV 0 3 V
VDD < 0.9 V
lectronics
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ITRS2011: Table PIDS2
VT ~ 0.3 V
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S Kanjanachu
ITRS2011: Table PIDS2Scaling: ID(sat) and CV/I
uchai
V
VDD
VT
ITRS2011: Table FEP2
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2000
2500
3000
m) 0 7
0.80.91
(ps)
Scaling: Pros Scaling: Cons ITRS2011: Table FEP2
4 Intro to Nanoel
1000
1500
2000
Id,s
at (
A/
m
0 20.30.40.50.60.7
ntrin
sic
dela
y
lectronics
5
0
500
2005 2006 2007 2008 2009 2010 2011 201200.10.2 In
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S Kanjanachu
Planar MOSFETuchai1. poly-Si/SiON 2. HKMG
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Objectives: to understand
-why we scaling Si MOSFET cannot continue forever 4 Intro to Nanoel
why we scaling Si MOSFET cannot continue forever
-where the problems are
-how to deal with the problems
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S Kanjanachu
Scaling: current state-of-the-art, HKMGuchaiITRS 2011: Table FEP2
OxideHK
Gate
h
Channel
MG
sion
/ Tr
ench
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/ Ex
tens
4 Intro to NanoelSo
urce
/ D
rlectronics
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ITRS 2011: Table FEP12[F] = Xj/2
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S KanjanachuMaterial & process limits: uchaiMaterial & process limits:
1. Gate insulators2 Gate electrodes
Gate StackHK
MG 2. Gate electrodes3. S/D Junctions
4. S/D Contacts
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4 Intro to NanoelThe thickness of the SiO2 insulation on the transistor’s gate has scaled from about 100 nm down to 1.2 nm (5 atoms) on lectronics
8
state-of-the art microprocessors. The rate at which the thickness decreased was steady for years but started to slow at the 90-nm generation, which went into production in 2003. It was then that the oxide hit its five-atom limit. The insulator thickness shrank no further from the 90-nm to the 65-nm generation still common today. Source: IEEE Spectrum Oct 2007 p.25
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S Kanjanachuuchai
Equivalent oxide thickness (EOT), scaling down…
ITRS 2011: Table FEP2
Q) How is gate insulator (SiO2) formed?
A) Thermal oxidation
Equivalent oxide thickness (EOT), scaling down…
Physical oxide thickness, reached 1.2-nm limit (5 atoms)
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S Kanjanachuuchai
i
si
si
CQV
VV
;
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coupling – leakage(thin) (thick) fundamental tradeoff
gain – power
tunnelling current density between(S/D gate) >> (channel gate)
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ITRS 2011: Table FEP2uchai
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Scaling results in thinner oxide(). Although this increases the gate-to-channel control (or co pling gain) the o erlap of 's increase
Q) How to have thinner oxide while preventing Jox increase?
A) change gate insulator material(s) that can lectronics
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coupling, gain), the overlap of 's increase gate leakage Jox ().
) g g ( )give thinner "equivalent" oxide thickness (EOT) but is "physically" thick enough to prevent 's overlap.
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S Kanjanachu
Equivalent oxide thickness (EOT)uchai
quantum confinement effectsd oxide thickness poly-Si depletion effects
EOT:
- the actual oxide thickness (d) and- the surrounding thickness ( + ) where
i d l t d ( ff ti l
0.8(ข)
0.8(ข)t l t
carriers are depleted (effectively an insulator).
d 0.5
0.6
0.7
(nm
)
(ข)
0.5
0.6
0.7
(nm
)
(ข)
metal gate =0
0 1
0.2
0.3
0.4
(
0 1
0.2
0.3
0.4
(
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0
0.1
2005 2006 2007 2008 2009 2010 2011 20120
0.1
2005 2006 2007 2008 2009 2010 2011 2012
poly gate (nm)÷10
4 Intro to Nanoel
poly gate doping (cm-3)
(nm)
1 1020 0.51.5 1020 0.4 lectronics
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.5 0 0.3 1020 0.3
source: ITRS 2007 Tab. FEP4a
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S Kanjanachuinv)(2
EOT: adding high-k dielectricuchai
A
ss
qNinvW )(2
max
The addition of a high-k dielectric results in increased gate-to-channel coupling. Thus it can be thick (prevent 's overlap), yet the coupling is good.
We needed a gate insulator that was thick enough to keep electrons from tunneling through it and yet permeable enough to let the gate’s electric field into
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the channel so that it could turn on the transistor. In other words, the material had to be physically thickbut electrically thin. (IEEE Spectrum Oct 2007 p.26)
4 Intro to Nanoellectronics
13effective equivalent (physical) oxide thickness ≠ effective equivalent (electrical) oxide thickness
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S Kanjanachu
0.5nm
2nmExample: SiON
Fi d EOT( h i l)
uchai
9.3r5.7r
nmT physeffox 5.12
5.79.35.0,
Find EOT(physical):
Find EOT(electrical): approx = 1.5 + + Find EOT(electrical): exact
Since the tunneling probability T
ox
B tqmT 2
*22exp
therefore:
21.25.01.31.3
t
ttt nitnit
oxox
effectiveoxox
BBB
therefore:The SiON insulator is physically 2.5nm thick but its couplingproperty is the same as SiO2 which is 1.5nm thick and leakagecurrent is the same as SiO2 which is 2.15nm thick.
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ical)EOT(electrnm 15.2 t
ITRS2011, Table PIDS2
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The benefits of hi-kuchai
Determine EOT of SiONa)0.25nm SiO2 + 1.5nm Si3N4b)0.50nm SiO2 + 2.0nm Si3N42 3 4
Answers:a) 1 nma) 1 nmb) 1.5 nm
From Leakage@ 0.5V, 1-nm EOTSiO2 =SiON =
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SiON =
Leakage@ 1.5V, 1.5-nm EOTSiO2 = 4 Intro to N
anoel
SiON =
Scaling requires that the gate insulator be lectronics
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changed from SiO2 to SiON,
and then SiON to HK
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Q) Are there other insulating materials that can replace SiO2 or SiON?A) Yes, but alternative gate insulator material must have the right "electrical" properties: It must provide low leakage by suppressing uchai
It must provide low leakage by suppressing (a) direct tunnelling (high r) and(b) thermionic emission (high EC and EV). EG ~ 4-5 eV with E > 1 eV.
Let's look at J in more detailLet s look at Jg in more detail...
fundamental conflict:
rgE
1
(b)
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(a)
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S Kanjanachuuchai
The transmission coefficient for a particle tunneling through a single potential barrier is:
(a) http://en.wikipedia.org/wiki/Quantum_tunnelling
( )(b)
the emitted current density J (A/m2) is related to temperature T b th ti :
(b) http://en.wikipedia.org/wiki/Thermionic_emission (a)
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T by the equation:
where T is the metal temperature in kelvin, W is the work function of the metal k is the Bolt mann constant 4 Intro to N
anoel
function of the metal, k is the Boltzmann constant.
lectronics
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S Kanjanachuuchai
(a) (b)ideal
(ก)(ก)
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(ข)(ข)
4 Intro to NanoelIs Ta O a suitable gate oxide material?
(r or k)
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Is Ta2O5 a suitable gate oxide material?
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...in addition, it must have the right "structural" properties: It must be able to maintain contact with Si and provide low interface state density.
uchai2102-5844 Intro to N
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Is TiO2 a suitable gate oxide material?
TDDB
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Possible SiO2 gate insulator "replacement":uchai
currentSiON
Intel 65 nmEOT = 1.2 nm
F1currentIntel 45 nm
EOT = 1.0 nm
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O .0
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F2
F3 lectronics
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S Kanjanachu
Roadmap for Gate Insulatoruchai
ITRS2009 Fig. FEP17 ITRS2011 Fig. FEP19
ITRS2007
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MOSFET maintains its name due to historical reason, but the “O” is no longer SiO2.
SiO replacement criteria: EOT(physical): thin lectronics
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SiO2 replacement criteria: EOT(physical): thinEOT(electrical): thicklow Dit in contact with Si
high r
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S Kanjanachuuchai
phonon scatteringEF pinning
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S KanjanachuuchaiMaterial & process limits:
1. Gate insulators2. Gate electrodes3 S/D Junctions3. S/D Junctions4. S/D Contacts
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lectronics
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Scaling requires G (and therefore RG) limits of poly-Siuchai
N N N N
resistivity
d i l l
Problem with poly-Si gate:
ND ND ND ND doping levels
10%time
phase separation
ND > solid solubility limitsnot manufacturable
1%c.f. # Si atoms / vol
8/(a3) = 5 1022 cm-3
1%
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resistivity means that poly-Si will not be useful due to solid solubility limit.
The gate must be changed to a metal.
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S KanjanachuF
dimsT C
QCQV 2
poly-Si vs MGuchai
Fii
msT CC
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26See IEDM 45-nm Whitepaper: “45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”
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Fi
d
i
imsT C
QCQV 2MG: materials
Metal gate must be able to provide low V (see Table 1) term must be low:
uchai
Metal gate must be able to provide low VT (see Table 1) ms term must be low:
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Fi
d
i
imsT C
QCQV 2MG: work function
uchai
ITRS 20011: Table FEP2
must be <0.15 eV from bandedge
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One metal gate is OK in NMOS process.Two metal gates are necessary in CMOS process. 4 Intro to Nanoel
g y p
Gate material is still a trade secret at this stage but can be il f d t f t / i
lectronics
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easily found out from spectroscopy/microscopy.
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HKMG: how it works Jox , VT , uchai
Jox , VT ,
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Further reading: IEEE Spectrum October 2007 p. 29 Jox , VT ,
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S KanjanachuuchaiMaterial & process limits:
1. Gate insulators2. Gate electrodes3 S/D Junctions 3. S/D Junctions4. S/D Contacts
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S/D Junction: Ion Implantation (I/I)uchai
xj
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Typical ion energies are in the range of 10 to 500 keV (1,600 to 80,000 aJ). Energies in the range 1 to 10 keV (160 to 1 600 aJ) can be used but result in a penetration of only a few nanometers or less lectronics
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10 keV (160 to 1,600 aJ) can be used, but result in a penetration of only a few nanometers or less. Energies lower than this result in very little damage to the target.
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S Kanjanachuthe main resistance in the MOS structure shall be the channel resistance, i.e.
S/D Junction: Requirementuchai
,
Rparasitics << Rchannel (<10%) where
Rparasitics = Rcontact + Rext + Racc +++ < Rchan
(ก) (ข)(ก) (ข)
but...
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ITRS 2011: lectronics
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Table PIDS2
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S Kanjanachu
S/D Junction: Roadmapuchai
+++ < Rchan
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ITRS 2011 lectronics
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1: Table FEP12
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S KanjanachuIdeal scaling: constant
Rchanneluchai
gReal scaling: decreases with scaling because the physical (tox) and electrical (Vgs - Vth) scaling rates are different
[A] [B]
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Q) Why the industry happily accept reduced Rchannel?A) because reduced Rchannel current drive capability (Id,sat) performance
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S KanjanachuS/D junction requirement:
Raccumulation & Rextension : requirement
+++ < Rchan
uchai
j q
Rchannel Rparasitics
Rparasitics = Rext + Racc + Rcontact
Rchan
Requirement 1: Rext + Racc
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A) form abrupt S/D junctions
Raccumulation & Rextension : how to meet requirementuchai
A) form abrupt S/D junctions
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Q) How to form abrupt junctions?uchai
A )A1)
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A2)
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g. F
EP18
g. F
EP20
ITR
S200
9:Fi
gIT
RS2
011:
Fig
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Rcontact : requirement uchai
2102-5844 Intro to Nanoel. F
EP18
. FEP
20
lectronics
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S200
9:Fi
gIT
RS2
011:
Fig
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S KanjanachuuchaiConclusions
• Economic motivation drives scaling• Rate of scaling = Moore’s law• Real scaling Ideal scaling
• MOS transistor and CMOS will remain the industry workhorses, but…MOS transistor and CMOS will remain the industry workhorses, but…– problems at gate stack (Gate + Oxide), S/D, channel
• Practical and fundamental limits are being approached Changes to
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Practical and fundamental limits are being approached. Changes to device technologies, structures and materials.
• Without new materials and inventions, Moore’s law will end. 4 Intro to Nanoel
,
lectronics
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