2 kw dual input dc-dc converter for fuel cells and...

2 kW Dual Input DC-DC Converter forFuel cells and Ultracapacitors

Bachelor Thesis, April 2007

by

Stefan Pihl Bergendorff

Ørsted • DTU, Automation

Technical University of Denmark

DK-2800 Kongens Lyngby

i

Abstract

This Bachelor thesis covers design and construction of a dual input converter with the ability to

be bidirectional, to one of the converter’s input. The work is done in collaboration with American

Power Conversion, who wanted an alternative to the DC-DC converter that are currently used for

their fuel cell UPS’es, Uninterruptible Power systems. The dual input is a way to eliminate batteries

from APC’s system and replace them with ultracapacitors.

The Dual input converter is a DC-DC convert with an operating range of 30-60VDC, which it

converts to ± 200V. The intended power level for this type of converter is 4kW but the prototype is

downscaled to 2kW.

The purpose of the thesis is primarily to investigate the potential of the converter in terms of

efficiency and complexity. The requirements for the input harmonics is not taken into consideration,

since it is the first prototype. The efficiency is high due to a solid design of the power components.

The bidirectional part of the converter was not realized due to lack of time and the designed control

scheme, is not used to test the converters efficiency because it was not available before the deadline

of the thesis.

The measurement was made with an improvised control, and an efficiency of 91% was obtained

at the lowest input voltage.

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iii

Resumé på dansk

Dette bachelorprojekt omhandler design og konstruktion af en "dual input converter" med mulighed

for at føre effekt tilbage til en af indgangende på konverteren. Arbejdet er udført i samarbejde med

American Power Conversion, som ønskede et alternativ til den nuværende DC-DC konverter som

benyttes til deres fuel cell UPS, Uninterruptible Power systems. Idén med two input er at APC

ønsker at fjerne batterierne fra deres UPS systemer og erstate dem med ultracapacitore.

Dual input converteren er en DC-DC konverter som kan omforme indgangs spændingen som er

mellem 30 og 60volt til en udgangsspænding på± 200V. Det tiltænkte effect niveauet var 4kW men

det valgtes for prototypen at nedskalere effecten til 2kW.

Formålet med projektet er primært at undersøge potentialet af converteren i form af effektivitet

og kompleksitet. kravende til de harmoniske inputstrømme er der ikke taget videre hensyn til da det

er en prototype. Effektiviteten holdes høj ved et grundigt design og valg af effektkomponenter. Den

bidirektionele del af konverteren er ikke blevet realiseret på grunde tidspres. Kontrol kredsløbet er af

samme årsag blevet nedprioteret, og det designede regulering er ikke benyttet til test af konverteren,

da det ikke var tilgængeligt før afleverings datoen.

Målingerne, som var lavet med en improviseret regulering, viste en høj effektivitet på 91

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iv

Preface

This thesis has been submitted to the Automation Department, Ørsted, Technical University of

Denmark, with the purpose of obtaining an international engineering bachelor degree in power

electronics. The experimental research presented in this thesis has been carried out from the 15 of

January 2007 to the 10 of April 2007.

During this period I have spent most of the time at APC, the daily contact with the research

engineers at APC, has been a great source of knowledge for me. I would especially like to thank

my supervisor projekt manger Henning Roar Nielsen, and former RD Engineer Jesper Winston

Petersen, for their insight and expertise. I would also like to thank my supervising Professor Michael

A. E. Andersen for putting me in contact with APC and Klaus T. Moth, former director of emerging

technology department.

Finally I would like to thank my family and friends for being patient withme, when I have been busy with my study.

Stefan Pihl Bergendorff Marts 2007.

List of publications

[1] H. Schneider, S. Pihl Bergendorff, L. Petersen and M. A. E. Andersen, "Isolated EWiRaC: A New Low-Stress Single-Stage Isolated PFC Converter", APEC2007 conference paper, Technical University of Den-mark.

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TABLE OF CONTENTS v

Table of Contents

Abstract i

Resumé på dansk iii

Preface v

List of figures 2

List of tables 3

1 Introduction 4

1.1 Background Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.1 Overall System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.2 Fuel Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.3 Ultracapacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1.4 UPS Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1.5 Basic Requirements For The DC-DC Converter . . . . . . . . . . . . . . . 11

1.1.6 Project Delimitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 DC-DC Converter Theory 13

2.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 The Modified Voltage Fed Full Bridge Converter . . . . . . . . . . . . . . 13

2.1.2 The Modified Current Fed Full Bridge Converter . . . . . . . . . . . . . . 16

2.1.3 The Modified Current Fed Push-Pull Converter . . . . . . . . . . . . . . . 18

2.1.4 Conclusion Topology Selection . . . . . . . . . . . . . . . . . . . . . . . 20

2.1.5 CCM or DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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vi TABLE OF CONTENTS

3 DC-DC Converter Design 213.1 Power Calculation and Component Selection . . . . . . . . . . . . . . . . . . . . 21

3.1.1 Switch Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1.2 Input Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1.3 Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1.4 Output Diode Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.1.5 Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.1.6 Estimated Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2 Control Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2.1 Constructed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4 Implementation, Measurements and Performance 434.1 Layout of the DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.1.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2 Efficiency of the converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5 Discussion, Conclusion and Future Work 46

Bibliography 47

Appendix 47

A 48A.1 Magnetomotive force in the transformers . . . . . . . . . . . . . . . . . . . . . . . 48

B 49B.1 Leakage inductance in the transformers . . . . . . . . . . . . . . . . . . . . . . . 49

C 51C.1 Control design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

D 62D.1 Pspice diagram of the converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

vi

LIST OF FIGURES 1

List of Figures

1.1 Block diagram of the overall system for ulracaps/fuell cell application . . . . . . . 5

1.2 Fuel cell chemistry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 A fuel cell stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Performance curves for a single PEM fuel cell . . . . . . . . . . . . . . . . . . . 7

1.5 Individual ultracapacitor cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6 Ultracapacitors MC2600 series (with 2600 farad capacitance) produced by Maxwell

Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 The modified voltage fed full bridge converter . . . . . . . . . . . . . . . . . . . . 14

2.2 Waveforms for the modified voltage fed full bridge converter . . . . . . . . . . . . 15

2.3 Modified current fed full bridge converter . . . . . . . . . . . . . . . . . . . . . . 16

2.4 Modified current fed full bridge converter waveforms . . . . . . . . . . . . . . . . 17

2.5 Modified current fed push-pull converter . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 Modified current fed push-pull converter waveforms . . . . . . . . . . . . . . . . . 19

3.1 Diagram of the DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 Switch PWM signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 Switch current at 30V in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 Pspice simulation graph of the switch current at 30V in . . . . . . . . . . . . . . . 25

3.5 Normalized on resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . 26

3.6 MOSFET and it’s turn-on/turn-off transition waveform . . . . . . . . . . . . . . . 27

3.7 Pspice simulation graph of the switch current and voltage at 30V in . . . . . . . . . 28

3.8 Core loss density curve, Kool Mµ . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.9 Primary voltage in one switch cycle . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.10 Winding chamber of an ETD49 coil former . . . . . . . . . . . . . . . . . . . . . 34

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2 LIST OF FIGURES

3.11 Correction factor for the transformer resistance as a function of ϕ and number of

layers M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.12 Core loss density curve, for 3C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.13 Core loss frequency/density curve vs. temperature, for 3C90 . . . . . . . . . . . . 38

3.14 Forward current versus voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.15 controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.16 controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.17 Controller diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.1 Picture of the DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2 Operating efficiency of the converter . . . . . . . . . . . . . . . . . . . . . . . . . 45

A.1 Behavior of the MMF in a transformer . . . . . . . . . . . . . . . . . . . . . . . . 48

C.1 Control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

C.2 Simulation model for the output characteristic . . . . . . . . . . . . . . . . . . . . 53

C.3 Bodeplot of the output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 54

C.4 Close loop bodeplot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

C.5 Control sheet 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

C.6 Control sheet 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

C.7 Control sheet 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

C.8 Control sheet 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

C.9 Control sheet 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

C.10 Control sheet 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

D.1 Pspice diagram of the converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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LIST OF TABLES 3

List of Tables

1.1 Table showing different types of fuel cells . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Basic requirements for the DC-DC converter . . . . . . . . . . . . . . . . . . . . . 11

3.1 Loss in power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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4 Chapter 1. Introduction

Chapter 1

Introduction

This project has been developed in collaboration with APC (American Power Conversion) as they

have a great desire to eliminate batteries from their UPS (Uninteruptible Power system) systems.

APC is one of the biggest takers of lead batteries in the world, they have to replace approximately

80 million batteries every year. APC is currently investigating new technologies such as fuel cells.

But even with fuel cell systems there is a need for batteries, because the fuel cell systems have a

upstarts periode of 5-20 seconds. So this thesis report propose a DC-DC converter that incorporates

ultracapacitors in a fuel cell system, instead of batteries.

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1.1. Background Information 5

1.1 Background Information

1.1.1 Overall System

The chosen solution for incorporating ultracapacitors, as a power source, for a UPS system is illus-

trated on figure 1.1.

Figure 1.1: Block diagram of the overall system for ulracaps/fuell cell application

The overall system is powered from a fuel cell module and a ultracapacitor module. The output

voltage from these, which is 30-60V, has to be converted to ±200V for the input to the UPS. The

nominal power that the DC-DC converter should transfer is 4kw, but for reasons of convenience,

and simplicity it has been chosen to make the converter a 2kw. The main focus in the project will

be laid on showing that the topology actually works, and that it is highly efficient.

The specifications for the DC-DC converter will meet the demands from a fuel cell system and a

ultracapacitor module. The expected efficiency for the DC-DC converter is 93%. The specifications

is summarized in table 1.2subsection 1.1.5

1.1.2 Fuel Cells

Fuel cells convert fuel and air directly to electricity, heat and water in an electrochemical process.

Unlike conventional engines, they do not burn the fuel and run pistons or shafts, and so have fewer

efficiency losses, low emissions and no moving parts.

In principle a fuel cell operates like a battery. However, unlike a battery, it will not run down

while it continues to be supplied with fuel and air.

It is an essentially clean technology that uses hydrogen (from its fuel source) and oxygen (from

the air) to generate electricity and heat without combustion or pollution, its only basic emission

5


being vaporized water.

Basic Principle Of A Fuel Cell

In the fuel cell hydrogen and oxygen react to create water, electricity and heat, which can be used

in various applications. The reaction is essentially the reverse of electrolysis. There is no noise or

mechanical movement involved. The fuel cell is like a battery, the only difference being that as long

as hydrogen is provided it will continue to provide power. Hydrogen (1) and oxygen is supplied

Figure 1.2: Fuel cell chemistry

on each side of a cell. The cell consists of an electrolyte membrane with a catalyst layer on each

side. When hydrogen is lead to the first catalyst layer, the anode, the hydrogen molecules are split

into their basic elements, a proton (2) and an electron. The protons migrate through the electrolyte

membrane (4) to the second catalyst layer, the cathode. Here they react with oxygen to form water

(5). At the same time the electrons are forced to travel around the membrane to the cathode side,

because they can not pass the membrane. This movement of electrons thus creates an electrical

current (3).

A typical fuel cell produces 0.5-1 volt. The appropriate voltage level for a specific application

is achieved by combining a number of single cells in series and parallel circuits to form a fuel cell

stack.

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Figure 1.3: A fuel cell stack

As figure 1.4 demonstrates, a PEM fuel cell yields an efficiency of 34% when operated at it’s

point of highest power density. The low efficiency of the fuel cells means, that in order to make

optimal use of the fuel cell, the system that is powered by them should have a high efficiency.

In order not to influence the chemical reactions in the fuel cells, the input ripple current have to be

Figure 1.4: Performance curves for a single PEM fuel cell

above 1kHz. Other than that there are no known requirements for the size of the input ripple current.

But from a logical point of view, the input ripple current should be as small as possible.

The Different Types Of Fuel Cells

There are several different types of fuel cell, but all share the basic design of two electrodes (a

negative anode and a positive cathode) separated by a solid or liquid electrolyte.

Fuel cells are classified according to the nature of their electrolyte which also determines their

operating temperature. Each type of fuel cell has particular materials requirements and, in theory,

all can use a wide range of fuels, providing that the fuel contains hydrogen. The most common ones

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can be seen in table 1.1

Types abbreviation Electrolyte Ion Temp. [C]Direct Methanol Fuel Cell DMFC Polymer H+ 30-80Proton Exchange Membrane FC PEMFC Polymer H+ 70-200Solid Oxide Fuel Cell SOFC Conducting ceramic O−

2 650-1000Phosporic Acid Fuel Cell PAFC Phosporic acid H+ 150-200Molten Carbonate Fuel Cell MCFC Carbonate acid CO−

3 650Alkaline Fuel Cell AFC Aqueous alkaline solution OH− 150-200

Table 1.1: Table showing different types of fuel cells

1.1.3 Ultracapacitors

Like batteries, ultracapacitors are energy storage devices. They use electrolytes and configure

various-sized cells into modules to meet the power, energy, and voltage requirements for a wide

range of applications. But batteries store charges chemically, whereas ultracapacitors store them

electrostatically.

Ultracapacitors are true capacitors in that energy is stored via charge separation at the electrode-

electrolyte interface, and they can withstand hundreds of thousands of charge/discharge cycles with-

out degrading. An ultracapacitor, also known as a double-layer capacitor, polarizes an electrolytic

solution to store energy electrostatically. Though it is an electrochemical device, no chemical reac-

tions are involved in its energy storage mechanism. This mechanism is highly reversible, and allows

the ultracapacitor to be charged and discharged hundreds of thousands of times.

How An Ultracapacitor Works

An ultracapacitor can be viewed as two nonreactive porous plates, or collectors, suspended within

an electrolyte, with a voltage potential applied across the collectors. In an individual ultracapacitor

cell, the applied potential on the positive electrode attracts the negative ions in the electrolyte, while

the potential on the negative electrode attracts the positive ions. A dielectric separator between the

two electrodes prevents the charge from moving between the two electrodes.[4][5]

Once an ultracapacitor is charged and energy stored, a load can use this energy. The amount of

energy stored is very large compared to a standard capacitor because of the enormous surface area

created by the porous carbon electrodes and the small charge separation created by the dielectric

separator. However, it stores a much smaller amount of energy than does a battery. Since the

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Figure 1.5: Individual ultracapacitor cell

rates of charge and discharge are determined solely by its physical properties, the ultracapacitor can

release energy much faster (with more power) than a battery that relies on slow chemical reactions.

[4][6]

A single ultracapacitor can only produce a potential of 2,5-2,7 voltage. For moste applications

this it not enough, so the ultracapacitors has to be aligned in a konstellation of serial and parallel

connections, to obtain the desired voltage and energy. Further more to utilize the ultracapacitor

effectively it is not desired to discharge them more than to half the rated voltage. In this way it is

possible to obtain 75% of the initial stored energy.[4]

Figure 1.6: Ultracapacitors MC2600 series (with 2600 farad capacitance) produced by Maxwell Technologies

A short summary of the features of ultracaps. vs. batteries is listed below.

Advantages:

• Very high rates of charge and discharge.

• Little degradation over hundreds of thousands of cycles.

• Good reversibility

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• Low toxicity of materials used.

• High cycle efficiency (95% or more)

Disadvantages:

• The amount of energy stored per unit weight is considerably lower than that of an electro-

chemical battery (3-5 W.h/kg for an ultracapacitor compared to 30-40 W.h/kg for a battery).

It is also only about 1/10,000th the volumetric energy density of gasoline!

• The voltage varies with the energy stored. To effectively store and recover energy requires

sophisticated electronic control and switching equipment.

• Has the highest dielectric absorption of all types of capacitors

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1.1.4 UPS Load

A UPS(Uninteruptible Power System - UPS) is a emergency power generating unit. It takes over the

supply of electrical power for a critical load at a power outage. The critical load will hereby function

undisturbed. The UPS works with a voltage range of pm160− 220V , but it has been decided on a

voltage output of ±200V , from the DC-DC converter.

1.1.5 Basic Requirements For The DC-DC Converter

Table 1.2 shows the basic requirements for the DC-DC converter. The input voltage values are

typical for the present fuel cell modules at APC. The nominal output voltage is also typical for

a standard 10kW UPS at APC. Initially the DC-DC converter should have been a 4kW converter

that would have been connected in parallel on the input and serial on the output with 3 identical

converters, so that they could handle 10kW with a smaller loss compared to one big 10kW converter.

But in accordance with APC it was decide to make a 2kW converter, because of the time issue of 10

weeks to complete the project. As said earlier, the main focus is on how well the converter functions

U Max ripple Response after load Pout

step (0%-100%-0%)[VDC] [Vpp] [V] [kW]

InputMinimum 30Maximum 60

OutputNominal ±200 2 +20 / -20 2

Table 1.2: Basic requirements for the DC-DC converter

and how high an efficiency that can be obtained. Because of the need for galvanic isolation, it is not

believed that an efficiency higher then 93% is obtainable. The EMI requirements an input current

harmonics will not be taken into greater consideration, because this a prototype. Additional research

will have to be done if this topology is going to be used in an actual application.

1.1.6 Project Delimitation

The project has the following main points, established on the past system analysis and problems

encountered along the way. The main focus of the report is laid on the following points:

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• Power components design

• Converter design

• Construction of the converter design

However the bidirectional part of the design is neglected as the complexity of the chosen topology

is high even without this part, and it would be hard pressed to manage it before the deadline of

10 weeks. The control circuit was demoted to a secondary aspect, because of many problems

with internal matters at APC as well as having it produced by an external partner. The internal

problems includes a slow procedure of "inhouse" communication with regard to spending money

on projects. Another unfortunate incident happened when APC was taken over by a larger company,

the Schneider group, which resulted in a downsizing of the ETD department, where I was situated,

including two of my counsellors. I did not manage to find new counsellors but still had the head

of technology department, Henning Roar Nielsen as counsellor, but it was limited time he had to

spare.

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13

Chapter 2

DC-DC Converter Theory

The main criterions to find a suitable converter topology, is the necessary galvanic isolation needed

in a real application and the converters ability to increase the input voltage to the desired output

voltage. The dual input and bidirectional ability criterions is also to be taken into consideration.

The topology that can fulfill these requirements is a boost type converter. There are 3 different

types of boost converters 1 that is considered, the modified voltage fed full bridge converter, the

modified current fed full bridge converter and the modified current fed push-pull converter. The

modification consist essentially in the need for two inputs and an output of ±200V .

2.1 Topology Selection

The voltage fed full bridge converter is shown on figure 2.1 and consist of two identical inputs,

where only one of them will be utilized at a time, why the converter can be viewed as having one

input for simpler explanation, as do all the considered converters.

2.1.1 The Modified Voltage Fed Full Bridge Converter

The voltage fed full bridge converter uses four switches on the primary side. Figure 2.2 shows the

typical waveforms of the converter. The switches is driven alternately in pairs, SW1 and SW4, then

SW2 and SW3. The transformer primary is subjected with the alternating voltage Vpri that can

either be Vin, −Vin or zero, depending on the state of the switches.

The rectifier on the output is built as a double center-point bridge rectifier, which works similar

1Technically the voltage fed converter is a Buck type converter

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14 Chapter 2. DC-DC Converter Theory

Figure 2.1: The modified voltage fed full bridge converter

to the normal bridge rectifier. The difference lying in, two output voltages for similar loads can be

produced, and the diodes having to block two times the peak voltage of the transformers secondary

voltage.

The switches placed on the output is for conducting power the opposite way trough the converter

to the input off the ultracapacitors. This however has not been investigated properly, due to lack of

time, therefor it has been cut from the agenda and will not be mentioned further in the report other

than on diagrams.

∆t1: At t0 the switches SW1 and SW4 are switched on, and the positive half-wave of the

secondary voltage of T1 and T2, is respectively conducted with the forward biased diodes D1 and

D5. At the same time the negative half-wave of the secondary voltage of T3 and T4 is conducted

trough the forward biased diodes D8 and D4.

∆t2: At t1 the current Ipri1 and Ipri2 has become zero. Primary voltage and secondary voltage

of the transformers are zero,and the diodes D1D8 are conducting. The switches SW1 − SW4 are

off.

∆t3: At t3 the the negative half-wave of the secondary voltage of T1 and T2 is applied, the

diodes D3 and D7 is forward biased and the secondary voltage is conducted to the LC-filter and the

load at Vout2. The secondary voltage of T1 and T2 will in the same time period be conducted via the

forward biased diodes D6 and D4 to the LC-filter and the load at Vout1. Because the current for one

half-wave has to pass through two parallel diodes the the diodes losses will be low.

∆t4: At t1 the current Ipri1 and Ipri2 has become zero. Primary voltage and secondary voltage

14

2.1. Topology Selection 15

Figure 2.2: Waveforms for the modified voltage fed full bridge converter

of the transformers are zero, too. The diodes D1−D8 are conducting, and the switches SW1−SW4

are off.

Theoretical the duty cycle of this converter can be chosen as one, leading to a duty cycle of 0,5

for each switch pair. However in a practical solution, where transistors would be used, a delay, td

is needed, because the transistors has a death time. This means that by using a duty cycle of 0,5 for

the transistor and one transistor pair is switched on the moment the second pair is switched off a

short circuit can happen.

15


2.1.2 The Modified Current Fed Full Bridge Converter

Figure 2.3: Modified current fed full bridge converter

The circuit of the current fed full bridge converter is shown in figure 2.3. At the input there

is the filter inductance L1. As will be shown in the following, a clamping circuit is needed. This

active clamp circuit consists of the diode DCl and the capacitance with assumed constant voltage

CCl and the switch SWCl. The maximum blocking voltage of the switches SW1 − SW4 is the

voltage of the clamping circuit. The transformers T1 − T4 has the turn ratio n. The rectification

on the secondary side is realized with a double center-point full bridge rectifier consisting of the

diodes D1D8 connected to a smoothing capacitor and the output voltage Vout1 and Vout2. Figure

2.4 shows the waveforms and characteristic time instants of the current fed full bridge converter. In

the following the converter’s operation between the time instants is described.

∆t1: In the period before t0, all the switches have been conducting. At t0 the switches SW1 and

SW4 are switched on, and the primary currents Ipri1 and Ipri2 is impressed into the transformers

and energy is transferred via the transformer to the secondary.

∆t2: At t1 switches SW2 and SW3 are switched on, and all switches are conducting. The

transformer current has become zero and will be zero until the time instant t2. The inductor IL1 is

rising due to the voltage Vin1 across the inductance L1. Energy is stored in the inductance L1.

∆t3: At t2 switches SW1 and SW4 are switched off, and the primary currents Ipri1 and Ipri2 is

16


Figure 2.4: Modified current fed full bridge converter waveforms

impressed into the transformers and energy is transferred via the transformer to the secondary.

∆t4: At t3 At t2 switches SW1 and SW4 are switched on, and all switches are conducting. Due

to the symmetrical circuit of the converter the waveforms in the second half period are equal to the

waveforms shown above on figure 2.4 .

On figure 2.3 a clamp circuit is shown. The current fed full bridge converter needs this circuit

for the energy stored in the transformer’s leakage inductance. Leakage inductance is the difference

between the self-inductance and the mutual inductance of the primary and secondary windings. Its

value is typically quite small, but very important in determining the characteristics and operation

of the circuit. The leakage inductance contributes to a turn-off voltage spike seen by the switching

17


device and thereby contribute considerable to the switching loss of the switching devices.

2.1.3 The Modified Current Fed Push-Pull Converter

Figure 2.5 shows the modified current fed push-pull converter. The operating principle is faily

simple; the switches is both kept in the on state in order for the magnetizing of the inductors to

take place and is turned off, one after the other, so that the energy is transferred to the loads via

the transformers. The modified current fed push-pull converters waveform transitions is shown on

Figure 2.5: Modified current fed push-pull converter

figure 2.6 and described in the following.

∆t1: At t0 the switches SW1 and SW2 is conducting and no power is delivered to the trans-

former. Energy is stored in the input inductors L1 and L2 while the output filter capacitors feeds the

loads.

∆t2: At t1 switch SW2 is turned off and the primary currents Ipri1 and Ipri2 is impressed into

the primary which is submitted to the reflected output voltage and energy is transferred to the load

through the rectifier diodes.

18


Figure 2.6: Modified current fed push-pull converter waveforms

∆t3: At t2 the switches SW1 and SW2 is conducting and no power is delivered to the trans-

former. Energy is stored in the input inductors L1 and L2 while the output filter capacitors feeds the

loads.

∆t4: At t3 switch SW1 is turned off and the primary currents Ipri1 and Ipri2 is impressed into

the primary which is submitted to the reflected output voltage and energy is transferred to the load

through the rectifier diodes.

The advantages of this topology is that two input inductors results in less current stress, since

the average current is half that in the current fed full bridge converter. The current ripple is also very

low as the two induct ripples will cancel each other out totally at 0,5 duty cycle and less at higher

19


duty cycles.

2.1.4 Conclusion Topology Selection

The voltage fed full bridge converter is obviously the least desirable topology as the current ripple

on the input source is considerable and would require large capacitors.

The current fed full bridge converter is on the other hand interesting, as power is drawn contin-

uously and the input current ripple theoretically is zero, as there never will be a DC voltage across

the input inductor.

But compared to the current fed push-pull converter, which also draws the power continuously,

it has four switches that is conducting the power to the transformer. Where as the push-pull only

has two and the input current is halved by two inductors, which should lead to lower losses.

The current fed push-pull converter is chosen as the most likely to fulfill topology the demands

and yield the highest efficiency.

2.1.5 CCM or DCM

The push-pull converter is necessarily run in continuous conduction mode or CCM, because it is

constructed with isolated transformers that contains a magnetizing inductance.[1] The current in

the input inductors IL1−2 has to be above zero at all times, if not the magnetizing inductance will

be short circuit when all switches SW1 − SW4 are on. Which would result in a saturation of the

transformer cores.

An overlap of the switching periods is needed as shown on figure 2.6 for the two switches. This

means, that for the current IL1 to be large than zero, the switch duty cycle has to be large than 0,5.

Otherwise, the energy buildup in the input inductors isn’t possible.

IL > 0 ⇒ D > 0, 5 (2.1)

The magnetizing of the transformers can’t be reset if If there isn’t an overlap in the switch

periods. By removing the magnetizing of in the transformer cores, a better utilization is archived.

Hence the flux is driven in both directions.

20

21

Chapter 3

DC-DC Converter Design

Along with the design specification, all power and control elements are design to fulfill the require-

ments given by the functional specification and the basic requirements of the respective components.

In the following the power components and output filter are designed. After this the control scheme

is discussed and designed accordingly, and to simplify and make the calculations more understand-

able there is shown overview diagrams of the respective components/circuits in question. All power

calculations is done as there where only one input to the converter, due to the fact that the two inputs

is identical and functions separately.

3.1 Power Calculation and Component Selection

Figure 3.1: Diagram of the DC-DC converter

The power components are designed according to the converters "worst case" losses. The losses

21

22 Chapter 3. DC-DC Converter Design

should be worst at low input voltage, 30V and full output power, 2kW. With an expected efficiency

of 93%, the input power for the converter will be:

Input power = 2kW + 7% = 2000W · 1, 07 = 2140W (3.1)

This means that at Vin = 30V , Iin_max will be:

Iin_max =2140W

30V= 71, 33A (3.2)

and at Vin = 60V , Iin_max will be:

Iin_max =2140W

60V= 35, 67A (3.3)

The duty cycle for boost topology converters has to be above 50%, so the duty cycle for this

converter is chosen to 55% at Vin_max. Which means that the peak primary voltage of the converter

will be:

Vpri peak (total of two primary windings in series) = Vin_max ·1

(1−Dmin)(3.4)

= 60V · 1(1− 0, 55)

= 133, 3V (3.5)

The peak primary voltage, Vpri for each transformer is then 133,3V2 = 66, 65V ≈ 67V , and with

Vout = 200V the transformer ratio will be:

67V

200V≈ 1 : 3 (3.6)

By assuming transformer ratio to be exact, 1:3 and by including output rectifier drop, the "real" pri-

mary voltage can be calculated.(The calculation is still while assuming that the transformer leakage

inductance is zero):

Vpri_total =2 · (200V + 2V )

3= 135V (3.7)

The transformer ratio of 1:3 is chosen because it will make it possible to make a better coupling,

see subsection 3.1.3 transformer design. When otherwise a smaller ratio could give a lower primary

voltage and shorter duty cycles, which again would giver lower losses in the switches. But it is

expected that it is the leakage inductance from the transformer that will cause the high switching

22

3.1. Power Calculation and Component Selection 23

losses, therefor it is most important to obtain a good coupling between the primary and secondary

windings.

With Vpri = 135V the duty cycle for the boost switches can be calculated, with the duty cycle

formula for an boost topology:

D = 1− Vin

Vout(3.8)

In this case the Vout is the primary voltage Vpri of the transformer. At Vin_max the duty cycle will

be:

Dmin = 1− 60V

135V= 0, 56 (3.9)

And at Vin_min the duty cycle will be:

Dmax = 1− 30V

135V= 0, 78 (3.10)

With the switching duty cycles determined, the overlap of the switches can be found by the wave-

forms on figure 3.2: The overlap of switch signals at 60V in can be be found to 1, 06− 1 = 0, 06 of

(a) (b)

Figure 3.2: Switch PWM signals

the duty cycle and at Vin = 30V the overlap is 1, 28− 1 = 0, 28.

3.1.1 Switch Design

The chosen switch is a irfp90n20d Power MOSFET, witch is a 200V and 94A transistor in a TO-247

housing.

23


MOSFET Conduction losses

The conduction loss in a MOSFET can be determined by:

Pcond = RDS(on)· I2

rms (3.11)

With the duty cycle determined the switch current waveforms can be found to be:

Figure 3.3: Switch current at 30V in

From figure 3.3 the RMS current in the switches can be calculated:

Irms_30V =√

(2 · 0, 28) · 35, 67A2 + 0, 22 · 71, 33A2 = 42, 80A (3.12)

The pspice simulation however shows that a relative large power is recycled through the clamp

circuit and back to the boost switches:

The simulations rms current at Vin = 30V is calculated to:

Irms_sim =√

0, 28 · 40, 20A2 + 0, 22 · 89, 00A2 + 0, 28 · 50, 01A2 = 53, 81A (3.13)

This current will be used for the following calculations.

The total MOSFET on-state losses (not including MOSFET in clamp circuit) are chosen to allow

24


Figure 3.4: Pspice simulation graph of the switch current at 30V in

loss of 2,5% of converter power rating at minimum input voltage.

Pper_switch = 0, 0125 · 2000W = 25W (3.14)

which yields an "on" resistance of:

RDS(on)max =Pper_switch

I2rms_sim

=25W

53, 81A2= 8, 6mΩ (3.15)

The chosen MOSFET has a static on resistance, RDS(on)max, of 23mΩ which means the number of

MOSFET needed in in parallel is:

23mΩ8, 6mΩ

= 2, 67 ≈ 3 (3.16)

But as the temperature rises so does the MOSFET’s "on" resistance. The expected operating tem-

perature is 80C which gives an RDS(on)= 1, 5 · 23mΩ = 34, 5mΩ according to figure 3.5.

With RDS(on)= 34, 5mΩ the number of needed MOSFET’s in parallel is:

34, 5mΩ8, 6mΩ

= 4, 012 ≈ 4 (3.17)

25


Figure 3.5: Normalized on resistance vs. temperature

and the conduction losses per switch, can then be found by:

Pcond. per switch =RDS(on)

4(4 MOSFET’s in parallel)· I2

rms_sim (3.18)

(3.19)

=34, 5mΩ

4· 53, 81A2 (3.20)

(3.21)

= 24, 97W (3.22)

Total conduction losses:

Pcond = 2 · Pcond. per switch = 2 · 24, 97W = 49, 94W (3.23)

MOSFET switching losses

The loss in a MOSFET also consist of a switching loss. Figure 3.6 shows a MOSFET and it’s

"turn-on" and "turn-off" transition waveforms. The Miller charge capacitance, CDG holds the drain

voltage until the full drain current, ID flows through the MOSFET, which results in switching losses

at the "turn-on" and "turn-off" periods.

The instantaneous power that is dissipated in the MOSFET during the "turn-on" and "turn-off"

periods can be calculated as the gray area of the triangular shape times the switching frequency. The

26


(a) Magnified view of MOSFET turn-on and turn-off transition waveforms (b) MOSFET with it’s ef-fective terminal capacitance

Figure 3.6: MOSFET and it’s turn-on/turn-off transition waveform

switching losses is calculated with the following formulas:

PSW = Pon + Poff = (P∆t2 + P∆t3) + (P∆t5 + P∆t6) (3.24)

The power loss in time period ∆t2 can be found by:

P∆t2 = fsw ·12· VDS ·

ID

4(4 MOSFET)·RG · (CGS + CDG) · ln

VG − VT

(VG − VT )− ID/4g

(3.25)

where RG is the gate resistor, first chosen to 5ohm but during testing of the converter, raised to

13,3ohm due to of problems with electrical noise disturbances. (CGS + CDG), also known as the

input capacitance, is stated in the data sheet to 6040pF. VG is the gate voltage and VT is the gate

threshold voltage which should be between 3,0V and 5,0V. g is the forward transconductance and

stated to 39s.

Figure 3.7 shows the drain current ID, the blue graph, and voltage VDS as the purple/pink graph,

27


across the MOSFET’s. It can be seen that according to simulations VDS is clamped to 160V at the

turn-off period of the MOSFET’s. As mentioned earlier the it is the leakage inductance of the

transformers that induceses the high voltage across the MOSFET’s. The leakage inductance is set

to 0,2% of the inductance of the primary transformer inductance, which is analog to the measured

leakage inductance of the transformers, se appendix B.

Figure 3.7: Pspice simulation graph of the switch current and voltage at 30V in

The power losses in ∆t2 can now be calculate as:

P∆t2 = 45kHz · 12· 132, 60V · 27, 04A

4· 13, 3Ω · (3.26)

(6040pF ) · ln

(15V − 4V

(15V − 4V )− 27,04A/439s

)(3.27)

= 25, 7mW (3.28)

The power losses in time period ∆t3 can be calculated as:

P∆t3 = fsw ·12· VDS ·

ID

4(4 MOSFET)·RG ·

∆Q

(VG − VT )− ID/4g

(3.29)

= 45kHz · 12· 132, 60V · 27, 04A

4· 13, 3Ω · 87nC

(15V − 4)− 27,04A/439s

(3.30)

= 2, 16W (3.31)

The parameter ∆Q is the gate to drain charge or the "Miller" charge stated to 87nC in the data sheet.

28



P∆t5 = fsw ·12· VDS ·

ID

4(4 MOSFET)·RG ·

∆Q

VT + ID/4g

(3.32)

= 45kHz · 12· 160, 17V · 52, 42A

4· 13, 3Ω · 87nC

4V + 52,42A/439s

(3.33)

= 12, 60W (3.34)


P∆t6 = fsw ·12· VDS ·

ID

4(4 MOSFET)·RG · (CGS + CDG) · ln

VT + ID/4g

VT

(3.35)

= 45kHz · 12· 160, 17V · 52, 42A

4· 13, 3Ω · (6040pF ) · ln

(4V + 52,42/4

39s

4

)(3.36)

= 4, 11W (3.37)

The switching loss per switch is found to be:

PSW = (0, 0257W + 2, 16W + 12, 60W + 4, 11W ) · 2 = 37, 79W (3.38)

and the total MOSFET loss is calculated as:

PMOSFET = Pcond + PSW = 49, 94W + 37, 79 = 87, 73W (3.39)

3.1.2 Input Inductor Design

The input inductors are chosen in accordance with the requirement of the maximum input current.

It is assumed that input from the fuel cell as well as the ultracapacitor module is a pure DC voltage

source. As the switching frequency is 45kHz, the requirement of the maximum fuel cell input ripple

harmonic being higher than 1kHz is not an issue.

Copper loss calculation

The chosen inductor has an inductance of 65µH and two windings, that is used in parallel which

according to it’s data sheet gives an RDC_max of 8mohm. The inductance of 65µH gives an AC

29


ripple of:

∆IL =30V · 0, 78 · 22µs

65µH= 7, 92A (3.40)

The inductor is capable of handling a RMS current of 36A, and is made by Falco for APC. The

RMS current value is close to the maximum input current, but it is wanted by APC that the inductor

is pushed as far as possible, as an extra experiment. With an RDC_max of 8mohm the theoretical

winding loss can be calculated at 30V per inductor:

PCU_DC_30V = I2L_rms ·RDC_max = 35, 67A2 · 0, 008Ω = 10, 18W (3.41)

The above calculations does not take into consideration that the AC winding resistance at 45kHz

will be significantly higher than at DC. The current through the inductor can roughly be considered

as a DC part and an AC part at 45kHz(ignoring higher harmonics). The IL_rms of the AC ripple

current can be calculated as:

IL_rms =∆IL

2 ·√

3=

7, 92A

2 ·√

3= 2, 3A (3.42)

The AC loss in the inductor is primarily caused by skin effect, which causes the resistance and

copper loss to increase at high frequencies. High frequency currents do not penetrate to the center

of the wire but crowds at the surface. The inside of the wire is not utilized and the effective wire

cross sectional area is reduced. The length with which the effective cross sectional area is reduced

is called the the penetration depth or the skin depth, and the penetration depth of a copper wire is

given by:

δ =75√f

mm =75√

45 · 103 Hzmm = 0, 35 mm (3.43)

This reduction of the conductor thickness h of the wire to δ, effectively increases the resistance

by the same factor. Hence the conductor can be viewed as having an "ac resistance" given by:

RAC =hδ·RDC (3.44)

This equation however was made by Dowell (1966) and it was developed for rectangular wires

with the hight h. For round wires the equation h = dCU ·√

π4 is applied.[3]

RAC =dCU ·

√π4

δ·RDC =

2 mm ·√

π4

0, 35 mm· 0, 008Ω = 40, 5mΩ (3.45)

30


The ac copper loss in the conductor is:

PCU_AC_30V = I2AC_rms ·RAC = 2, 32 · 40, 5mΩ = 0, 21W (3.46)

A more exact winding copper loss can be found to be:

PCU = PCU_DC_30V + PCU_AC_30V = 10, 18W + 0, 21W = 10, 39W (3.47)

Core loss calculations

The power loss in the inductor also consists of a core loss, the core loss is often shown as a curve in

the data sheet for the core material:

Figure 3.8: Core loss density curve, Kool Mµ

Figure 3.8 shows the curve for the typical core loss per volume vs. flux density, for the material

kool Mµ with the permeability 26µ. One way of calculating the core loss is by knowing the fre-

quency and the maximum flux density of the inductor, and then draw a straight line in the double

logarithmic graph at the wanted frequency. Formula 3.48 is an approximation of core loss at the

flux density of the inductor at a given frequency.

Pfe = Pv(Typical core loss) · Vc(core volume) (3.48)

31


The maximum flux density of the inductor is given by.

B =VL · Ts ·D2 ·N ·Ac

=60V · 22µs · 0, 56

2 · 33 · 2, 29 · 10−4m2= 34mT (3.49)

where Ts · D is the time period where the maximum voltage, VL is the applied voltage to the

inductor. Ac is the cross sectional area of the inductor core, and N is the number of winding turns.

with the maximum flux density and frequency known, the core loss can be calculated. The data

sheet uses US units, and 34mT is the same as 340 Gauss, as 1 Tesla equals 104 Gauss. At 340 Gauss

and 45 kHz the typical core loss is read to 42 mW/cm3. The volume of the core is 28,68 cm3

according to the data sheet. The core loss can then be calculated:

Pfe = 28, 68cm3 · 42mW/cm3 = 1, 21W (3.50)

Total inductor loss

The total inductor loss is:

Pinductors = (Pfe + Pcu) · 2 = (1, 21W + 10.44W ) · 2 = 23, 30W (3.51)

3.1.3 Transformer Design

The design of a transformer is an iterative process, where the major consideration is a tradeoff

concerning where to dissipate the power loss, in the core or in the windings. The number of turns is

the deciding factor in the ratio between the core loss and winding loss.

The core size is chosen by request of APC, for similarity reasons with there currently used

DC-DC converter, in the application that this DC-DC converter, in future prospect could replace.

The core is an ETD49 with 3C90 as ferrite material. A ferrite core usually saturates at 300mT, the

chosen material saturates 380mT at 100C, but for the core loss point of view the flux density is

chosen to 220mT, which gives a nice margin.

Copper loss calculations

The primary peak voltage is largest at Vin_max (60V). From the duty-cycle calculations in section

3.1, the transformer voltage can be found to be:

32


Figure 3.9: Primary voltage in one switch cycle

The peak primary voltage per transformer is found by:

Vpri =135V

2= 67, 5V (3.52)

The "on" time is calculated as:

Ts(on) = 0, 44 · Ts = 0, 44 · 22µs = 9, 7µs (3.53)

and with the flux density decided, the number of primary turns can be found to be:

Npri =VT (on) · Ts(on)

2 ·B ·Ac=

67, 5V · 9, 7µS

2 · 0, 22T · 209 · 10−6m2= 7, 12 ≈ 7 (3.54)

where Ac is the cross sectional area of the core and B is the flux density. As the transformer ratio is

1:3, the secondary number of turns is given by:

Nsec = 3 ·Npri = 3 · 7 = 21 (3.55)

Winding is made with isolated copper wire, chosen with a diameter of 0,7mm. With the isolation

however it’s more like 0,8mm. The winding chamber of an ETD49 coil former is 32,7mm wide.

Which allows each layer to have 5 wires in parallel and 7 turns. By using several smaller wires

in parallel, instead of one wire with a large diameter, more of the wire cross sectional area will be

utilized, and the skin effect will be minimized. The transformer will be made with a total of 6 layers,

three connected in parallel as the primary side and three in series as the secondary side.

The fill factor Ku is the fraction of the core window area that is filled with copper, and is

33


Figure 3.10: Winding chamber of an ETD49 coil former

calculated as:

Total copper area = Aw · number of wires in parallel · number of turns (3.56)

= 0, 352 · π · 5 · 7 (3.57)

= 80, 82mm2 (3.58)

AW is the cross sectional area of the wires, or bare area, and WA is the winding window area. It is

stated in the data sheet to be 273mm2.

Ku =Total copper area

WA=

80, 82mm2

273mm2= 0, 30 (3.59)

A fill factor of 30% is ok for this application, because of the use of round wires and extra isolation

between the layers.

The copper losses will be largest at at VIN = 30V, hence the highest current.

Ipri_rms =

√Dtrafo ·

(Itrafo

2(two parallel sets of transformer)

)2

(3.60)

=

√0, 22 ·

(71, 33A

2

)2

= 16, 73A (3.61)

with the transformer ratio this entails the secondary current to be:

Isec_rms =Ipri_rms

3=

16, 73A

3= 5, 58A (3.62)

To calculate the copper loss it is necessary to know the resistance of the winding conductor. The

34


DC resistance can be expressed as:

RDC = ρ · lb · nAw

(3.63)

Where ρ is the resistivity and equal to 0,023mm−Ω at 100C. lb is the average length of a turn and

stated to be 0,085mm the ETD49 core. n is the number of turns and Aw is the wire cross sectional

area. The primary and secondary winding resistance is respectively calculated to:

Rpri_DC = 0, 023mm− Ω · 0, 085mm · 7turns

0, 35mm2 · π · 5wires · 3layers= 2, 4mΩ (3.64)

Rsec_DC = 0, 023mm− Ω · 0, 085mm · 21turns

0, 35mm2 · π · 5wires= 21, 5mΩ (3.65)

However to calculate the power loss more accurately, the skin- and proximity effect, as discussed

earlier, has to be taken into consideration. The copper loss can be calculated as the following:

Pcu = Ppri + Psec = I2pri_rms ·Rsec. DC · FR_pri + I2

sec_rms ·Rsec_DC · FR_sec (3.66)

FR is the correction factor that can be found via figure 3.11. As it can be seen the number of layers

can have significant impact on the copper loss. There are ways of minimizing the proximity effect,

and thereby the correction factor. One way is to interleave the windings, which means that the

windings should be wound alternately. In this way the MMF, magnetomotive force, induced by the

winding currents are equalized, see figure A.1 in appendix A for an illustration, and the copper loss

for the entire winding can be determined by figure ref3.11 with M = 1[2].

The factor ϕ can be calculated as:

ϕ =h

δ· √η (3.67)

where h = dcu ·√

π4 is the hight of the wire and η is the winding porosity or the fraction of the

width of the winding chamber that is filled with copper. The penetration depth, δ was found to be

0,35mm at 45kHz, for copper. The porosity can be determined by:

η =√

π

4· dcu ·

npri

lw=

√π

4· 0, 7mm · 5 · 7

32, 7mm= 0, 66 (3.68)

dcu is the diameter of the wires and npri is the number of turns in a layer. lw is the width of the

winding chamber. As it is the same wire size used for the primary and secondary windings and it is

the same number of turns per layer, the porosity is the same. The factor ϕ is then also the same for

35


Figure 3.11: Correction factor for the transformer resistance as a function of ϕ and number of layers M

both windings, as the penetration depth of the primary windings is equal to the secondaries:

ϕ = ϕpri = ϕsec =√

π

4· 0, 70, 35

· √η = 1, 44 (3.69)

In the graph 3.11 at ϕ = 1,44 the correction factor can be found to be 1,35 and the copper loss can

be determined:

Ppri = 16, 732 · 2, 4mΩ · 1, 35 = 0, 91W (3.70)

Psec = 5, 582 · 21, 5mΩ · 1, 35 = 0, 90W (3.71)

The total copper power loss per transformer is then:

Pcu = 0, 91W + 0, 91W = 1, 82W (3.72)

36


Core loss calculations

The core loss is calculated with the same method as in formula 3.48 for the inductors. Figure 3.12

shows the graph for the core loss per volume vs. the flux density for 3C90.

Figure 3.12: Core loss density curve, for 3C90

A straight line is drawn at 45kHz. The volume of an ETD core is 24000m3 and the flux density

is chosen to 220mT. At 45kHz the core loss equals:

Pfe = 24 · 10−6m3 · 230 · 103W/m3 = 5, 52W (3.73)

At the expected operating temperature of the core of 60 − 80C the loss will be slightly higher

according to figure 3.13 that shows the power loss for several frequency/flux density combinations

as a function of temperature, but impossible to with out an accurate graph for the given situation.

The total theoretical power loss per transformer can be calculated as:

Ptrafo = Pfe + Pcu = 5, 52W + 1, 82W = 7, 34W (3.74)

For the total converter this equals a loss of:

Ptransformers = 7, 34W · 4 = 29, 36W (3.75)

37


Figure 3.13: Core loss frequency/density curve vs. temperature, for 3C90

3.1.4 Output Diode Rectification

The chosen output diodes are fast recovery diodes of the type DSEI 30-06A, which are 600V and

37A diodes in a TO247 house. The loss in one diode can be calculated by:

PD = VD · ID_avg (3.76)

VD is the forward voltage drop of the diode the moment it starts to conduct and is found to be

0,8V according to figure 3.14, with the instantaneous value or peak value of the forward current.

ID_avg is the average current the diode conducts during one switch period. Unfortunately there

was not time to implement the bidirectional part of the DC-DC converter, so the IGBT’s where

replaced by diodes on the output. This means that there are two diodes conducting at a time, and

four for each output in one switch cycle. The peak current in the diode can be calculated as:

ID_peak =Iout

Dtrafo· 14

(four diodes conducting in one switch cycle) (3.77)

=5A

0, 22· 14

(3.78)

= 5, 68A (3.79)

38


Figure 3.14: Forward current versus voltage drop

The average current for one diode can be calculated as:

ID_avg =Iout

4=

5A

4= 1, 25A (3.80)

and the forward conduction loss is found to be:

PD = 1, 01V · 1, 25A = 1, 26W (3.81)

Which means that the total power loss in the rectifier diodes is given by:

Prectifier = PD · 8 = 1, 26W · 8 = 10, 1W (3.82)

3.1.5 Output Filter

The chosen output capacitors are two 250V electrolytes with 1500µF . One for the +200V output

and the other for the -200V output. The current through one capacitor can be calculated as:

IC_rms =√

I2rectifier_rms − Irectifier_avg2 =

√(ID_rms · 4)2 − Iout2 (3.83)

The rms current of one diode can be found by:

ID_rms =√

(ID_peak)2 ·Dtrafo =√

5, 68A2 · 0, 22 = 2, 66A (3.84)

39


The output capacitor current is then:

IC_rms =√

(2, 66A · 2)2 + (2, 66A · 2)2 − 5A2 = 5, 62A (3.85)

The capacitor has a typical ESR value of 90mΩ and the total loss in the capacitors can be found by:

Poutput_capacitors = I2C_rms ·RC · 2 = 5, 62A2 · 90mΩ · 2 = 5, 69W (3.86)

3.1.6 Estimated Efficiency

The total loss of the power components can be seen in the table 3.1 below.

Component Type Power lossInput Inductors four 65µH and 36A rms 23,30WMOSFET’s irfp90n20d POWER MOSFET 87,73WTransformers four ETD49 with 3C90 29,36WOutput Rectifier eight DSEI 30-06A power diodes 10,10WOutput Capacitors two 250V electrolytes with 1500µF 5,69WClamp Circuit MOSFET, Diodes, Capacitor and inductor ca 20WTotal 176,18W

Table 3.1: Loss in power components

The loss for the clamp circuit is only an estimation, based on experience and a measurement

of the average current that is transferred back through the circuit of 5A. With an approximately

efficiency of 90% of the buck converter, an estimated guess is that the clamp loss is around 20W.

The theoretical efficiency of the DC-DC converter can be calculated by:

η =Pout

Pout + Ptotal_loss· 100 (3.87)

=2000W

2000W + 176, 18W· 100 (3.88)

= 0, 92 (3.89)

3.2 Control Design

At the predefined input voltage, 30-60V, the output voltage of the converter has to be maintained

constant at ±200. To achieve this the converter needs a control system. Figure 3.15 shows a simple

40

3.2. Control Design 41

block diagram of the converter with a control system. The control system is fed with an error signal,

e(t), that is the difference between a reference signal and the measured output voltage. From the

error signal the control system generates the PWM signals that control the switches in the converter.

Besides keeping the output voltage constant, the control system has to take the requirements of the

Figure 3.15: controller block diagram

sources feeding the inputs into consideration. Current overprotection of the fuel cell input is needed,

so until a "safe" voltage of the fuel cell input is archived, or a sudden load jump occurs, the needed

power has to be drawn from the ultracapacitor input.

Figure 3.16 shows a diagram of a control strategy based on the "feedforward" theory, where

besides the measurement of the output voltage current sense signal is used. This particular control

Figure 3.16: controller block diagram

strategy is called "current mode control", because of the current feedback loop. The advantages of

the current mode control is that you get a direct measurement, which makes it possible to implement

the current overprotection for the fuel cell input. The diagram also shows a switch driver circuit,

which is provided by APC. This driver circuit is isolated, which is needed for the ultracapacitor side

switches and the clamp circuit MOSFET.

As this part of the project has been delimited, because of continuing setbacks, the used control

41


for the testing of the circuit is not a current mode control strategy. However a diagram of the initially

intended control scheme can be viewed in appendix B along with a few calculations.

3.2.1 Constructed Control

The control used for testing the converter is consist of a two digital waveform function generator,

where it is possible to manually change the duty cycle of generated PWM signal. One is used for

the clamp MOSFET that is regulated so the clamp volage is below 160V at all times.

The other is used to generate two overlapping PWM signals via the circuit shown on figure ??The two PWM signals for the boost MOSFET’s is generated by using a 90kHz PWM signal from

Figure 3.17: Controller diagram

the digital waveform function generator and using it as the the clock signal for the flip-flop and as

input to the two NAND gates. The 90kHaz signal is delayed approximately by 100ns to the NAND

gate inputs. This delay is necessary because there is a propagation delay of 14-16ns from the clk

signal to the output occurs, in the flip-flop.

The flip-flops output Q is used for the upper NAND gate and the inverted output Q is used for

the lower NAND gate. Basically the flip-flop decides when the NAND gates can produce a value

on the output. By controlling the duty cycle of the 90kHz signal the duty cycle of the PWM signal

for the bosst switches can be regulated.

42

43

Chapter 4

Implementation, Measurements andPerformance

In this chapter the construction, and the basic consideration concerning layout of the converter is

explained. Hereafter the measurements that have been performed on the converter is described.

4.1 Layout of the DC-DC Converter

Figure 4.1 shows how the layout was done. Due to internal as well as external procedures of acquir-

ing the control print, it was decided to make the power board as seen on figure 4.1. It is constructed

on a plexiglas board with the dimensions of 40cm ·41cm, some of the connection is done with solid

wire and others, where more power is expected, is done with copper foil. The individual connector

size was determined by a rule of thumb saying; 15A per 1mm2.

The DC-DC converter is constructed between to heat sinks that was found in APC’s "junk"

collection. On each heat sink there is room for 16 semiconductors in either TO220 or TO247

housing. The boost MOSFET’s is placed so the heat dissipation is evenly distributed between the

sinks, meaning that switch 1 and 3 is on one sink and switch 2 and 4 on the other sink. The thermal

resistance of the heat sink is not known but it should not be a problem keeping the temperature

below the maximum of the individual component, as some forced air cooling also will be applied, to

simulated a more realistic environment. The clamp MOSFET, for each input, and it’s two associated

diodes is also placed on the heat sink accordingly. On the further most side to the right of the

converter the output diodes is placed.

The input supply can be seen on the left side of the board and directly after the input connections

43

44 Chapter 4. Implementation, Measurements and Performance

Figure 4.1: Picture of the DC-DC converter

the HAL sensor is placed which measures the input current. It is however not used in the testing

as the intended controller wasn’t available. The input inductors are the big red ones right after the

HAL sensor and the smaller inductors that can be seen is the clamp inductors. The four transformers

is placed approximately in the middle of the board. To the right, the two output capacitors is seen

and behind them, two ventilators is placed to produced airflow for cooling.

The driver circuit used for the MOSFET’s is galvanic isolated and designed by APC. They need

a ±15V supply and the PWM signals to operate. The ±15V is supplied by a external DC source.

4.1.1 Layout Considerations

The drivers for the MOSFET’s should be placed as close to the MOSFET’s as possible. This should

be done to minimize the inductance in the driver circuit. The inductance in the wires to the MOS-

FET’s could self-oscillation with the input capacitance in the MOSFET’s. To prevent this the MOS-

FET’s is supplied with individual gate resistors which should dampen the effect if it should arise.

The clamp loop have to be as small as possible otherwise it will induce further inductance in the

circuit, which again will raise the voltage across the MOSFET’s.

44

4.2. Efficiency of the converter 45

4.2 Efficiency of the converter

The control circuit described in section 3.2.1 constructed control, is used to test the converter effi-

ciency. As mention earlier, total duty cycle, of the push-pull MOSFET’s, regulation wasn’t possible,

due to limitation of the duty cycle the digital waveform function generator could deliver. Which

means that some of the measurement couldn’t be performed. The most important measurement was

however at low input voltage where it wasn’t a problem to regulated the duty cycle. See figures 4.2

for the efficiency measurements. It can be seen that the measured efficiency isn’t quite as high as

(a) Operating efficiency at Vin = 30V (b) Operating efficiency at Vin = 45V

(c) Operating efficiency at Vin = 50-58V

Figure 4.2: Operating efficiency of the converter

the expected 0,93. The extra losses can be explained, due to higher peak voltages across the boost

MOSFET’s than expected. This is probably because of the inductance in the clamp circuit.

45

46 Chapter 5. Discussion, Conclusion and Future Work

Chapter 5

Discussion, Conclusion and Future Work

A prototype was successfully constructed and a efficiency of 91% was archived at the worst case

scenario. This was archived even without a proper regulation control. The highest efficiency was

unfortunately not disclosed in the testing, due to lack of a proper regulation.

The prototype converter does however live up to it’s demand of converting the alternating input

voltage, 30V-60V to a constant output voltage,±200V at a powerlevel of 2kW with an efficiency of

91%. The measurements at high input voltage could not be performed due to instrumental limitation,

but I am confident that with the correct control scheme the converter would perform as expected.

With the high efficiency there are some perspective in the topology. It has the potential to

become a real contender for an fuel cell/ultracapacitor application.

With further investigations the efficiency could be even higher. a few ideas for improving the

converter is listed below:

• A proper design of cooling

• Professional circuit boards in multiple layers

• Implementation of a real regulation

46

BIBLIOGRAPHY 47

Bibliography

[1] Wilson C.P de Aragao Filho and Ivo Barbi. A comparison between two current-fed push-pull

dc-dc converters - analysis, design and experimentation. 1996.

[2] Robert W. Erickson and Dragan Maksimovic. Fundamentals of Power Electronics. 2001. Sec-

ond Editiion.

[3] A. Hansen and H. Havemann. Højspændingskontaktregulatorer af forward-converter typen.

http://www.answers.com/topic/maxwell-s-equations.

[4] Claudio Rossi. Application of supercapacitors in fuel cells based ups, 2005.

[5] Adrian Schneuwly. Properties and apllications of supercapacitors from state-of-the-art to future

trends, 2000.

[6] Raphael Waeber, 2006. Director Sales and Marketing Boostcap Euorpe.

47

48 Chapter A.

Appendix A

A.1 Magnetomotive force in the transformers

There are ways of minimizing the proximity effect, and thereby the correction factor. One way is

to interleave the windings, which means that the windings should be wound alternately. In this way

the MMF, magnetomotive force, induced by the winding currents are equalized, see figure A.1 for

an illustration.

(a) (b)

Figure A.1: Behavior of the MMF in a transformer

48

49

Appendix B

B.1 Leakage inductance in the transformers

The primary and leakage inductance of the transformers was measured with a instrument called

"LCR meter(LCR-819)" from GW instek. The transformers quality factor Q is also measured. The

leakage inductance was measured with the secondary side short circuited:

T1 :

Lpri = 0, 205mH (B.1)

Q = 129, 8 (B.2)

leakage inductance = 0, 00021mH ≈ 0, 21µH (B.3)

T2 :

Lpri = 0, 197mH (B.4)

Q = 134, 2 (B.5)


T3 :

Lpri = 0, 209mH (B.7)

Q = 120, 5 (B.8)


49

50 Chapter B.

T4 :

Lpri = 0, 218mH (B.10)

Q = 118, 5 (B.11)


50

51

Appendix C

C.1 Control design

Figure C.1: Control block diagram

Equivalent output filter

To make it easier to calculate and simulate the control close loop, some estimation will be done.

Selected: Cout = 1500tF.

The input choke dos not configure in the equivalent model, because it can be calculated as a short

circuit, because diL/dt duC/dt. The choke will have a phase correction at plus 90 degrees, but

it will be at a frequency more than one decade above the f0 fore the converter close loop.

51

52 Chapter C.

Calculation of the equivalent output resistance Req

The output voltage of the PI regulator PI1 makes the limit for the switch current (I). The ratio

between VPI1 and dIin is given by equation C.1:

dVPI1 = dIin_puls ·GIsense (C.1)

• dVPI1 : voltage change at the output of the PI regulator

• dIin_puls : current change at the secondary side of the converter(rectifier)

• GIsense : Current feedback gain: 1/2000 x 75 x 2 = 75m times (will be

For dIin_puls @ 1V change at PI1:

dIin_puls =dVPI1

GIsense=

175dot10−3

= 13, 33A (C.2)

dIout_puls = dIin_puls ·Ntransformer = 13, 33 · 13

= 4, 44A (C.3)

The maximum middle output current dIout_avg, can now be calculated. Note that the max duty

cycle is at Vin max.

dIout_avg = dIout_puls ·Dtrafo_max = 4, 44 · 0, 44 ≈ 1, 96A (C.4)

Maximum average output current @ 1V change at PI1.

The equivalent output resistance can now be calculated as dVPI1 divided by the dIout_avg @

dVPI1 :

Req =dVPI1

dVPI1

=1V

1, 96A= 510mΩ (C.5)

The voltage sense gain can be calculated as Uref divided by Uout:

GIsense ≈4, 02V

400V≈ 10, 05mgg (C.6)

52

C.1. Control design 53

Calculation of output characteristic

Req = Xc =1

2 · π · f0_out · Cout·GIsense, atAout = 0db (C.7)

⇓ (C.8)

f0_out =1

2 · π ·Req · Cout·GIsense =

12 · π · 510mΩ · 1500µF

· 10, 05mgg = 2, 09Hz (C.9)

simulation of output characteristic

Figure C.2: Simulation model for the output characteristic

f0 for the control loop must be at least one decade below the switch frequency, to minimize the

phase correction from the switch frequency. The control loop don’t have to be quick, Therefore f0

is selected to be 50Hz, to gain higher stability.

The PI regulator gain will be calculated so that the close loop gain is one at f0. In that way will

the phase margin be −90 − 45. This will make a phase margin at 45r minus the phase correction

from other filters witch can be let out, because they are designed to have a f3db more than one decade

above f0 for the close loop. Calculation of gain for high frequency (A(f →∞)):

(A(f →∞)) = Aout(f0)− 3db ≈ 37, 6db− 3db = 34, 6db ≈ 53, 7times (C.10)

Calculation of R1 and R2:

A(f →∞) =R1

R2, selected:R1 = 1kΩ (C.11)

⇓ (C.12)

R2 =R1

A(f →∞)=

1kΩ53, 7

= 18, 6Ω ≈ 18, 2Ω (C.13)

53

54 Chapter C.

Figure C.3: Bodeplot of the output characteristic

Calculation of C1:

R1 = Xc(f0) =12 · πdotf0 · C1 (C.14)

⇓ (C.15)

C1 =12 · πdotf0 ·R1 =

12 · πdot159Hz · 1k = 0, 1µF (C.16)

To eliminate high frequency noise, is the high frequency gain reduced by C2. C2 is calculated, so

that the cross over frequency is more than one decade higher than f0. This inshore that it has less

than 3 degrees influence at the close loop phase margin.

Calculation of C2: The high frequency cross over frequency is selected to be more than 10 x f0:

(f3bd_high) =1

2 · πdot10n · 1k= 15, 9Hz (C.17)

54


Figure C.4: Close loop bodeplot

Slope compensation

It is not necessary to add slope compensation due to that the duty cycle cant be above 50%.

Control diagrams

55

56 Chapter C.

Figure C.5: Control sheet 1

56



57

58 Chapter C.


58



59

60 Chapter C.


60



61

62 Chapter D.

Appendix D

D.1 Pspice diagram of the converter

Control diagrams

Figure D.1: Pspice diagram of the converter

62

2 kw dual input dc-dc converter for fuel cells and...

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