2003 pa workshop 6 2 for websitepasymposium.ucsd.edu/papers2003/nanleiwangpaworkshop2003.pdf ·...
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
28V High Efficiency High Linearity InGaP/GaAs Power HBT
28V High Efficiency High Linearity InGaP/GaAs Power HBT
N.L. Wang, W. Ma, C. Dunnrowicz, X.Chen, H.F.Chau, X.Sun, Y.Chen, B.Lin, EiC CorporationI.L.Lo*, C.H. Huang*, M.H.T.Yang*, Visual Photonics Epitaxy Co. Ltd.C.P. Lee, National Chiao Tung Univ., Hsinchu, Taiwan
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
AgendaAgenda
Introduction28V Operation InGaP/GaAs HBT DesignCircuit Design and AssemblyExperiment ResultsConclusion
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
IntroductionIntroduction
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
28V InGaP/GaAs HBT Power Transistor
28V InGaP/GaAs HBT Power Transistor
BackgroundThe best InGaP/GaAs HBT designed for 3-8V operation achieved excellent linearity and 1010 hours @ Tj=150oC28V HBT was demonstrated as a discrete device for higher power operationFlip chip was attempted to reduce thermal resistance
EiC’s Present EffortBuild MMIC compatible with existing assembly approachDesign SOA (safe operation area) and ruggednessProvide high linearity
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
28V Operation InGaP/GaAs HBT Design
28V Operation InGaP/GaAs HBT Design
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Design of 28V InGaP/GaAs HBTDesign of 28V InGaP/GaAs HBT
BVcbo~70V, BVceo~35VConventional 100µm thick substrate MMIC approach is adopted Thermal resistance design of HBT layout was done with proprietary programSOA (Safe Operation Area) through proper ballasting was designed with another proprietary programInitial “wafer level reliability” study result is very similar to the low voltage InGaP/GaAs HBT
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2003 PA Workshop 6-2
Measured I-V Curve vs. Designed SOA for Ae=1500µm2
Measured I-V Curve vs. Designed SOA for Ae=1500µm2
Total Emitter Area 1500um2. This is the building block for larger size HBT
I-V Curve
050
100150200250300350400450
0 5 10 15 20 25 30 35 40 45 50Vce
Icc
(mA
) Ib=1mA
Ib=2mA
Ib=3mA
Ib=4mA
Ib=5mA
I-V Curve
050
100150200250300350400450
0 5 10 15 20 25 30 35 40 45 50Vce
Icc
(mA
) Ib=1mA
Ib=2mA
Ib=3mA
Ib=4mA
Ib=5mA
SOA boundary
Class A Quiescent Bias Point
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Power HBT DesignPower HBT Design
Multi-finger building block is paralleled in large size HBTPatented feed structure to provide minimum phase lag from the input feed to the HBT fingers and minimum variation of phase of RF signal at each finger
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Circuit Design and AssemblyCircuit Design and Assembly
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
On-chip Circuit DesignOn-chip Circuit Design
Bias circuit (based on current mirror), RF choke and input pre-match circuit are designed on the same chip with the power HBTTemperature compensation is achieved through the current mirrorOutput matching is done off-chipInput matching is completed by off-chip matching
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2003 PA Workshop 6-2
Basic Circuit DesignBasic Circuit Design
PartialInput
MatchingRFIN
ChokeVref Vbias
RFOUT
Temperature compensated
PartialInput
MatchingRFIN
ChokeVref Vbias
RFOUT
Temperature compensated
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
AssemblyAssembly
Standard MMIC assembly procedure is followed:– The IC die is 4 mil thick– AuSn eutectic attachment is used– 1mil gold wire bond connects the die to the hybrid
circuit
No reliability concern about the assembly approach
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Experiment ResultsExperiment Results
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
HighlightsHighlightsThermal resistance of 30-35oC/W was measured for the building block of Ae=1500 µm2 HBTOutput power scales with HBT size to 25W at 900MHz, while maintaining the efficiency over 60%.Two tone test IMD3 maintains below –40dBc until reaching saturation power.At 900MHz under CDMA2000 9 fwr ch condition, 4.5W with ηc=42% was measured with ACLR1=-45dBc / ACLR2=-58dBc, and 35% at ACLR1=-50dBcAt 2GHz under CDMA2000 9fwr ch condition, 0.5W with ηc=32% is achieved at ACLR1=-50dBcAt 2GHz under WCDMA, 23dBm with ηc=18% at ACLR1=-45dBc
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Temperature Compensated Bias Circuit
Temperature Compensated Bias Circuit
<9% change of Icq over –45 to +85oC rangeIcq vs. Temperature
0
10
20
30
40
50
-50 -25 0 25 50 75 100
Temperature, degC
mA
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Gain / Efficiency of HBT with Ae=1500 µm2
Gain / Efficiency of HBT with Ae=1500 µm2
Pout=36dBm, G=14dB, ηc=71% Pout=35dBm, G=13.5dB, ηc=67%
HVHBT Gain, Efficiency, 900MHz
0
2
4
6
8
10
12
14
16
18
20
10 15 20 25 30 35 40Pout(dBm )
Gai
n(dB
)
0
10
20
30
40
50
60
70
80
90
100
Effic
ienc
y
Gain Efficiency
Gain, Efficiency vs Pout, 2GHz HBT Ae=1500um 2̂
0
4
8
12
16
20
10 20 30 40Pout(dBm)
Gai
n (d
B)
0102030405060708090100
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Thermal ResistanceThermal Resistance
30 to 35oC/W thermal resistance is measured from the HBT of Ae=1500um^2Measurement relies on the Vbe vs.Temperature relationshipAt full power operation, temperature rise is 50oC
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
Output Power vs. HBT Size @900MHz
Output Power vs. HBT Size @900MHz
61687170ηc %
9.9213.1815.3416.8Gain(dB)
44413835Pout(dBm)
12000600030001500Emitter size
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2003 PA Workshop 6-2
Two Tone Test Result @ 2GHzTwo Tone Test Result @ 2GHzTwo Tone Test @ 2GHz HBT Ae=1500
-80
-70
-60
-50
-40
-30
-20
-10
0
10 15 20 25 30 35Pout (dBm) average power
dBc
IMD3 20mAIMD5 20mAIMD3 40mAIMD5 40mA
Two Tone Test @ 2GHz HBT Ae=1500
0
1020
3040
50
6070
8090
100
10 15 20 25 30 35
Pout (dBm) average powerm
A o
r %
Icc 20mAIcc 40mAEff 20mAEff 40mA
Single tone CW P1dB is 32.5dBm; Gss=13.2dB
Output power is average. Each tone power is 3dB lower; PEP is 3dB higher
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2003 PA Workshop 6-2
CDMA2000 Test ResultCDMA2000 Test Result
Efficiency is 32 to 35% at ACLR1=-50dBcAt 900MHz, 36.5dBm is achieved at ACLR1=-45dBc with 42% efficiency. 35dBm is achieved at ACLR1=-50dBc. HBT size is 4 building blocks.At 2000MHz, 27dBm is achieved with ACLR1=-50dBc from 1 building block.
HVHBT ACLR vs. Pout, Ae=6000, 900MHz
-80-75
-70-65-60-55
-50-45-40
-35-30
20 25 30 35 40
Pout(dBm)
AC
LR (d
Bc)
010
20304050
607080
90100
ACLR1 ACLR2 Eff
CDMA2000 ACPR vs Pout, 2GHz, HBT Ae=1500
-80-75-70-65-60-55-50-45-40-35-30
10 15 20 25 30Pout(dBm)
AC
PR(d
Bc)
0102030405060708090100
ACPR1 ACPR2 Efficiency
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
WCDMA Test Method 1WCDMA Test Method 1WCDMA ACLR vs. Pout, 2GHz, HBT Ae~1500um 2̂
-65
-60
-55
-50
-45
-40
-35
-30
10 18 20 22 24 26
Pout (dBm)
ACLR
(dBc
)
0
5
10
15
20
25
30
35
ACLR1 ACLR2 Efficiency
Peak to average ratio is 9.8dBP1dB is 32.5dBmAt ACLR1=-45dBc, Pout is 23dBm with 18% efficiency
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
ConclusionConclusionKey Advantages
InGaP/GaAs HBT achieves high efficiency: over 60% at 2GHzExcellent linearity under modulated signalsLong lifetime and stable gain is expected from the standard InGaP/GaAs HBT result
Major Achievement25W is achieved in the standard MMIC approachInGaP/GaAs HBT can be further developed to serve the high power / high reliability applications
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EiC Corp.Excellence in Communications
2003 PA Workshop 6-2
AcknowledgmentAcknowledgment
The authors like to thank Mr. Jerry Curtis for his encouragementMany colleagues’ invaluable support on this project is also acknowledged here