©2004 brooks/cole figures for chapter 15 reduction of state tables state assignment click the mouse...

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©2004 Brooks/Cole FIGURES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the book includes: Objectives Study Guide 15.1 Elimination of Redundant States 15.2 Equivalent States 15.3 Determination of State Equivalence Using an Implication Table 15.4 Equivalent Sequential Circuits 15.5 Incompletely Specified State Tables 15.6 Derivation of Flip-Flop Input Equations 15.7 Equivalent State Assignments 15.8 Guidelines for State Assignment 15.9 Using a One-Hot State Assignment Problems

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Page 1: ©2004 Brooks/Cole FIGURES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT Click the mouse to move to the next page. Use the ESC key to exit this

©2004 Brooks/Cole

FIGURES FOR

CHAPTER 15REDUCTION OF STATE TABLES

STATE ASSIGNMENT

Click the mouse to move to the next page.Use the ESC key to exit this chapter.

This chapter in the book includes:ObjectivesStudy Guide

15.1 Elimination of Redundant States15.2 Equivalent States15.3 Determination of State Equivalence Using an Implication Table15.4 Equivalent Sequential Circuits15.5 Incompletely Specified State Tables15.6 Derivation of Flip-Flop Input Equations15.7 Equivalent State Assignments15.8 Guidelines for State Assignment15.9 Using a One-Hot State Assignment

Problems

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©2004 Brooks/Cole

Table 15-1: State Table for Sequence Detector

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Table 15-2. State Table for Sequence Detector

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Figure 15-1a: Reduced State Table for Sequence Detector

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Figure 15-1b: Reduced State Graph for Sequence Detector

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©2004 Brooks/Cole

Figure 15-2

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Table 15-3.

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Figure 15-3: Implication Chart

for Table 15-3

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Figure 15-4: Implication Chart After First Pass

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Figure 15-5: Implication Chart After Second Pass

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Table 15-4.

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©2004 Brooks/ColeFigure 15-6a: Graphs for Equivalent Circuits

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©2004 Brooks/ColeFigure 15-6b: Graphs for Equivalent Circuits

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Figure 15-7: Implication Tables for Determining Circuit Equivalence

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Figure 15-8

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Table 15-5. Incompletely Specified State Table

(c)

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Table 15-6.

X

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Figure 15-9a: Next-State Maps for

Table 15-6

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Figure 15-9b: Next-State Maps for

Table 15-6

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Table 15-7.

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Figure 15-10: Next-State

Maps for Table 15-7

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©2004 Brooks/ColeFigure 15-11: Derivation of S-R Equations for Table 15-7

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Table 15-8. State Assignments for 3-Row Tables

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Figure 15-12: Equivalent Circuits Obtained by Complementing Qk

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Figure 15-13: Equivalent Circuits Obtained by Complementing Qk

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Table 15-9.

A3 B3 C3

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Assignment “A“ Assignment “B" Assignment “C"J1 = XQ'2 J2 = XQ1' K1 = XQ2

K1 = X' K2 = X' J1 = X'

J2 = X'Q1 J1 = X'Q2 K2 = X'Q1'

K2 = X K1 = X J2= X

Z = X'Q1 + XQ2 Z = X'Q2 + XQ1 Z = X'Q1' + XQ2‘

D1 = XQ2' D2 = XQ1'D1 = X' + Q2'

D2 = X'(Q1+Q2) D1 = X'(Q2 + Q1) D2 = X + Q1Q2

Flip-Flop Input Equations

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Table 15-10. Nonequivalent Assignmentsfor 3 and 4 States

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Table 15-11. Number of Distinct (Nonequivalent) State Assignments

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Figure 15-14b

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Figure 15-15a: Next-State Maps for Figure 15-14

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Figure 15-15b: Next-State Mapsfor Figure 15-14

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©2004 Brooks/ColeFigure 15-16: State Table and Assignments

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Table 15-12. Transition table for Figure 15-16(a)

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©2004 Brooks/ColeFigure 15-17: Next-State and Output Maps for Table 15-12

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Figure 15-18: Partial State Graph