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Functional vectors are cre-ated against the behavioralmodel and are designed to exer-cise transactions, operations orbehaviors of the logic design.This is one level of abstractionremoved from the gate-level orschematic view of the designand two levels removed fromthe physical, layout or siliconview of the design. To assess thequality of the vectors, they mustbe graded or fault simulatedagainst fault models at the gatelevel or defect models at thephysical levelthe most com-mon grading, however, isagainst the stuck-at faultmodel. The grading requiresyet another simulation and thistime against a gate-levelmodeland then a selectionprocess to pick the vectors orpatterns that achieve the best

or targeted fault coverage; andto remove the patterns thatachieve redundant coverage.

In modern complex designs,the basic structural or sche-matic level verification uses themore efficient scan-basedstuck-at vectors for manufac-turing test and quality assess-mentthis leaves functionalvectors to be used for timing,speed performance or fre-quency verification purposes.However, scan-based vectorsare challenging this use as well.

Functional vectors can beused on a structural tester, butbecause the structural testersare optimized for the simplerapplication format and thelower data rate of the scan type

vector, then functional vectorsmust restrict the number ofedgesets/timesets supported.

Structural vectorsAs ICs increase in density andcomplexity and time-to-marketschedules continue to shrink,the prospect of pursuing a tra-ditional functional approach totest becomes problematic. Howcan design and test teams findthe time to develop functionaltest vectors for complex SoCswhen time-to-market pressuresare forcing them to increasefault coverage and the types offaults considered, and in lesstime with less available OSknowledge (you bought thatthird-party IP core because youdidnt have the time or expertiseto make it yourself)?

For an increasing number of

IC designs, a structured testmethodology offers a better al-ternative. In a structured testapproach, engineers use faultmodels based on verifying thestructure of the silicon ratherthan vectors based on verifyingthe behavior of the silicon. Thistype of testing can be per-formed using the static stuck-atfault model. Gates and wires areproven using design-for-test(DFT) in the chip and automat-ing vector generation and thevector gradin g process withEDA tools. Tests are developedby applying values to the gateinputs that toggle the suspecteddefective node to its oppositevalue (i.e. forcing a 1 on astuck-at 0 node) and then

applying values at the support-ing gate inputs that would allowthe good value to propagate toan observ ation point. If thevalue at the observation pointdiffers from the expected value,then a fault has been detected.

While not new, structuredtest methodologies have be-come an increasing popularapproach to test for a numberof reasonsautomated EDAtools that generate structuredtests reduce vector creationtime compared to traditionalfunctional test generation;available EDA tools can createvectors t argeting stuck-at, de-lay, bridging, opens, memorydefects, leakage and other ad-va nc ed fa ul t mo de ls , wh ichtranslate to higher qualitytests. Also, related tools facili-tate the generation of logic as-

sociated with scan, logic BIST,memory BIST and Iddq (leak-age testing).

Additionally, the vectorsused in a structural test arehighly portable and carry moreinherent design information.That is a key advantage in an IPcore-based IC design. Morecomprehensive vectors let testengineers organize tests, de-velop programs and conductdiagnosis with less familiaritywith the chip. Also, when struc-tured test architectures are cor-rectly implemented, they canprovide more coverage in fewervectors.

A structural testing ap-proach assumes that DFT is in-serted on-chip and requires

strict adherence to design rulesfor test. And it forces develop-ers to extend their developmentschedule with the time it takesto add and verify DFT and torun ATPG. There is a miscon-ception that DFT and ATPG aretime consuming; the truth isthat they are replacing tasksnormally accomplished aftertape-out. In fact, moving thesetasks to early in the design cycleconsumes considerably lesstime than it would take to gen-erate functional vectors andbuild a test program in the post-design phase.

Another advantage of struc-tural vectors is that all of themajor EDA tools output theIEEE 1450.1 standardtheStandard Test Interchange Lan-guage. Todays structuraltesters can accept this design

language directly withouttranslation and hence removeone of the major difficulties andopportunities for error injec-tion to the test program devel-opment process.

Stuck-at scan vectorsThe most common type of struc-tural vector is the scan vector.The vast majority of scan vec-tors are DC or stuck-at scan vec-tors that are produce by ATPGtools. If the design is a full-scan,all flip-f lops become part of thescan architecture and are orga-nized into scan chains or scanshift registers directly acces-sible from the pins of the part,and the vector generation iscombinational. If the design ismostly scan or partial scanwhere some flip-f lops are notpart of the scan chains, then thevector generation must includesequential analysis (the vectorgenerator must know how to

operate flip-flops in the func-tional sense). In addition, if thescan vector is to be used to testor verify at-speed or AC specifi-cations or behaviors, then ei-ther a sequential or pseudo-se-quential time-frame analysismust be conducted to create theat-speed sample cycle.

If the scan vectors are cre-ated randomly (assigning ran-dom logic values to scan chainelements)it doesnt matterwhether the vectors are appliedfrom the tester or from an on-chip pattern generator, such asa linear feedback shift registerthe application can be referredto as a BIST. In most cases, thescan vectors are created by de-

Figure 2: For aggressive designs, the method is to apply the shift operation slowly, and to then apply the

at-speed cycle between the last shift and the sample.

Shift test results out of scan registers atlow frequency (e.g. 50MHz)

Shift test pattern into scan registers atlow frequency (e.g. 50MHz)

Logic

Clock test pattern

through logic athigh frequency

(e.g. 400MHz)

Logic

Clock

Scan enable

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terministic toolsthe deter-minism being that the vector isdeveloped to target specificfaults. The stuck-at fault is thesimplest ATPG fault model andrequires that a net or node (gateinput or output) in the logic cir-cuit be adjudged to have astuck-at-one or stuck-at-zerocondition (as if shorted to Vddor Vss). To test this net or node,it must be driven to the oppo-site value (stuck-at-one must bedriven to a logic 0), and theval ue of the suspected faul tynode must be driven to an ob-serve point uniquely (the obser-vation could only be attributedto the propagation of the faulteffect). This requires the faultexercise and the propagationpath to be enabled by applyinglogic 1s to the off-path inputs ofAND type logic and logic 0s to

the off-path inputs of OR typelogic (Figure 4).

If the process of forward-tracing the fault effect, andback-tracing the enabling andfault exercise paths is taken toits conclusion, it can be seenthat the logic values end up ateither input pins or within scanflip-flops. The bits that areneeded to conduct the test dis-tributed in the scan chain arecalled the test-cubetheother bits may be randomlyfilled, also called padding. Thescan chain can be filled at anyfrequency, and is generally op-erated at just tens of MHz. Oncethe state is installed, the scanenable is de-asserted and afunctional response is al-lowed to occur for one clockcyclethen the scan enable isre-asserted and the result of thesample is shifted out. Thebits that represent the result ofthe test are called care-bits.

AC scan vectorsWith the advent of deep-submi-cron and nanometer fabricationprocesses, the stuck-at modelbegan to allow greater volumesof test escapes for chips in cer-tain design markets. This is be-cause process variation and de-fects now drive timing-relatedfailure conditions. In deep-sub-micron and nanometer designs,it is impossible to describe allfaults with a static fault modelsuch as the stuck-at model. Abetter model is the dynamicallyevaluated delay fault model.

While similar to the stuck-at fault model, the delay faultmodel embeds timing charac-

teristics and converts a timingweakne ss into a Boolean fail-ure (the wrong logic value ar-rives at the observe point at thesample time). One delay faultmodel is the gate or transi-tion delay fault model. It rep-resents itself as a pin value of agate element that acts as if ithas an STR or STF logic tran-sition, or as if an interconnectsignal has a greater than nor-mal propagation delay. A sec-ond fault model, the pathdelay fault is similar to the

gate-delay fault, but resolvesthe slow-to-rise and slow-to-fall concept to the last gate ina described path through apropagation path of severalgates and net connections.

A variety of defects thatcause errant timing behaviorcan be modeled as delay faults.These encompass resistivegate-oxide shorts and insuffi-cient doping which may resultin slow transistor switching; orincorrect routes that includeopen and plugged vias and openor malformed routes which mayresult in resistive propagationpaths. Metal bridges or shortedwire connections can also bemodeled as delays, but thecause is interfering contentionwi th ot he r sign al s. A s of tfault condition that must alsobe evaluated is the mutual-ca-pacitance induced crosstalksignal integrity problem.

Other defects also cause de-lay-like behaviors to show up inlogic such as power supplydroop, when power rails cannotdeliver enough power to drivelogic blocks or clock droopwhen a clock-tree driver is ofinsufficient drive strength orwhen the clock edge rate is laid-over. Some of these delays maybe so subtle that they cannot bedetected in non-critical paths.Though some subtle delays mayseem like an acceptable defector fault, this condition may

eventually lead to reliability is-sues or cause other weaknessessuch as excessive leakage.

AC scan is the use of scan-based techniques to conduct anat-speed sample cycle to verify

timing compliance and can beused to verify frequency com-pliance (speed binning) and pinspecification compliance (I/Otiming), and to detect manufac-turing-induced delay defects.Engineers verify frequencycompliance by ensuring that allcritical timing paths within aspecified range in a design meettheir specification in silicon af-ter manufacturingand thisanalysis is done on a per-end-point basis (an endpoint is aregister or an output pin) anduses critical paths extractedfrom static timing analysis. Pintiming specifications, such asinput-setup, input-hold andoutput-valid, are verified by

ensuring that the one worst-case longest path and the onebest-case shor test path per pinfalls within the specified setup-and-hold timing zone. To locatedelay defects, AC scan is used toexercise a number of paths perendpoint, similar to those forfrequency and pin specificationtiming, but with the focus thatnon-critical paths may incur adelay that now makes them thecritical paths.

The two AC scan fault mod-elstransition-delay that de-

tects STR and STF signals ongates and nets and is moresuited to determine gross de-lays, and path-delay which de-tects STR and STF signals overa complete described pathway

made of nets and gates and ismore suited to detect subtle de-lays on critical pathscan beused for all of the timing andfrequency verification tasks.

Both the transition delayand the path delay fault modelscan be analyzed and applied intwo timeframes to coincidewith the need for a vector pair.The first timeframe establishesthe fail value and launches atransition. The second time-frame captures the effect of thetransition. The launch-captureanalysis is supported by all pub-licly available ATPG tools.Whi le th e vec tor gener ationtechnology used in AC scan ismature, its application is not.

Figure 3: Launch on capture conducts two sample cycles instead of just one. A state is scanned into the part,

then a sample is conducted to change the launch bit in its register, and the next sample is conducted to

capture the at-speed result of the launched transition.

Shift test results out of scanregisters at low frequency

Shift test pattern into scanregisters at low frequency

Logic

Clock test pattern

through logic athigh frequency

Logic

Clock transitionpattern through

logic

ClockScan enable

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The main difference be-tween stuck-at scan and ACscan is the clocking. Clockingcan be implemented in manyways, but the requirement is foronly one at-speed clock pulse.For the mux-D flip-flop type ofscan, the scan test clock is usu-ally the system clockfor theLSSD type of scan, the scan testclocks are usually dedicatedtest clocks. The clockingshould be simple, but moderndesigns are anything but thatwith multiple clock domains,multiple frequencies, derivedclocks and huge clock distribu-tion trees that may have a load-ing of tens of thousands ofregisters.

For devices within the clock-ing capabilities of most com-mon testers, the clock isbroug ht in extern ally to th e

chip package through the sys-tem clock pin. This clock isused for both the shift and cap-ture clock, and is fairly straight-forward for designs that oper-ate under 400MHz. However,when dev ices have mor e ag-gressive frequencies than areeasily available from testers, orwh en br in gi ng the cl ock infrom outside of the chip re-quires an expensive high-speedpad, then the most commonpractice is to provide the systemclock from an embedded on-chip PLL or delay-lock loop(DLL). In this case, a clock pro-vided externally is just the ref-erence clock which should bemore in line with the capabili-ties of the tester; the internalclock applied to the system andin many cases to the scan archi-tecture, is the PLL clock. Theconcern here becomes thepower consumption at-speedfor both shifting and sampling.

Scan toggling can consumemore power than the part israted forand over-designingthe part to handle test poweris not efficient and can grow thedie unacceptably. So the chal-lenge is to provide a slow shiftclock and then allow for an at-speed sample clock. There aremany ways to provide this typeof clocking to the device.

Related to the clocking is theassertion and deassertion of thescan shift enable (SE) signal.There are two competing meth-ods for the SE applicationlaunch on shift (LOS) andlaunch on capture (LOC).Both methodologies are sup-ported by all popular EDA vec-

tor generation (ATPG) tools,but each has its own trade-offsand limitations.

Two techniquesOne of the common misconcep-tions in the industry is that youcan apply either the LOS or theLOC methodology with an ex-isting designed scan architec-ture. The physical scan architec-tures (scan bit order and scanenable) have different require-ments under each applied meth-odology. The LOS methodologylooks and acts exactly like regu-lar DC scan with only thesample interval changed. LOSwork s by stacking the vectorpair in the scan chain so that astate is installed in the scanchain on the next to last shift (n-1). The last shift replicates all ofthe state data and applies the

launch from the launch bit; thenthe SE is deasserted and thesample represents the capture.It is easy for the ATPG tool tocalculate what to put in the n-1spaces in the scan chain.

For designs with a slowermeasured frequency, the shift

and the sample clocks are ap-plied at the same frequency andthe entire operation looks justlike the stuck-at operation. Formore aggressive designs, themethod is to apply the shift op-eration slowly, and to then ap-ply the at-speed cycle betweenthe last shift and the sample(hence, LOS). When the at-speed cycle has a smaller inter-val th an th e shif t cycle, th etechnique is called cycle-switching or cycle-shrinking.When the at-speed cycle is per-formed by manipulating theduty cycle so that the last shifthas its launch clock late in theperiod and the capture cyclehas its capture clock early in thenext period, the technique isknown as clock-chopping orduty-cycle modulation. The keycritical problem with LOS is

that the SE must deassert be-tween the last shift and the nowat-speed sample cycleat highfrequencies this often makesthe SE a critical signal that canno longer be supplied by thetester. The fix for a critical SEis to treat it like a clock by mak-

ing a distribution tree and pos-sibly registering it internal tothe chipwhich now makes it aproblem for the ATPG tool.

The competing LOCmethod deviates from LOS byconducting two sample cyclesinstead of just one. A state isscanned into the part, then asample is conducted to changethe launch bit in its register(hence, LOC), and the nextsample is conducted to capturethe at-speed result of thelaunched transition. Similar tothe LOS, the sample cycles canbe appli ed as at-spee d clockcycles, or they can be applied asclock-chops or duty-cycle ma-nipulations. The key differenceis that only the LOC cycle is re-quired to be at-speed, and theSE is deasserted in the previouscycleit is no longer critical.

There are several pros andcons associated with LOS andLOC, and they can be seen asadvantageous to the softwareATPG tool or to the hardwarescan architecture. LOS is easieron the ATPG tool and results infaster runtime and more com-

Figure 4: The stuck-at fault is the simplest ATPG fault model and requires that a net or node in the logic circuit

be adjudged to have a stuck-at-one or stuck-at-zero condition.

Observation pathU21

U37

U46

U6

U3U74

U18U11

Exercise pathU55

A fault is selected (S@0 on output of U6) and the intent

is to drive it to the opposite valuelogic 1.

The exercise path is back-traced to the control points.

The propagation path is forward-traced to the nearest

observe point.

The enabling of the propagation path is back-traced

to the control points.

ATPG is unsuccessful when there are conflicts between

exercising the fault and propagating the fault effect.

S@0

Enable propagation path

1

x

x

0

x

1

1

1

0

x

1

1

0

1

1

SS

0S

S

0

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pressed vectors. However, it re-quires shift-bit independence(which may lead to non-optimalscan routing) to generate highcoverage and may produce vec-tors for invalid test-only orfalse paths. LOC requiresmore work from the ATPG tool(longer runtimes, less vectorcompression), but does not re-quire any particular bit order-ing in the scan chains. TheLOC allows for more hardwareoptimizations.

Scan architecturesThe configuration of the scanarchitecture can have a signifi-cant impact on the final form ofthe vectors and the amount ofmemory they require of the ATE.Though structural testers areoptimized to handle scan vec-tors, it is still possible to create

configurations or conditionsthat prohibit or complicate theuse of the vectorse.g. creatinga scan architecture that requiresshift operations at the PLL fre-

quency, which may be in the hun-dreds of MHz range or requiringmultiple edgesets. It is possibleto make a scan architecture thatexceeds even the deep scan drivememory supported by currentstructural testers.

In the past, scan vectorswere dee med unm anageablebecaus e of some mis con cep -tions and implementation er-rors that created inefficientscan architectures. For ex-ample, placing 60,000 flip-flops into one scan chain soonly one dedicated test pin-pairneeds to be supported (scandata in and scan data out) re-sults in only using one testerdata channel. If 2,000 scan vec-tors are applied, then thememory requirement of thatone channel is 120 millionclock cycles.

The maturity of the EDAscan insertion tools and an un-derstanding of the economicsof scan have resulted in moreefficient scan architectures.

Many scan chains using bor-rowed I/O pins (as opposed todedicated test pins) are com-mon as is the balancing of scanchains (making them all aboutthe same size). Other optimi-zations are partitioning timedomains into scan domains,not supporting load-and-parkand making scan lengthconfigurable.

During the vector generationprocess, many test rules (DRCs)are applied to ensure that thevectors can be delivered by thescan architecture and to assurethe safety of the created vectors:driven contention is prohibited,clocks cannot be used as dataand data cannot be used asclocks, and combinational feed-back is not permitted.

The most alarming problemis the effect that nanometer

technologies have on scan ar-chitectures. Route defects arethe most common problem innanometer processes and scanis a route-intensive architec-

ture. Accordingly, modern de-signs suffer from a high numberof broken scan chainsblockedscan chains where shift data isstopped or scan chains whichsuffer from hold time problemswher e bit-ski pping and data-smearing occur. This has re-quired that a new class of vec-tors be created to verify and rap-idly diagnose scan chains.

The sizing and complexity ofmodern ASICs and SoCs re-quire a remarkable array of vec-tors for comprehensive testingand to achieve the requiredquality levels. Todays designsrequire a mixture of functionaland structural vectors. How-ever, the structural content hasproven to be more efficient ingeneration, fault coverage andapplication. The use of struc-tural vectors does require that

DFT be supported, but the in-sertion of DFT and generationof vectors has become matureand is supported by all majorEDA vendors.