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Phase Noise and Spurious Sidebandsin Frequency Synthesizers

Christian Munker

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Version 3.2

December 20, 2005

[email protected]

mailto:[email protected]




2

Christian Munker Phase Noise and Spurious Sidebands in Frequency Synthesizers v3.2 December 20, 2005









Contents

I PLL Basics 9

1 Introduction 11

2 Around The Loop in a Day 13

2.1 Basic PLL Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 A Linear Model for the PLL? . . . . . . . . . . . . . . . . . . . . . 13

2.1.2 Excess Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1.3 A linear model! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 Type I PLLs (Averaging Loop Filter) . . . . . . . . . . . . . . . . . . . . . . 19

2.2.1 Type I, second order PLL . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.2 Time Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.3 Frequency Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.4 Type I, second / third order PLL, with one zero . . . . . . . . . . . . 25

2.3 Type II PLLs (Integrating Loop Filter) . . . . . . . . . . . . . . . . . . . . . 26

2.3.1 Type II, second order PLL . . . . . . . . . . . . . . . . . . . . . . . 26

2.3.2 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.3 Type II, third order PLL . . . . . . . . . . . . . . . . . . . . . . . . 30

2.3.4 Dual Path Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.4 Comparison of Type I and Type II PLLs . . . . . . . . . . . . . . . . . . . . 30

2.4.1 Type I PLLs (Averaging Loop Filter) . . . . . . . . . . . . . . . . . 31

2.5 Loop Filter Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.5.1 Averaging Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.5.2 Integrating Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6 Post-Filter and Higher Order PLLs . . . . . . . . . . . . . . . . . . . . . . . 34

2.6.1 Attenuation of Reference Frequency . . . . . . . . . . . . . . . . . . 35

3 PLL Building Blocks 37

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2.1 Analog Multiplier (Type 1 PD) . . . . . . . . . . . . . . . . . . . . . 38

3.2.2 EXOR (Type 2 PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.3 EXOR + FD (Perrott) . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.4 JK Flip-Flop (Type 3 PD) . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.5 Tristate PFD (Type 4 PD) . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.6 Hogge’s Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2.7 (Modified) Triwave Phase Detector . . . . . . . . . . . . . . . . . . 43

3.3 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3.1 Single Ended Designs . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3.2 The Dead Zone and How to Get Around It . . . . . . . . . . . . . . . 44

3.3.3 Charge Pumps and Two-State Phase Detectors . . . . . . . . . . . . 45

3.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.5 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3




4 CONTENTS

3.5.1 Dual Modulus Prescaler . . . . . . . . . . . . . . . . . . . . . . . . 47

3.5.2 Multi Modulus Divider . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.5.3 High-Speed Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.5.4 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.6 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4 Fractional-N PLLs 53

4.1 First Order Fractional-N PLLs . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.2 Higher Order Fractional-N PLLs . . . . . . . . . . . . . . . . . . . . . . . . 56

4.2.1 Sampling and Quantization . . . . . . . . . . . . . . . . . . . . . . . 56

4.2.2 Delta Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.2.3 Principle of Sigma-Delta Modulation (SDM) . . . . . . . . . . . . . 59

4.2.4 Different Architectures for Sigma-Delta Modulators . . . . . . . . . 63

4.2.5 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . 63

5 PLL Modeling and Simulation 65

5.1 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.1.1 Bilinear Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.2 1st Order Low Pass . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.1.3 2nd Order Low Pass . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.1.4 Third Order Low Pass . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.1.5 Integrating Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . 69

5.1.6 Loop Filter Modeling in VHDL . . . . . . . . . . . . . . . . . . . . 70

5.1.7 Loop Filter Modeling Using Exponential Functions . . . . . . . . . . 73

5.2 VCO Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3 Accuracy Limitation of Sampled / Quasi-Analog Models . . . . . . . . . . . 73

5.3.1 Amplitude Quantization . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3.2 Timing Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.4 Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.4.1 Event Driven Approach . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.5 Spectral Estimation of Simulation Results . . . . . . . . . . . . . . . . . . . 78

II Spurious Sidebands 81

6 Reference Frequency Feedthrough 83

6.1 FM / PM Modulation Basics . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.2 Sinusoidal Disturbance of Tuning Voltage . . . . . . . . . . . . . . . . . . . 85

6.3 Periodic Disturbances of Tuning Voltage . . . . . . . . . . . . . . . . . . . . 87

6.4 Sidebands Induced By DC Leakage Current . . . . . . . . . . . . . . . . . . 886.5 Narrow Pulses on the Tuning Voltage . . . . . . . . . . . . . . . . . . . . . . 90

6.6 The Magical Mystery Spur: Dividing Spurious Sidebands . . . . . . . . . . . 95

7 Other Sources of Spurious Sidebands 97

7.1 Spurious Sidebands Depending on the Output Frequency (α -Spurs) . . . . . 98

7.1.1 RF Leakage Into the System Frequency Path . . . . . . . . . . . . . 98

7.2 Spurious Sidebands Depending on the VCO Frequency (β -Spurs) . . . . . . 101

7.2.1 VCO / LO Leakage Into the System / Reference Frequency Path . . . 101

7.2.2 System Frequency Harmonics’ Spurious . . . . . . . . . . . . . . . . 102

7.2.3 Fractional-N Spurs . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.3 Spurious Sidebands Tracking the Carrier (γ -Spurs) . . . . . . . . . . . . . . 104

7.3.1 Reference Frequency Modulating the VCO . . . . . . . . . . . . . . 105

7.3.2 System Frequency Modulating the VCO . . . . . . . . . . . . . . . . 106

7.3.3 Reference / System Frequency Modulating the LO Distribution . . . 107




CONTENTS 5

7.3.4 LF Injection into the System Frequency Path . . . . . . . . . . . . . 108

7.4 Intermodulation Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8 Spurious of Fractional-N PLLs 111

8.1 Spurious Sidebands of First Order Fractional-N PLLs . . . . . . . . . . . . . 111

III Phase Noise and Jitter 115

9 Phase Noise and Jitter 117

9.1 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

9.1.1 Jitter of Driven Systems (PM Jitter) . . . . . . . . . . . . . . . . . . 117

9.1.2 Jitter of Autonomous Systems (FM Jitter) . . . . . . . . . . . . . . . 118

9.2 Jitter Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.2.1 Cycle Jitter (or Cycle-to-Cycle Jitter) . . . . . . . . . . . . . . . . . 1189.2.2 Period Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.2.3 Long-Term Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.2.4 Accumulated Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.2.5 Absolute Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.2.6 Allen-Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.3 Phase Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.4 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10 Noise In The PLL 123

10.1 Noise Transfer Properties of the PLL . . . . . . . . . . . . . . . . . . . . . . 123

10.1.1 The Famous PLL Noise Formula . . . . . . . . . . . . . . . . . . . . 125

10.2 Noise Contributors in the PLL . . . . . . . . . . . . . . . . . . . . . . . . . 127

10.2.1 Divider Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

10.2.2 Phase Detector and Charge Pump Noise . . . . . . . . . . . . . . . . 129

10.2.3 Reference Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.2.4 VCO Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

10.2.5 Noise of Loop Filter Resistors . . . . . . . . . . . . . . . . . . . . . 132

IV Related Fields 137

11 Modulation and Demodulation 139

11.1 Digital Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.2 Digital Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

V The Toolbox 141

A Fourier and Laplace Analysis and Synthesis 143

A.1 Fourier Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

A.2 Fourier Integral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

A.3 Discrete / Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . 145

A.4 Some Fourier Transformations . . . . . . . . . . . . . . . . . . . . . . . . . 146

B Noise 149

B.1 Statistical Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

B.2 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

B.3 Flicker Noise (1/f Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

B.4 Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151




6 CONTENTS

B.5 Bandlimited Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

C Switching and Sampling 153

C.1 Switched Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

C.2 Sampled Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

C.3 Switched (Cyclostationary) Noise . . . . . . . . . . . . . . . . . . . . . . . 154

C.4 Intermodulation of Two Frequencies . . . . . . . . . . . . . . . . . . . . . . 158

C.5 Clipped Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

D FM / PM Signals 161

D.1 Sinusoidal Modulation Signals . . . . . . . . . . . . . . . . . . . . . . . . . 161

D.2 Periodic Modulation Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 162

D.3 Phase / Frequency Shift Keying . . . . . . . . . . . . . . . . . . . . . . . . . 164

D.4 Statistical Modulation Signals . . . . . . . . . . . . . . . . . . . . . . . . . 164

E Signal Energy and Power 167

E.1 The Basics: Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

E.2 The Basics: Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

E.3 Power of a Periodic Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

E.3.1 Calculation of Signal Power in the Time Domain . . . . . . . . . . . 168

E.3.2 Calculation of Signal Power from the Auto-Correlation Function . . . 169

E.3.3 Calculation of Signal Power in the Frequency Domain . . . . . . . . 169

E.4 Power of Statistical Processes . . . . . . . . . . . . . . . . . . . . . . . . . . 169

E.5 Power of FM / PM Modulated Signals . . . . . . . . . . . . . . . . . . . . . 170

F Second Order (PT2) Approximation 173

F.1 Basic PT2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

F.2 PT2 System with a Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

G Bits and Pieces 177

G.1 Normal Distribution and Error Function . . . . . . . . . . . . . . . . . . . . 177

G.2 Bessel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

G.3 Trigonometric Theorems and Identities . . . . . . . . . . . . . . . . . . . . . 181

G.4 Quadratic Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

G.5 Differentials and Integrals . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

H Variable and Acronym Definitions 185




CONTENTS 7

PrefaceThe most exciting phrase to hear in

science, the one that heralds new

discoveries, is not ”Eureka!” (I

found it!) but ”That’s funny...”

Isaac Asimov

The purpose of computing is insight,

not numbers.

R.W. Hamming, Numerical

Methods for Engineers and

Scientists.

The spark which started off this script was a commercial, three day course on PLLs which

I attended back in the year 2000. The material of the course was so badly organized and

contained so many errors that I grew angry and thought ”I can do better than that!”.

It turned out that this was not so easy to achieve but I tried to write down the basics, little

secrets and the dirty tricks of PLL design while learning them myself. In the beginning I did

this to structure the complex material for myself, later on colleagues got interested and now

the basic theory chapters also serve as a compendium for students attending my PLL lectures.

My goal of working as an engineer always is to boil problems down to a level of complexity

where it can be tackled using ”back-of-the-envelope” formulas. True, sometimes the enve-

lope has to be quite large, but I still believe in the old GIGO mantra: garbage in, garbage

out. Running complex simulations without understanding the basic mechanisms and model

limitations gives very accurate results - for a different reality. In a way, the power of modern

simulation tools and computers leads to less understanding because you are no longer forced

to work out the core of the problem manually.

Of course, computer simulations have become an essential part of PLL design. But be-

fore firing up the simulator, you should find a simulation methodology with a suitable level

of abstraction and simplification. Some theoretical background helps to decide whatever is

”‘suitable”’ for a given system. And after the simulation, results should be checked for plau-

sibility on the back of the famous envelope. Therefore, the chapter on PLL modeling will be

extended in the near future.

This script is a work-in-progress with lots of loose ends, nevertheless I hope it will help you

to get in ”loop”. Feedback ([email protected]) is most welcome!

Munich, February 2005,

Christian M¨ unker






8 CONTENTS




Part I

PLL Basics

9



Chapter 1

Introduction

It ain’t necessarily so...

George Gershwin

Frequency synthesizers are among the most critical components of modern communication

systems. They create the local oscillator (LO) signal that serves as the RF carrier to transmit

data over the air or some kind of wire-bound interface and to mix the received signal back

down into the baseband domain. Frequency synthesis is usually achieved using some kind of

phase locked loop (PLL) which locks the signal of a high frequency oscillator to the signal

of a stable reference oscillator with a selectable frequency ratio. In the future, direct digitalsynthesis (DDS) and RF analog-to-digital converters (ADCs) combined with advanced digi-

tal signal processing will find their way into more RF systems due to their superior channel

switching speed and reproducibility. Nowadays, these methods are still too power hungry

and expensive for most consumer wireless applications, therefore only PLLs are treated here.

An ideal carrier signal would be a pure sinusoid, showing a single spectral line. In reality,

there are always random noise and other disturbances, corrupting the signals. In the time do-

main, these disturbances show as jitter which e.g. reduces the “data eye” of a clock and data

recovery unit. In the frequency domain, noise broadens the signal spectrum, i.e. the carrier

now has a frequency distribution instead of one single line. It also shows as a “noise floor”,

far away from the carrier. Additionally, there may be discrete sidebands of the carrier, caused

by some periodic disturbance signal. These lines are called spurious sidebands (fig. 1.1).

Vctrl + ve

Vctrl

Tref

|S (f)|vco

f 0

f 0 ref −f f

0+f

ref t f

Figure 1.1: Disturbance of the VCO control voltage producing phase noise and spurious

sidebands on the VCO output

11



12 Introduction

Spectral purity has become very important as more and more network subscribers are being

tucked into the limited number of frequency channels, making bandwidth a valuable resource

that may not be wasted by spurious emissions. In order to use this resource most effectively,

frequency synthesizers have to fulfill ever increasing demands:

• Fast settling time: GSM and some other communications standards use frequency di-

vision duplexing (FDD) / time division multiple access (TDMA) which require chang-

ing frequencies between every receive and transmit slot. For optimum usage of time

and frequency slots, this “frequency hopping” has to be as fast and smooth as possible.

• Low phase noise: Wide band noise from the local oscillator can leak into other fre-

quency channels during transmission, disturbing other subscribers. While receiving,

local oscillator wide band noise can mix large signal disturbances down into the tar-

get channel, desensitizing the receiver. Noise within the channel bandwidth is also

unwanted because it increases the bit error rate (BER) for both receive and transmit

case.

• Low spurious sidebands: Unwanted sidebands of the receive / transmit center fre-

quency have similar effects as noise.

• Low power: Portable devices have only limited energy supplies, frequency synthesiz-

ers have to save power just like other building blocks.

These requirements have to be fulfilled with less (and less expensive) components in short de-

sign cycles to be competitive. However, phase locked loops are complex building blocks that

are hard to analyze in a strictly mathematical way and hard to simulate. This tutorial tries to

bridge the gap between precise computer simulations, giving little insight into system mech-

anisms, and between hand-waving simplifications allowing only qualitative answers based

on questionable assumptions. Currently, there is little material available covering the aspects

of spurious sidebands and phase noise generation in PLLs in depth while still keeping anengineering point of view:, complexity must be reduced to achieve an understanding of the

system that allows making the right design choices in a short time without losing too much

accuracy.

Part I reviews some PLL basics needed for the following analyses: chapter 2 takes a walk

round the loop and looks at PLLs from a control theory point of view, with the focus on

different loop filter architectures and their influence on settling time etc. A novel approach

is presented for approximating the influence of the loop filter on spurious and phase noise

performance that will be used throughout this tutorial. Chapter 3 covers the building blocks

of a PLL like phase detector, VCO etc. and their influence on system behavior.

Part II looks at the mechanisms of spurious sideband generation: chapter 6 starts with alittle modulation theory to explain how low frequency disturbances in the system can cre-

ate spurious sidebands in the radio frequency domain. Some typical examples of real-life

disturbances are analyzed, leading to simple equations that allow making intelligent design

decisions. Chapter 7 gives an overview of different disturbance mechanisms in PLLs, go-

ing a little further into the details of practical PLL design. In chapter 8, the specialties of

fractional-N PLLs concerning spurious generation are analyzed.

Part III deals with noise in PLLs: After an introduction to the concepts of phase noise and

jitter in chapter 9, chapter 10, covers the noise mechanisms in different blocks and their

contribution to the overall PLL noise.

Finally, Part IV is as a kind of ”toolbox” with some of the mathematical tools needed for

PLL analysis: Fourier analysis, noise and modulation theory etc. are explained in greater

detail than in the main parts.




Chapter 2

Around The Loop in a Day

Wichtig ist, was hinten raus kommt.

H. Kohl

Overview: This chapter gives an introduction to PLL behavior from a signal

/ control theory point of view. A simple, linear model is used to develop

concepts like bandwidth, phase margin and settling time. The focus is on the

different behavior for PLLs containing one or two integrators (type I / type

II). Finally, an approximation for loop filter transimpedance is derived that makes PLL analysis in the frequency domain easier.

2.1 Basic PLL Theory

2.1.1 A Linear Model for the PLL?

Essentially, a PLL is a strongly non-linear system, especially during the lock-in process.

Time-domain analysis is required to treat design problems like capture range or jitter sup-

pression. Simulations in the time domain are tedious, mathematical analysis is very difficult

if not impossible.

This makes small-signal analysis - i.e. regarding the frequency response - a desirable alterna-

tive: It gives valuable informations concerning loop stability (phase margin) and bandwidth,

settling time or noise transfer of a system. This is especially interesting for systems which

have to fulfill requirements concerning spectral purity like frequency synthesizers for wire-

less applications. The main advantage of small-signal analysis (as usual) are its simplicity

and speed, allowing back-of-the-envelope calculations and fast design optimizations. How-

ever, it requires a linear time-invariant (LTI) system - which a PLL (as initially stated) clearly

isn’t. Still, the benefits of this analysis are so dramatic that a lot of bold simplifications are

made just to run this analysis on a PLL:

•The signal frequencies at both inputs of the phase detector are the same. In reality, this

is only true when the PLL is in or near lock. Having only one frequency in the system1

1PLLs with a divider by N can also be treated as we’ll see soon.

13



14 Around The Loop in a Day

allows using the concept of phase and of complex frequencies.

• The reference frequency is at least 10 times higher than the PLL bandwidth. This al-

lows aproximating the discrete-time blocks (phase detector, divider) as time-continous

blocks.

• The changes in phase difference at the phase detector are so small that the building

blocks behave in a linear way. When the phase difference approaches ±π or ±2π (depending on the PD) the transfer function may become very non-linear and finally

even non-monotonous.

That settled, we’ll develop a linear model with simple behavioral models that predicts the

main dynamic features of a PLL. The different building blocks of a PLL will be discussed in

detail in chapter 3.

A more in-depth treatment of loop dynamics can be found in [ Gar79], [Bes98], [Roh97, pp.

1 - 78].

2.1.2 Excess Phase

Under these assumptions, signals in the loop are ”nearly periodic”, i.e. periodic with a phase

modulation φ e(t ):

s(t ) = A cos(ω 0t +φ e(t )) (2.1.1)

The total phase of the signal s(t ) is

φ 0(t ) = ω 0t +φ e(t ) (2.1.2)

As we assumed that the signals in the PLL have a constant frequency, the phase component

ω 0t merely rises in a linear way with time. This is somewhat boring and predictable - we are

more interested in deviations from this linear behavior: the deviation is called excess phase

φ e(t ). That is also the part the PLL operates on: The phase detector calculates the difference

between reference phase and divided VCO phase. If both signals have the same frequency

(which we have assumed), the linear phase term will cancel out:

∆φ (t ) =ω 0t +φ e,re f (t )

− ω 0t +φ e,div(t )

= φ e,re f (t ) −φ e,div(t ) = φ e(t ) (2.1.3)

From now on, when talking of ”reference phase”, ”VCO phase” etc. we will actually mean

their excess phase.

Note: Altough we have assumed a constant and common frequency in the system, the instan-

tanous total (angular) frequency of the signal s(t ) in (2.1.1) is

ω (t ) = ω 0 +∂φ e(t )

∂ t

.=ω e(t )

(2.1.4)

where the second part could be defined as ”excess frequency”.




2.1 Basic PLL Theory 15

2.1.3 A linear model!

With the exception of the loop filter we’ll just use a simple behavioral model of the buildingblocks in this chapter - let’s start with the phase detector (PD). We don’t care about the

implementation, it might be an analog or a digital type, with or without a charge pump -

it has two inputs for reference and (divided) VCO phase and an output whose average is

proportional to the phase difference of its two inputs. That’s all for the moment! The equation

describing PD behavior is deceivingly simple:

V PD,out (t ) = K φ ·φ re f (t )−φ div(t )

= K φ φ e(t ) (2.1.5)

The output of the phase detector is usually a voltage that pulses with the reference frequency.

We are only interested in slowly changing processes and regard its slowly changing average

voltage. From a system point of view, nobody will notice that we are cheating a little because

the loop filter does exactly this job - smoothing and averaging the phase detector output. The

proportionality factor K φ is called phase detector gain. In 2.1.5 we have silently assumed

that the PD has a voltage output - that is not necessarily so, it is only important that PD, loop

filter and VCO fit together.

In the frequency domain, the model is equally simple:

V PD,out (s) = K φ ·Φre f (s) − Φdiv(s)

= K φ Φe(s) (2.1.6)

Again, V PD,out (s) is the average PD detector voltage in the complex frequency domain.

Next in line is the loop filter - it has to be a low-pass filter, otherwise the loop won’t become

stable. Depending on system and requirements, the loop filter transfer function F (s) may

include one pole at the origin (integrator), some other poles and z zero(s) in the transferfunction. z must be less than the total number of poles p LF of the filter (otherwise it wouldn’t

be a low-pass ...). In general, the transfer function of such a low-pass can be written as

F (s) = K F (s + s z,1)(s + s z,2) · · ·(s + s z, z)

(s + s p,1)(s + s p,2) · · ·(s + s p, p)z < p (2.1.7)

In most PLL applications, the number of zeros z is 0 or 1, the number of poles p is rarely

higher than 3. The loop filter gain constant K F can have the dimension 1 (e.g. voltage in,

voltage out), but it may as well have the dimension of a transimpedance - current from the

charge pump is converted into a control voltage for the VCO.

The Voltage Controlled Oscillator (VCO) has an output frequency ω vco that depends on the

control voltagev

ctrl(t ) at its tuning input

2

. In our simple model, the VCO is characterizedby two constants: its free running frequency ω FR determines the output frequency when the

tuning voltage is zero. The gain factor K vco describes how much the tuning voltage changes

the output frequency:

ω vco = ω FR + K vcovctrl(t ) (2.1.8)

We are more interested in the output phase of the VCO than in its frequency which can be

derived by integrating its frequency:

Φ(s) =Ωvco(s)

s= K vco

V ctrl(s)

s(2.1.9)

The loop gain factor K O is the product of phase detector, loop filter and VCO gain factors,

K φ K F and K vco:2There are Current Controlled Oscillators (CCOs) as well.





K O

.= K

φ K

F K

vco(2.1.10)

The last block is the divider, which - per definition - divides the VCO frequency by N. This

block is only needed for frequency synthesis applications, it makes no sense for clock and

data recovery or skew reduction applications. Phase is also divided by N as it’s the integral

of frequency.

ω div(t ) = ω vco(t )/ N (2.1.11)

φ div(t ) = φ vco(t )/ N (2.1.12)

Now let’s put the blocks together: Figure 2.1 shows a block diagram of a PLL, fig. 2.2 its

control theory equivalent.

ω 0 , φ0

φ + ∆φref ref

φ +∆φ00

φ0

φ N=i

+

CP

PDF(s)

N

1cut hereto open loop

VCO

Divider

Loop Filter

Phase Detector /

Charge Pump

Figure 2.1: PLL block diagram

G(s)

H(s)

φ ref, φωvco vco

= φφdiv vco N

to open loopcut here Divider

PD / CP / LF / VCO

Figure 2.2: PLL block diagram - control theory point of view

Usually, the reference phase φ re f is regarded as the input and the VCO phase φ vco as the

output signal of a PLL (fig. 2.1). Then, the forward gain G(s) (no feedback path) is defined

by

G(s) =φ 0(s)

φ e(s)= K φ F (s)

K vco

s(2.1.13)




2.1 Basic PLL Theory 17

As the VCO is an integrator with regard to its output phase, there is an 1/s term in the open

loop gain (pole at the origin).

The feedback transfer function H (s) is defined by the divider ratio N

H (s) =Φdiv(s)

Φvco(s)= 1/ N (2.1.14)

The product of forward and feedback transfer function is the open loop gain GH (s) (open

feedback path) of the system as

GH (s) =Φdiv(s)

Φre f (s)=

K φ K vcoF (s)

Ns(2.1.15)

As the loop filter transfer function F (s) has to be a low-pass function, the open loop gain

GH (s) also has a low pass characteristic. Its order p - which is also the order of the PLL -is the total number of poles in the open loop transfer function GH (s). It is equal to the order

of the low pass filter p LF plus one due to the VCO acting as an integrator. If the loop filter

contains another integrator, the PLL is called a Type II PLL. A “normal” loop filter without

integrator gives a Type I PLL - and there is no such thing as a Type III PLL because systems

with more than two poles at the origin (=integrator) are always unstable. Even Type II PLLs

have an open loop phase shift of 180 at low frequencies and must be stabilized by introduc-

ing a zero (which brings the phase back down) in the loop.

Now we close the loop and look at the closed loop tranfer function T (s):

T (s) =Φvco(s)

Φre f (s)

=G(s)

1 + GH (s)

=K OF (s)

s + K OF (s)/ N

(2.1.16)

First, we look at the frequency domain and do a “straight line approximation” to get a feel for

the PLL behavior. The frequency where the magnitude of the open loop gain becomes one,

|GH ( jω )| = 1, is called open loop bandwidth or unity gain frequency f c. f c is an important

parameter in PLL (and most other control systems) design. It is also roughly the frequency

where the magnitude of the closed loop gain starts dropping. The sampled principle of digital

PLLs introduces an additional delay of approx. 1/2 f re f which deteriorates the phase margin

near the reference frequency. Therefore, the phase detector reference frequency f re f has to

be significantly higher than f c.

|T ( jω )

| ≈ N for ω ω c [|GH ( jω )| 1]

|G( jω )| ∝ (ω c/ω ) p− z for ω ω c [|GH ( jω )| 1]

This shows that all PLLs have roughly the same kind of closed loop transfer function (fig.

2.3): up to the open loop bandwidth f c, the open loop gain |GH (s)| 1 and the closed loop

gain T (s) is only determined by the division ratio N in the feedback path. Changes of the

reference phase appear multiplied by the divider ratio at the output. This is very similiar to

an OP-AMP circuit whose behaviour only depends on the feedback network up to a certain

frequency.

At frequencies above f c (outside the loop bandwidth), the feedback loop is no longer effec-

tive (|GH (s)| 1) and the transfer function is only determined by the forward gain function

G(s). In this frequency range, the PLL behaves like a lowpass of order p − z, the closed

loop transfer function drops with ( p−

z)·20 dB/dec. At frequencies around f c,

|T ( jω )

|may

exhibit peaking, depending on the phase margin.





f −3dB B

n

ω|C(j )| log

N log

f

−3dB

Figure 2.3: Closed loop gain |T ( jω )| and noise bandwidth Bn

The -3dB bandwidth B−3dB = f p of the closed loop gain is a very important parameter, it

specifies the maximum change rate of the reference signal the PLL output still can follow. Infrequency synthesis applications, the reference frequency usually isn’t changed or modulated,

here f p gives the bandwidth for noise components on the referencesignal to influence the PLL

output. A lower bandwidth gives a better reference noise suppression. The -3dB bandwidth

is defined as the frequency where

|T ( jω )| .= |T (0)|/

√2 = N /

√2 (2.1.17)

It also gives the maximum frequency up to which noise from the VCO is suppressed by the

control loop operation - for this noise component, a smaller bandwidth means worse noise

performance (see chapter 10 for details).

In general, it is not so easy to determine the closed loop behaviour from the open loop transfer

function. For a “well behaved” system with reasonable phase margin, open and closed loopbandwidth are approximately equal, f c ≈ f p. f c = f p when T (s) is a second order system

with a phase margin of 45.

For synthesizer applications, the system’s noise bandwidth Bn of the PLL is very important:

Bn =1

2π

∞

0

|T ( jω )|2 N 2

d ω (2.1.18)

Bn is the equivalent “brick-wall” bandwidth (see B.5) of the system for noise being added at

the reference input (∆φ re f ). Bn allows a quick calculation of the output phase noise θ 2no of a

PLL if the dominant noise contribution comes from the PD inputs (reference, divider & PD

noise) and has a flat noise power spectral density N 0:

θ 2no = Bn · N 0

Ps

· N 2 (2.1.19)

where Ps is the signal power at the PLL output.

For most applications, PLLs (and other control systems as well) can be approximated by a

second order system (appendix F) which is well known in control and system theory. This

allows calculating the bandwidth, settling time, amount of peaking etc. in closedform without

a great loss of accuracy, e.g.

T (s) =N

s2/ω 2n + 2(ζ s/ω n) + 1(2.1.20)

where ω n is the eigenfrequency of the closed loop and ζ is the damping ratio. Depending

on the PLL type, the denominator may have a zero. The transient behaviour (F.1.4) depends




2.2 Type I PLLs (Averaging Loop Filter) 19

strongly on the damping ratio ζ : For ζ = 0, the two poles of T (s) sit on the imaginary axis

and the system shows undamped oscillations at the frequency ω n. Increasing the damping

ratio ζ lets the poles wander towards the negative real axis on an arc (conjugate complex

poles). In the time domain, this corresponds to an exponentially damped sinusoidal signal.

Increasing ζ reduces the overshoot and also the frequency of the ringing (fig. 2.8). For ζ > 1,

the system is overdamped ; its step response will be an exponential decay with two time con-

stants. In the PLL world, the step response (F.1.4) describes the PLL frequency response

when the reference frequency or the divider ratio makes a jump.

2.2 Type I PLLs (Averaging Loop Filter)

The most simple version of a PLL is one with a simple RC (first order) filter. This filter

averages the output of the phase detector (PD). This filter adds a pole to the open loop transferfunction but no integrator, therefore, we get a Type I, second order PLL. Let’s have a look at

the transfer function:

log

Open

Loop

Gain

(dB)

Phase

21 c

n

0 dB

−180°

−90°

0°

−20db/dec

−60db/dec

−40db/dec

mφ

ωω ω

ω

ω

Figure 2.4: Bode plot for open loop gain T ( jω ) of type I, 2nd / 3rd order PLLs (no zero)

2.2.1 Type I, second order PLL

The transfer function of a first order loop filter (fig. 2.5) is:

F (s) =1

sT 1 + 1with T 1

.= R1C 1 (2.2.1)

The open loop transfer function GH (s) becomes

GH (s) =K O

Ns (sT 1 + 1)(2.2.2)

showing one pole at the origin and one at s = −ω 1 = 1/T 1. The magnitude of the open loop

gain transfer function is





R2

R1

R1 R2

C1 C2 C2C1

to VCO to VCO

I

= V

/ R 1

PD/CPPD

1st pole

2nd pole

1st pole

2nd pole

V

= I

R 1

P D

C P

P D

C P

Figure 2.5: Averaging loop filters of 1st / 2nd order (no zero)

|GH (s)| =

K O

N ω ( j −ω T 1)

=K O

N ω

1 ω 2T 21 −1

(2.2.3)

The closed loop transfer function becomes

T (s) =Φvco(s)

Φre f (s)=

G(s)

1 + GH (s)=

K OF (s)

s + K OF (s)/ N =

K Os/ω 1+1

s + K O N (s/ω 1+1)

= K O N sN (s/ω 1 + 1) + K O

= N s2 N /(K Oω 1) + sN /K O + 1

=N

s2/ω 2n + 2(ζ /ω n)s + 1=

N ω 2ns2 + 2(ζω n)s +ω 2n

(2.2.4)

⇒ s1,2 = −ω n(ζ ± ζ 2 − 1) = −ω n(ζ ± j

1−ζ 2) (2.2.5)

using the familiar notation from control theory for a second order system (see appendix F):

Natural Frequency and Damping Ratio for a Type I PLL

Natural Frequency : ω n.

=

K Oω 1

N (2.2.6)

Damping : ζ .

=N ω n2K O

=1

2

N ω 1

K O(2.2.7)

Depending on ω n and ζ , the output signal can be an exponential function, a damped sinusoid

or an undamped oscillation. The natural frequency ω n is the geometric average of loop gain

K O/ N and corner frequency of the loop filter, ω 1, i.e. some sort of gain-bandwidth-product .

It determines the frequency of oscillation (if there is one). The damping ratio ζ determines

how much damping there is in the system. Here, it directly depends on the loop filter band-

width and inversely on the loop gain

K O/ N - we’ll see that this is an undesirable correlation.





When s → 0, T (s) → 1 which means the PLL tracks slow changes of the input phase. For fast

changes (s→

∞), T (s)→

0, indicating that the PLL has a low-pass characteristic regarding

the reference input.

The inverse Laplace transform of (2.2.4) gives the impulse response φ vco,δ (t ) of the PLL.

Depending on the damping ratio ζ , the response is an exponential function (ζ ≥ 1), an ex-

ponentially damped sinusoid (0 < ζ < 1) or an undamped oscillation (ζ = 0). In praxis,

nearly all well-designed PLLs have a ζ of 0.3 . . . 0.9 because this gives the fastest settling

time together with an acceptable overshoot (as we’ll later see):

φ vco,δ (t ) =ω ne−ζω nt

1− ζ 2sin

1−ζ 2 ω nt

for 0 < ζ < 1 (2.2.8)

(2.2.5) shows what happens when you increase the loop gain GH (s): When K O/ N = 0, ω n iszero and ζ at infinity. The roots of the closed loop transfer function T (s) are the same as the

open loop poles, s1 = 0, s2 = −ω 1 (try evaluating (2.2.5) ... (2.2.1) for the limit K O/ N → 0).

Increasing K O/ N moves the roots on the real axis until they meet in the middle at −ω 1/2

when ζ = 1. From here on, the roots become complex and part from the real axis in a 90

angle, zeta decreases furtheron. This means, the pulse response of a type I, second order

PLL becomes more oscillatory with increasing loop gain but never becomes unstable. The

trajectory of the roots can be displayed in a so called root locus diagram (fig. 2.6). (2.2.4)

shows that the roots have a constant real part of −ω 1/2 and an imaginary part of

1−ζ 2ω nfor 0 ≤ ζ < 1.

ωj

ζ =

σ

ω ζ =

OK : 0 → ∞

1−ζ 2ωn

−ω =1 RC

1

cos θ

ω1

2n

θ

Figure 2.6: Root locus diagram for typ I, first order PLL

2.2.2 Time Domain

Keep in mind that the following calculations are only correct as long |φ e(t )| < φ max which is

the maximum phase error of the PD (usually π /2 or π , depending on the type of PD). Larger

phase errors cause a ”cycle slip”, i.e. the PD skips one cycle.

Final Value:

The final value theorem of Laplace theory (2.2.9) allows to predict the settling behavior of a

system:





Final Value Theorem

limt →∞

h(t ) = lims→0

sH (s) (2.2.9)

H (s) is the product of the stimulus and the system pulse response - H (s) could be the closed

loop transfer function T (s) (→ pulse response) or T (s)/s (→ step response) etc. Now, let’s

have a look what happens when our first order, type I PLL is treated with different stimuli:

limt →∞

h(t ) = lims→0

sT (s)

sk ; k = 0,1,2, . . .

= lims

→0

s1−k N

s2/ω 2n + 2(ζ /ω n)s + 1

=

0 for k = 0 (pulse response)

N for k = 1 (step response)

∞ for k ≥ 2 (ramp response)

(2.2.10)

What does this mean? A pulse disturbance of the input phase (k = 0) completely disappears

at the VCO output after a while, a phase step (k = 1) at the input appears multplied by N at

the output and a phase ramp (= frequency step, k = 2) leads to an infinitely increasing phase

at the VCO, i.e. a frequency change. This behavior is not surprising - it is exactly what a PLL

is supposed to do - and we’ll see that all PLLs behave in the same way.

Step Response

The case of step response is of special importance:

T ε (s) =T (s)

s=

1

s

N

s2/ω 2n + 2(ζ /ω n)s + 1(2.2.11)

For damping ratios between 0 and 1, the PLL will respond with an exponentially damped

sinusoidal ringing:

φ vco,ε (t ) = 1− e−ζω nt

1−ζ 2

sin

1− ζ 2 ω nt +θ

; θ = tan−1

1−ζ 2

ζ for 0 < ζ < 1

(2.2.12)

Its time constant is τ = 1/ζω n = 2T 1, the ringing frequency is

1−ζ 2 ω n. The steady-state

error ess of C ε (t ) approaches zero for t → ∞ which is good because this means that the phase

error will be completely eliminated in the end. How long this settling takes is an important

performance criterium: the settling time, T s, is defined as the time required for the system to

settle within a certain percentage δ of the input amplitude” [Dor92, p. 164] (fig. 2.7).

Settling and rise time can be calculated easily by ignoring the sinusoidal component of

(2.2.12):

Settling time and rise time for Type I PLL

T s = − ln(δ )τ = −2ln(δ )T 1 (2.2.13)

T r = (ln0.9− ln0.1)τ ≈ 4.4T 1 (10% → 90%) (2.2.14)





t

pM

pT sT

ess1+δ

δ1−

rT

c (t)ε

0.9

1

0.1

Overshoot

Figure 2.7: Step response parameters: Overshoot, settling and steady-state error

The amount of phase error peaking or overshoot M p,φ and the corresponding peak time T p,φ

can be obtained by calculating the maximum of (2.2.12) or the zero of (2.2.8). c(t ) becomes

zero when the sine function becomes zero, i.e. when nω nβ t = π . The maximum of φ vco,ε (t )occurs at n = 1:

Peaking time for Type I PLL

T p,φ =π

ω n

1− ζ 2

(2.2.15)

Now, the maximum can be calculated from (2.2.12):

Relative Maximum of Phase Error (Type I PLL)

M p,φ = φ vco,ε (T p) = 1 + e− ζπ √

1−ζ 2 (2.2.16)

For many applications, it is important to regard the phase error φ e(t ) = φ div(t )−φ re f (t ) at the

input. We define a phase error transfer function H e(s) as:

H e, I (s) =Φe(s)

Φre f (s)=

Φre f (s) −Φdiv(s)

Φre f (s)= 1− T (s)/ N

=s2 + 2ζω ns

s2 + 2ζω ns +ω 2n(2.2.17)

and use our stimulus signalsΦre f (s) = ∆c/sk again for pulse, step and ramp input (k = 0,1,2).

We’ll use the final value theorem (2.2.9) once more

limt

→∞φ e(t ) = lim

s

→0

sΦe(s)

= lims→0

s1−k s2 + 2ζω ns

s2 + 2ζω ns +ω 2n; k = 0, 1,2, . . .





= 0 for k = 0 (pulse response)

0 for k = 1 (step response)

∆c2ζ ω n

= ∆c N K O

for k = 2 (ramp response)

(2.2.18)

2.2.18 shows that a phase pulse or a phase step at the input disappears after some time. The

PLL as a control system gets rid of these disturbances. But what happens if the input of the

PLL sees a frequency jump of ∆ω = ∆c (e.g. by a change in the reference frequency f re f or

the division ratio N ? In the phase domain, this is equivalent to a ramp function, φ e(t ) = ∆ω t .

(2.2.18) predicts that the phase error will be different by ∆cN /K O after the disturbance, an

effect that creates problems for some applications.

2.2.3 Frequency Domain

In the frequency domain, the magnitude of the steady state response is

|T ( jω )| =N

(1−ω 2/ω 2n )2 + (2ζω /ω n)2(2.2.19)

ω n is the geometric mean of the open loop gain K O/ N and the -3dB frequency of the LPF

(1/T 1 = ω 1), i.e. it sort of indicates the Gain-Bandwidth product of the loop. ζ defines the

damping, i.e. how much overshoot and ringing the transient response has. Figure 2.8 shows

how ζ affects the step and frequency response of this type of PLL, the markers in the step re-

sponse show the time needed for 2% settling. The fastest settling is achieved with a damping

of ζ = 0.707.

Step Response

Time / Settling Time (ωn

t)

A m p l i t u d e

Bode Magnitude Diagram

Frequency (ω / ωn)

M a g n i t u d e ( d B )

0 5 10 150

0.5

1

1.5

10−1

100

101

−40

−30

−20

−10

0

10

ζ=2

ζ=0.3

ζ=0.71

− 4 0 d B / d e c

ζ=1ζ=2

ζ=0.5

ζ=0.3ζ=0.5

ζ=0.71

ζ=1

ζ = 0 . 7

1

ζ = 1

ζ = 0 . 5

ζ = 0 . 3

ζ = 2

Figure 2.8: Step Response and Frequency Response of Type I, 2nd Order PLL

The -3dB closed loop bandwidth can be calculated from (2.2.19) as





Closed Loop Bandwidth for Type I PLL

B−3dB [Hz] =ω n2π

1−2ζ 2 +

2−4ζ 2 + 4ζ 4 (2.2.20)

=ω n2π

for ζ = 0.707

For values of ζ < 0.707, |T (s)| exhibits peaking with a relative maximum of M pω at the fre-

quency ω p

Frequency Peaking of Type I PLL

M pω =1

2ζ

1−ζ 2(2.2.21)

ω p = ω n

1−2ζ 2 (2.2.22)

A high loop gain is desirable to suppress phase errors. Sideband or noise suppression usually

defines an upper corner frequency of the LPF. However, the damping is inversely proportional

to the loop gain, and damping values below 0.5 lead to excessive gain peaking of the loop

response and long settling times. This means, with a loop filter like that, loop gain K and the

time constant of the LPF T 1 cannot be chosen independently.

Noise BW Bn = 1/4K ???

2.2.4 Type I, second / third order PLL, with one zero

R1

R2

C1

C2

R2

C2

R1

C1

to VCOto VCO

I

= V

/ R 1

PD/CPPD

C P

P D

P D

C P

V

= I

R 1

1st pole / zero1st pole / zero

2nd pole 2nd pole

Figure 2.9: Averaging Loop Filters of 1st / 2nd order (one zero)

Type I PLLs do not need a zero in the loop filter transfer function but in some cases it is

helpful to obtain a larger loop bandwidth or to reach a special transfer characteristic (fig.

2.9). Especially when using a simple first order low-pass, the zero gives one more degree of

freedom to allow for choosing both K and T 2:

F (s) =sT 2 + 1

sT 1 + 1with T 1

.= ( R1 + R2)C , T 2

.= R2C (2.2.23)





log

Open

LoopGain

(dB)

Phase

ω

ω

ωω ωc

n

32 1

0 dB

−180°

−90°

0°

−40db/dec

−20db/dec

−20db/dec

−40db/dec

φm

ω

Figure 2.10: Bode Plot for Open Loop Gain GH ( jω ) of Type I, 2nd / 3rd order PLLs (one

zero)

As always, there is no free lunch: worse spurious and noise suppression is the price that has

to be paid for the extended bandwidth and higher flexibility that come with the zero.

2.3 Type II PLLs (Integrating Loop Filter)

A Type II PLL has an integrating loop filter which looks purely capacitive at low frequencies

(pole at the origin). The phase detector / charge pump combination needs to deliver a current

into the loop filter. Alternatively, the active loop filter topology (2.12b) first transforms the

voltage output of the PD into an current via R1 which is then integrated. Due to the inte-

grating behaviour, only special phase detector types can be used, most common is the use of

a phase / frequency detector with tri-state charge-pump output (type 4). Figure 2.12 shows

some realisations for such charge pump / phase detector / loop filter combinations. When the

PLL is in lock, the integral of the charge pump current over one reference cycle must be zero,

otherwise the loop filter voltage and hence the VCO frequency would drift away.

2.3.1 Type II, second order PLL

This PLL has two integrators in the loop (VCO and integrating loop filter), therefore it needs

a zero in G(s) to be stable:

F (s) =1

s

1 + sT 2

T 1(2.3.1)

For a charge pump + R2C 2 combination, T 1 = C 2 and T 2 = R2C 2, for an active integrator,

T 1 = R1C 2 and T 2 = R2C 2.

The resulting open loop transfer function is

T (s) =K

N

1 + sT 2

s2T 1(2.3.2)




2.3 Type II PLLs (Integrating Loop Filter) 27

log

Open

LoopGain

(dB)

Phase

ω ω

ω

ω ω2 c

n

1 3

0 dB

−180°

−90°

φm

−60db/dec

−40db/dec

−40db/dec

−20db/dec

−135°

ω

4th order

3rd order2nd order

Figure 2.11: Bode Plot for Open Loop Gain GH ( jω ) of type II, 3rd / 4th order PLL

R2

C2C3C1

C1

C2

C3

R3

R1

R2

R3

to VCO

to VCOPD/CP

PD

1st order

1st order

3rd order3rd order

2nd order

2nd order

−

+

b: Active Integratora: Charge Pump

Figure 2.12: Integrating Loop Filters of 1st / 2nd / 3rd order (one zero)

showing a double pole at the origin (one due to the VCO and one due to the integrating loopfilter) and a zero at s = −1/T 2 (solid line in fig. 2.11). The closed loop transfer function

becomes (using the notation of the PT2 approximation, appendix F)

T (s) =N (2ζ /ω ns + 1)

(s2/ω 2n ) + (2ζ /ω n)s + 1(2.3.3)

Once more we use the final value theorem (2.2.9) to estimate the settling behaviour at the

PLL output:

limt →

∞h(t ) = lim

s→

0s

T (s)

s

k ; k = 0, 1,2, . . .

= lims→0

s1−k N

s2/ω 2n + 2(ζ /ω n)s + 1





ωj

σ

(2)

OK : 0 → ∞

ωn

Figure 2.13: Root locus diagram for typ II, second order PLL

=


N for k = 1 (step response)

∞ for k ≥ 2 (ramp response)

(2.3.4)

We notice that the final values of a type II PLL are exactly the same as with a type I PLL -

a pulse disturbance of the input phase (k = 0) completely disappears at the VCO output, a

phase step (k = 1) at the input appears multplied by N at the output and a phase ramp (= fre-

quency step, k = 2) leads to an infinitely increasing phase at the VCO i.e. a frequency change.

This doesn’t come as such a big surprise as every PLL passes phase changes with a low-pass

characteristic (and maybe an amplification) from the input to the output. So, where’s the bigdifference between type I and type II PLLs?

We’ll see that the phase error at the input behaves in a very different way from the type II

PLL:

H ε , II (s) = 1− T (s)

N =

s2/ω 2ns2/ω 2n + 2(ζ /ω n)s + 1

(2.3.5)

Using our stimulus signals Φre f = ∆c/sk and the final value theorem (2.2.9) once more for

pulse, step and ramp input (k = 0,1,2) we get the settling at the PLL input:

limt →∞φ e(t ) = lims→0 sΦe(s)

= lims→0

s1−k s2/ω 2ns2/ω 2n + 2(ζ /ω n)s + 1

; k = 0,1,2, . . .

=


0 for k = 1 (step response)

0 for k = 2 (ramp response)

(2.3.6)

Due to the double integrator, a Type II PLL also manages to get the phase error back to zero

when a phase ramp (=frequency step) is applied.

2.3.2 Frequency ResponseThe magnitude of the steady state response is




2.3 Type II PLLs (Integrating Loop Filter) 29

|T (s)| =N

√??? (2.3.7)

Step Response

Time / Settling Time (ωn t)

A m p l i t u d e

Bode Magnitude Diagram

Frequency (ω / ωn)

M a g n i t u d e ( d B )

0 5 10 150

0.5

1

1.5

10−1

100

101

−20

−15

−10

−5

0

5

ζ=0.3

ζ=0.7ζ=0.5

ζ=1

ζ=2

ζ=1

ζ=0.3

ζ=0.5

ζ=0.7

ζ=2

ζ = 1

ζ = 2

ζ = 0 . 7

ζ = 0 . 5

− 2 0 d B / d e c

ζ = 0 . 3

Figure 2.14: Step Response and Frequency Response of Type II, 2nd Order PLL

again, using the abbreviations

ω n =

K O

NC 2(CP) resp. ω n =

K O

NT 2

R2

R1(Integrator) (2.3.8)

and

ζ =R2

2 K OC 2

N

(CP) resp. ζ =R2

2 K OC 2

NR1

(Integrator) (2.3.9)

the -3dB bandwidth of this loop is

B−3dB [Hz] =ω n2π

2ζ 2 + 1 +

(2ζ 2 + 1)2 + 1 (2.3.10)

= 2.1ω n2π

for ζ = 0.707 (2.3.11)

which is approximately twice as large as with a Type I PLL with the same ζ and ω n. The

noise bandwidth is

Bn =KR2 + 1/T 2

4(CP) resp. Bn =

K ( R2/ R1) + 1/T 2

4(Integrator) (2.3.12)





2.3.3 Type II, third order PLL

Another pole is introduced e.g. for improved reference spurious rejection by adding anothercapacitor in parallel to R2C 2 of the CP loop filter. The transfer function of the loop filter

becomes

F (s) =1

s

1 + sT 2

1 + sT 1(2.3.13)

2.3.4 Dual Path Loop Filters

The rather large loop filter capacitances of conventional integrating loop filters make the in-

tegration on a chip impractical and expensive. Dual path loop filters [CS98] allow reducing

the total capacitance by splitting up the loop filter. One filter path contains a low-pass RP,C Pand a charge-pump, the second one consists of an integrator and a second charge-pump with

reduced current. This allows reducing the integrator capacitance by the same amount as the

charge pump current. The signals of both paths are summed up and put through a post-filter

if needed.

Potential issues: noise due to reduced current and capacitance, mismatch between charge

pumps causes errors in loop gain and bandwidth

Figure 2.15: Dual Path Loop Filter

2.4 Comparison of Type I and Type II PLLs

The most important distinction is whether the PLL has an averaging or an integrating loop

filter, i.e. whether the PLL is of Type I or Type II:

Type I PLL loop filters show no integrating behaviour (non-integrating or averaging loop

filter). They have no pole at the origin, their transimpedance is resistive at low frequencies.

This means, the DC component of the output voltage is only determined by the duty cycle




2.5 Loop Filter Impedance 31

and the pulse amplitude of the input signal. The PD output has to pulse all the time to provide

the tuning voltage for the VCO.

Type II PLL loop filters include an integrator creating a pole at the origin ( integrating loop

filter). Therefore, the transimpedance at low frequencies is capacitive. The output voltage

depends on the history of the input signal - in locked state, only the non-idealities of PD /

CP create pulses and a ripple on the VCO control voltage. The phase detector usually has a

tri-state output.

The order of a PLL can be increased by using higher order loop filters. The higher order poles

may only become effective at frequencies above f c (or must be compensated by zeroes), oth-

erwise the loop will become instable. The benefits of higher order PLLs are a sharper roll

off of |C ( jω )| outside the loop bandwidth and hence a better noise / spurious performance.

In control applications, higher order PLLs permit better tracking of input signals. The draw-

backs are an increased sensitivity to component variations, a higher component count and of course the more difficult dimensioning.

2.4.1 Type I PLLs (Averaging Loop Filter)

The averaging loop filter in Type I PLLs (fig. 2.5) averages the output of the phase detector

(PD). This has some consequences:

• The PD must deliver voltage pulses into the loop filter because the VCO expects a

tuning voltage. If the PD/CP has a current output, this current must first be converted

into a voltage in a loop filter resistor (fig. 2.5).

•The pulse width at the output of the PD is proportional to the phase error at the input.

As the output voltage of averaging loop filters is proportional to the pulse width, TypeI PLLs always have a static phase error in lock. This phase error depends on the

VCO frequency (VCO control voltage is determined by the pulse width) and on the PD

output voltage (or PD/CP output current). This leads to a major drawback of Type I

PLLs: variations of the loop gain e.g. by thermal drift of the VCO characteristic cause

a phase drift that may be unacceptable for precision applications.

• The product of CP current and load resistor may be larger than the supply voltage

without clipping the signal. This is because the CP drives current into the load resistor

with a capacitor in parallel which “swallows” a part of the charge. As long as the duty

cycle does not become too large, the loop filter voltage will not reach the supply.

• The PD/CP are active for a much longer part of the reference period than they would

be in a Type II PLL. This favours injection of bias noise or other disturbances into theloop filter.

• The linearity of a Type I PD/CP in general is better then its Type II counterpart because

the ill-defined turn-on and turn-off phases of the CP are short in relation to the total

turn-on time.

• The open loop transfer function T (s) only contains one integrator - the VCO. This

allows a bigger variety of loop filter structures than in Type II PLLs where the transfer

function must have a zero to compensate for the second integrator.

2.5 Loop Filter Impedance

As seen in the last section, the loop filter has a lot of influence on the dynamic behaviour

of the PLL. Unfortunately, the math on the way is quite ugly. Before moving to the spectral





performance of PLLs, i.e. spurious sideband and noise behaviour, it would be nice to have

some handy approximations for the loop filter. The calculations in the frequency domain

can be ugly enough without the complexities of higher-order loop filters. Fortunately, it is

sufficient to look at the circuit well inside or far outside the PLL passband for most cases. In

these two ranges, loop filters can be approximated very nicely by their input impedance Z LF ,i

and transimpedance Z LF , i.e. the ratio of output voltage and input current. The first step is

to split the loop filter impedance into the input impedance Z LF ,i and the “post-filter” creating

the roll-off at higher frequencies. For phase detectors with current output (only these will be

regarded here), the loop filter input impedance acts as a “transimpedance” (current in, voltage

out). The post filter modifies this impedance by its attenuation | APF ( f )|:

| Z LF ( f )| = | Z LF ,i| ∗ | APF ( f )| (2.5.1)

This simplified analysis is only valid if the post-filter does not interact too much the input

impedance, i.e. when the post-filter does not shift the corner frequencies f 1, f 2 too much.

2.5.1 Averaging Loop Filter

In the simplest case (no zeros), the loop filter core is a simple one-pole low-pass (see fig. 2.5)

which looks like a resistor R1 at low and like a capacitor C 1 at high frequencies (fig. 2.16).

Higher frequencies are attenuated with a 1/ f or -20dB / dec. characteristic.

Loop Filter Impedance for Averaging Loop Filter (no zero)

Z LF ,i( jω ) = R11

1 + jω R1C 1=

R1

1 + jω T 1(2.5.2)

=

R1 for f f 1

1/ jω C 1 for f f 1(2.5.3)

with

T 1 = 1/2π f 1.

= R1C 1

LF,i|Z (f)|

fref

1R

f1

fc

log f

−90°

0°

φ

Figure 2.16: Impedance of Averaging Loop Filter (1 pole, no zero)

A zero in the filter (see fig. 2.9) makes things slightly more complicated - at low frequencies

the impedance is also resisitive, R1, around f 1 (pole) the impedance starts dropping and be-

comes capacitive. At f 2 (zero) the phase shift turns up towards zero and the input resistance

becomes resistive again, R1

|| R2 this time (fig. 2.17). This means, higher frequencies are at-

tenuated by only a limited amount R2/( R1 + R2). This effect produces a strong ripple on the

loop filter voltage and usually must be compensated by higher order post-filters.




2.5 Loop Filter Impedance 33

Loop Filter Impedance for Averaging Loop Filter with zero

Z LF ,i( jω ) = R11 + jω R2C 2

1 + jω ( R1 + R2)C 2

= R11 + jω T 2

1 + jω T 1(2.5.4)

=

R1 for f f 1

R1|| R2 for f f 2(2.5.5)

with

T 2 = 1/2π f 2.

= R2C 2; < T 1 = 1/2π f 1.

= ( R1 + R2)C 2

f1 fc f2 fref

R ||R21

1R

|Z (f)|LF,i

log f

−90°

0°

φ

Figure 2.17: Input Impedance of Averaging Loop Filter (1 pole and 1 zero)

(2.5.5) and fig. 2.16 show that Z LF has only one pole at s1 = −1/T 1 and a zero at s2 =−1/T 2. This leads to a mainly resistive behaviour of the transimpedance, with Z LF ≈ R1 at

low frequencies and Z LF ≈ R1|| R2 at high frequencies.

2.5.2 Integrating Loop Filter

Integrating loop filters have a mainly capacitive behaviour, i.e. they integrate the output cur-

rent from the charge pump and convert it into the VCO control voltage. The transimpedance

Z LF ,i( jω ) of an integrating three element / second order loop filter (see fig. 2.12) is given by:

Loop Filter Impedance for Integrating Loop Filter

Z LF ,i( jω ) =1 + jω R2C 2

jω (C 1 +C 2) −ω 2 R2C 1C 2

=1

jω C 1

1 + jω R2C 2C 1+C 2

C 1+ jω R2C 2

=1

jω bC 1

1 + jω T 2

1 + jω T 1with b

.=

C 1 +C 2

C 1(2.5.6)

=1

jω C ∗1(2.5.7)

with





T 2 = 1/2π f 2.

= R2C 2; > T 1 = 1/2π f 1.

=

R2C 2

b = R2

C 1C 2

C 1 +C 2

(2.5.6) shows that Z LF ,i( jω ) has one pole at the origin, one pole at ω 1 = −1/T 1 and a zero at

ω 2 = −1/T 23. The zero is always between the two poles. This means, Z LF ,i( jω ) is always

capacitive, except in the frequency range between ω 2 and ω 1.

C ∗1 is the equivalent loop filter input capacitance:

C ∗1 ≈ bC 1 ·1 + jω T 1

1 + jω T 2

= bC 1 ·

1 +ω 2T 21 1 +ω 2T 22

= bC 1 ·

1 + ( f / f 1)2 1 + ( f / f 2)2

≈

C 1 +C 2 for f

f 1, f 2

C 1 · f 2 f

for f 2 f f 1

C 1 for f f 1, f 2

(2.5.8)

f2

fc

f1

fref

1C

1C +C

2

fref

f1

f2

fc

1C*(f)LF,i

|Z (f)|

−90°

0°

log f log f

φ

Figure 2.18: Loop Filter Impedance / Effective Capacitance of Integrating Loop Filter

(2.5.8) and fig. 2.18 show that at very high frequencies only C 1 and at low frequencies the

sum of C 1 +C 2 is effective.

2.6 Post-Filter and Higher Order PLLs

PLLs using three-element loop-filters - especially those with averaging loop-filters - have

reference spurious sidebands that are too high for many applications. An additional RC

lowpass (“post filter”) creates an extra pole at s3 = −1/T 3 ≈ −1/ R3C 3, giving a third orderloop filter (see fig. 2.12), that attenuates these sidebands:

Z LF (s) =1

sbC 1

1 + sT ∗2(1 + sT ∗1 )(1 + sT 3)

(2.6.1)

It is assumed that the additional pole does not interact strongly with the pole at 1/2π f 2, i.e.

T ∗1 ≈ T 1, T ∗2 ≈ T 2. In this case, phase margin and lock-in time are not deteriorated and the

spectrum of the error signal ve(t ) is additionally attenuated by the RC low-pass consisting of

R3 and C 3:

| APF ,3( f )| =1

1 + f

f 32

≈ f 3

f for f f 3

3Note that the position of the pole and the zero have changed their places compared to the integrating filter.




2.6 Post-Filter and Higher Order PLLs 35

(20dB/dec.) - see also table 2.1. If the superposition principle is valid (i.e. for a low modula-

tion index), the spurious sidebands sk

of the VCO are attenuated by the same amount| A

3( f )

|.

Especially the reference frequency f re f needs to be attentuated by R3C 3, therefore f 3 must be

lower than f re f . For stability reasons, f 3 must be significantly higher than f 1.

f 3/ f 0.2 0.5 1 1.73 2 3 4 5 7 10

| APF ,3( f )| 0.98 0.89 0.71 0.5 0.45 0.32 0.24 0.20 0.14 0.1

| APF ,3( f )| (dB20) -0.2 -1 -3 -6 -7 -10 -12 -14 -17 -20

Table 2.1: Attenuation of RC Lowpass Filter

2.6.1 Attenuation of Reference Frequency

The loop filter converts input current pulses i(t ) into an output voltage ve(t ). This input

current has significant spectral components at the reference frequency that need to be sup-

pressed. Shape and spectrum of the current pulses look different for an integrating or an

averaging loop filter (fig. 2.19): For an integrating loop filter, the pulses are very narrow with

a width of T ABL or less. The amplitude of the spectral lines is quite low (low pulse energy due

to narrow width) but stays constant up to high frequencies (1/T ABL). For an averaging filter,

the loop filter voltage is equal to the average value of the pulses. Therefore, their pulse width

(and hence energy) has to be much higher, but the amplitude of the spectral lines drops much

faster (first zero at 1/T PWM ). In general (section 6.5), the spectrum of a rectangular pulse

train is given by (6.5.7)

ck = 2mα · sink πα

k πα = 2mα sinc(k πα ); k = 1,2, . . . where α = T w/T re f

For details see section 6.5.

TPWM

(w/T )ref

PWM2/T1/T

PWM

TABL

(w/T )ref

1/Tref

Tref 1/T

ABL

¡ ¡ ¡

¡ ¡ ¡

¡ ¡ ¡

¡ ¡ ¡

¢ ¢

¢ ¢

¢ ¢

¢ ¢

£

£

£

£

m

f

S(f)

t

s(t)

w

(a): Non−integrating loop filter

m

f

t

w

(b): Integrating loop filter

Figure 2.19: Spectra of Pulses for (Non) Integrating Loop Filter

EXAMPLE 1: Harmonics of short vs. long CP pulses

A charge-pump produces pulses of m = 1 mA at a reference frequency of f re f =200 kHz (T re f = 5µ s). The pulse width is T PWM = 2µ s (averaging loop filter)





resp. T ABL = 2ns (integrating loop filter):

Duty Cycle : α av = T PWM /T re f = 0.4

α int = T ABL/T re f = 4 ·10−4

Pulse Weight : wav = mT PWM = 2nAs (wint = 2pAs)

Fundamental : c1,av = 2mα avsinc(πα av) = 0.6mA

c1,int = 2mα int sinc(πα int ) = 80µ A

101st Harmonic : c101,av = 60µ A; c101,int = 80µ A

The energy content of very short pulses can be larger than the energy content of

wide pulses at higher order harmonics. In praxis, this is usually no problem be-

cause higher order harmonics are attenuated heavily by the loop filter. However,

when the charge pump is not properly isolated from the rest of the chip, these

higher harmonics may contaminate the chip via the supplies, bondwires or some

other form of capacitive coupling.

Usually, f re f f 1, f 2 so that the above approximations for Z LF can be used. In this case,

the complex loop filter impedance Z (s) can be approximated by the loop filter capacitor C 1(integrating LF or averaging LF without zero) or by the resistance R1|| R2 (averaging LF with

zero) (see above):

ve(t ) = ie(t ) ∗ Z ≈ 1

C 1

t

−∞ie(τ )d τ for f re f f 1 (2.6.2)

However, as soon as post-filters are used, the above integral becomes painful. Fortunately, itis much easier to calculate the voltage error at the output of the loop filter in the frequency

domain:

V e( jω ) = I e( jω ) · Z LF ( jω ) (2.6.3)

Due to the mainly resistive behaviour of the averaging filter, the reference feedthrough and

reference spurious sidebands are much worse than with an integrating loop filter with the

same bandwidth.




Chapter 3

PLL Building Blocks

If builders built buildings the way

programmers wrote programs, the

first woodpecker to come along

would destroy civilizations.

Anonymous

Overview: This chapter gives you an overview over basic building blocks of

an PLL like phase detector (PD), charge pump (CP), divider or VCO.

3.1 Overview

3.2 Phase Detector

There are different types of phase detectors with different phase and frequency behaviour.

[Bes98] has categorized them as type 1 ... type 4 (table 3.1), but it seems these categories are

not used outside of Germany. Nevertheless, [Bes98] gives a good overview.

All phase detectors produce an output signal of some sort that is proportional to the phase

difference at their inputs (that’s where the name comes from ...). The phase detector gain

PD type Multiplier EXOR EXOR + FD JK-Flip-Flop Tristate PFD

(Type 1) (Type 2) — (Type 3) (Type 4)

Modus continous sampled sampled sampled sampled

Tristate — — — — yes

PD yes yes yes yes yes

FD — — yes (yes) yes

Table 3.1: Overview of Phase Detector Types Suitable for Frequency Synthesis

37



38 PLL Building Blocks

K φ is the ratio of a change of averaged output voltage and a change in phase error, it is only

defined for identical input frequencies at both inputs, otherwise the phase error is different

with each period:

K φ =∆vout

∆φ e(3.2.1)

When the PD works together with a charge pump (current output), K φ is usually defined as

K φ =∆iout

∆φ e(3.2.2)

There are continous or analog PD’s (Type 1) which control the loop all the time and sampling

or digital PD’s (all the others) which are only updated once or twice per reference period.

Type 4 PDs are quiet when the PLL is in lock, while the others produce pulses. Due to this

three-state behaviour, type 4 PDs are well suited for driving an integrating loop filter.

Type 1 and 2 PD’s struggle helplessly when the frequencies at both inputs are not identical1.

The other PD’s can handle any frequency difference at their inputs.

3.2.1 Analog Multiplier (Type 1 PD)

Analog multipliers are the oldest phase detectors. They have some advantages concerning

noise suppression, however, they require analog inputs and cannot be used together with a

divider (digital output!) in the feedback path. Therefore, they are not suitable for frequencysynthesis and will not be regarded here.

For more details, see [Gar79, pp. 106 - 120]: Here, multiplying PD’s are analyzed in detail,

with focus on noise and lock-in behaviour.

• Only suitable for analog (not clipped) signals of same frequency f vco = f re f .

• In locked state φ e = 0 and the output voltage ud pulses with twice the input frequency.

• ud = (umax − umin)/2 when φ e = 12π or when f vco = f re f

• K φ = umax − umin

4π

ud

Ref

VCO

4−quadrant multiplier

Figure 3.1: Multiplier symbol

1Due to second order effects, Type 1 and 2 PD’s also can handle a frequency difference although only in a very

limited range.




3.2 Phase Detector 39

umin

umax

ud

eφ−2π −π 2πππ/20

Figure 3.2: Average multiplier output signal ud as function of phase error φ e

ud

umax

umin ef

freffdiv <fdiv fref>

locked

Figure 3.3: Average multiplier output signal ud as function of frequency error f e

3.2.2 EXOR (Type 2 PD)

An EXOR is the most simple implementation of a digital phase detector. It can be regarded as

a clipping version of the analog multiplier. Therefore, some of its properties are quite similiar

to the multiplier. In most cases, an EXOR is used together with an averaging loop filter (Type

I PLL), because the output is simply a pulse width modulated voltage with an average value

proportional to the input phase difference. This is accomplished either by switching a cur-

rent source that drives a load resistor or by simply using the output voltage of the EXOR itself.

A big disadvantage of the simple EXOR PD is that it does not work when the frequencies

at its input are different: in this case, the duty cycle at the output varies all the time. Also,

it can cannot differentiate whether the divider phase is early or late by |∆φ |. However, the

“early point” (∆φ =−π . . .0) is unstable in a closed loop: when e.g.

|∆φ

|becomes smaller,

the duty cycle becomes smaller as well. The resulting loop filter voltage reduction slows

down the VCO2, reducing |∆φ | even further although the system should try to compensate

the disturbance. Therefore, the divider phase is always late in a locked loop with EXOR PD,

i.e. ∆φ = 0 . . .π and the PD slope is always positive, ∂ ud /∂φ e > 0.

As a consequence, the phase difference between its inputs in locked state depends on the

operating conditions: The VCO needs a certain tuning voltage for a certain target frequency.

The control loop action of the PLL will generate the corresponing phase difference. This

means, the phase error will depend on the target frequency and the VCO characteristics - a

change of e.g. the VCO gain causes a phase drift.

Due to the simple structure, the EXOR PD can be designed with an excellent phase noise

behaviour. Drawbacks are that it can’t be used as a frequency detector and its sensitivity to2Assuming the VCO has a positive voltage-frequency characteristic





Div

Ref

Q

2π

∆φ

t

Figure 3.4: Timing diagram for EXOR PD with identical frequency at its inputs

t

Ref

Div

Q

Figure 3.5: Timing diagram for EXOR PD with different frequencies at its inputs

duty cycle variations. Tor some applications, the undefined static phase error can also be a

problem.

• Only phase sensitive, not suited for signals with different frequency f re f = f div.

• In locked state φ e = 0 and the output voltage ud pulses with twice the input frequency.

• The average output voltage depends on the duty cycle of the signals. The next two

equations are only valid for duty cycles of 50%:

• ud = (umax − umin)/2 when φ e = 12π or f re f = f div

• K φ =umax

−umin

π

Q

Div

Ref

Figure 3.6: EXOR schematic





ud

eφ−2π −π 2ππ0 π/2

umin

umax

Repeat

U n s t a b l e R

e g i o n

S t a b l e

R e g i o

n

Repeat

Figure 3.7: EXOR average output signal ud as function of phase error φ e

ud

umax

umin ef

freffdiv <fdiv fref>

locked

Figure 3.8: Average EXOR output signal ud as function of frequency error f e

3.2.3 EXOR + FD (Perrott)

This phase detector behaves like an EXOR (Type 2 PD) when the loop is in lock, i.e. it

produces pulses with a duty cycle proportional to the phase error. Therefore, most of the

descriptions for the EXOR are also true for this type of phase detector. For a detailed de-

scription see [Per97, pp. 126 - 129]. In contrast to the EXOR, the following features have

been added:

The divide by two flip flops at the inputs extend its phase sensitivity range to 0 . . . 2π and

make it insensitive to variations of the duty cycle. Its additional frequency detector turns the

EXOR into a phase-frequency detector (PFD). They can distinguish between the stable and

the unstable region of the EXOR operating range: when the EXOR output is C = 0 at the

rising edge of REF and C = 1 at the rising edge of DIV, the current operation is in the stable

region (0 < φ e < 2π ). In other cases, the frequency detector becomes active, pulling Slo orShi low.

• Phase and frequency sensitive for arbitrary frequency differences.

• In locked state φ e = 0, the output voltage ud pulses with the input frequency (not with

the double input frequency) - due to the frequency dividers, this is different to an ordi-

nary EXOR!

• Also due to the frequency dividers, this PD is not sensitive to duty cycle variations of

its input signals.

• K φ =

umax

−umin

2π





D Q

D−FF

Q

=1&

&

D QS

R

D−FF

Q

D QS

R

D−FF

Q

D Q

D−FF

Q

Shi

S lo

Ref/2

Div/2

C

Divider /2 XOR Frequency Detector

Figure 3.9: EXOR+FD schematic

eφ

φdiv φref<

umax

umin

fdiv fref>

freffdiv <

ud

π 2π−2π

FD Mode

0

PD ModeFD Mode

−4π 4π

Figure 3.10: Average EXOR+FD output signal ud as function of phase error φ e

3.2.4 JK Flip-Flop (Type 3 PD)

The JK Flip-Flop has the peculiar property that it works as a phase detector and also as a

frequency detector - but only when the input frequencies are sufficiently different. When the

input frequencies are nearly identical, the output voltage runs with the frequency difference,

making lock impossible. Therefore, this type of PD is not suitable standalone for frequency

synthesis but it can be used together with other detectors to aid frequency acquisition.

•Phase and frequency sensitive, but not for frequencies which are nearly identical f

re f ≈ f div.

• In contrast to an EXOR, this PD is not sensitive to variations of the duty cycle of its

input signals because it operates on the edges of the input signals.

• In locked state: φ e = 0, pulsed output voltage.

• K φ =umax − umin

2π

• Non-inverting and inverting output available - they are not UP and DOWN outputs!

3.2.5 Tristate PFD (Type 4 PD)

This hasbeen the “classical” PD for integrated frequency synthesizers in the last 20 years (and

still is). It fits well with the classical Up-Down-Chargepump which itself is very well suited





ud

umax

umin

fdiv fref> freffdiv <

ef

PD Mode

Figure 3.11: Average EXOR+FD output signal ud as function of frequency error f e

S lo

Shi

Ref

Div

f/2

iv/2

C

Q

Figure 3.12: Signals in the EXOR+ PD when f re f > f div

for integration in CMOS technologies. It is phase and frequency sensitive with an unlimited

lock-in range. Its three state output fits nicely with integrating loop filters and charge pumps

with very short turn-on cycles. These short turn-on times make it easier to achieve good noise

performance, additionally, the integrating characteristic gives good suppression of inband

VCO noise.

• Phase and frequency sensitive

•Up / down voltage outputs with quiet state (up and down outputs high-ohmic) in locked

state (φ e = 0), therefore suitable for charge pumps / integrating loop filters.

• K φ =umax − umin

4π

• Sensitive to missing edges because the PD has “memory” and tries to correct the missed

edge. This makes type 4 PDs unsuitable for clock and data recovery purposes.

3.2.6 Hogge’s Phase Detector

[LB92], [Lee98]

3.2.7 (Modified) Triwave Phase Detector[LB92], [Lee98]





Div

π

Q

C

iv/2

f/2

Ref

S lo

Shi

Figure 3.13: Signals in the EXOR+ PD when f re f = f div (φ div < φ re f

)

Q

Q

Ref

Div

Figure 3.14: JK Flip-flop schematic (neg. edge triggered)

3.3 Charge Pumps

3.3.1 Single Ended Designs

3.3.2 The Dead Zone and How to Get Around It

An old problem with charge pump designs is the ”dead zone”: when a type II PLL is in or

near lock, only very short pulses are needed to keep the loop locked. However, the speed of

the PD logic or the CP may not be sufficient to fully turn on the current sources. The result-

ing phase error transfer characteristic has a ”flat” part around ∆φ = 0, i.e. K φ is reduced or

even zero in the main operating point of the PLL. The consequence is a strong deviation of

loop gain and loop bandwidth from the target value that cannot be explained from static CP

current measurements. This a purely dynamic effect that also depends on temperature and

process variations. In really bad cases the dead zone can cause the PLL phase to drift around

the locked value because the loop is effectively open (K φ ) around ∆φ = 0. The result is a

tremendously increased phase noise / jitter.

Obviously, it’s best to avoid the dead zone altogether, a very effective solution is to increase

the latency time of the PFD in the reset path (fig. 3.17). This extra delay creates a minimum




3.3 Charge Pumps 45

ud

umin

eφ

umax

π−2π −π 0 2π

repeat

Figure 3.15: Average JK Flip-flop output signal ud as function of phase error φ e

ud


efumin

umax

u n

d e

f i n e

d

u n

d e

f i n e

d

PD Mode

Figure 3.16: Average JK Flip-flop output signal ud as function of frequency error f e

pulse width (”anti-backlash”, ABL) of the Up/Down pulses. At ∆φ = 0, the pulses canceleach other out, small phase errors increase the length of one of the pulses in a very linear

way. The minimum pulse length should not be excessively long because the transfer of am-

plitude noise components from the charge pumps is proportional to the pulse length. When

the Up/Down current sources are not perfectly matched, the mismatch creates spurious side-

bands, increasing with the pulse width (6.5).

Another solution to get around the dead zone problem is to add a small DC offset current

(”trickle charge”) to the CP output (fig. xxx). When the offset current is sufficiently large,

the PFD / CP combination always works in one quadrant in locked state, i.e. only one current

source is active. This not only eliminates the dead zone, it also avoids non-linearities due to

different up/down - currents (→ K φ ). Reference frequency spurious sidebands resulting from

the offset current (6.4) usually forbid the use of this concept in integer PLLs - the reference

frequency is too close to the loop bandwidth to achieve a sufficient suppression. However,

for fractional- N PLLs the case is different: the reference frequency is much higher and Σ∆PLLs distribute the energy of the reference spur over a wider frequency band anyway. Most

importantly, is that Σ∆ PLLs are very sensitive to non-linearities, yielding strange spurious

sidebands. Operating the CP only in one quadrant removes these sidebands.

3.3.3 Charge Pumps and Two-State Phase Detectors

Although the three-state PFD is a charge pump’s best friend, two-state PFDs or PDs like the

EXOR can also be combined with a charge pump / integrating loop filter combination: The

EXOR output switches e.g. the current sink, the inverted output switches the current source

(fig. 3.20). Or, the EXOR switches e.g. the current sink, the current source is always on, with

half the current flowing continously into the loop filter (fig. 3.21). In average, the net current





Q

QSD

R

D−FF

Q

QSD

R

D−FF

TABL∆

DOW

UP

"1"

"1"

Div

Ref

Figure 3.17: Tristate PFD schematic

eφ

freffdiv <

di

i min

i max

fdiv fref> φdiv φref<

2π−2π 0 4π−4π

FD Mode PD Mode

FD Mode

Figure 3.18: Average Tristate PFD output signal id as function of phase error φ e

flowing into an integrating loop filter must be zero. Therefore, the control loop action of the

PLL forces sink and source current to be switched on for exactly the same duration (50%) per

cycle. The resulting input phase difference is π /2 (if current sink and source have the same

current magnitude I 0 and if the duty cyle of the input signals is 50%). The same is true for the

unipolar charge pump if the switched current is exactly twice as large as the constant current.

A major disadvantage of this concept is that CP current is flowing all the time, coupling noise

into the loop filter.

3.4 Loop Filter

See section

3.5 Divider

Programmable dividers for RF frequency synthesizers usually are constructed from an RF

prescaler and some programmable, lower frequency control / counter blocks. The reason for

this is that all divider cells run with the full input frequency in a fully synchronous counter.

This consumes a lot of power and is hard to design for high frequencies. A fixed prescaler by

P reduces the maximum input frequency to the programmable divider by a factor of P but it

has a major disadvantage: the minimum frequency step increases by a factor of P. Prescalers

built from dual modulus dividers (DMD) or multi modulus dividers (MMD) offer a way out

of this dilemma: The division ratio (= modulus) of a DMD prescaler can be switched between

2 N and 2 N + 1; an MMD offers a wider range of division ratios, e.g. 2 N , 2 N + 1, 2 N + 2, . . ..During the division cycle, the prescaler modulus is altered in such a way that the desired total




3.5 Divider 47

ud

umax

umin


ef

PD Mode

Figure 3.19: Average Tristate PFD output signal ud as function of frequency error f e

= 1

Ref

Div

I0

I0

Exor

to VCO

Figure 3.20: EXOR with bidirectional charge pump and integrating loop filter

division ratio is achieved. This is described in the next two sections, [VFL+00] and [Per97]

give a more detailled description of various divider architectures.

3.5.1 Dual Modulus Prescaler

At the heart of all DMD / MMD Prescalers is a divider cell whose division ratio can be

switched between 2 and 3 (fig. 3.22), depending on the logic level at the P input. When

P = 0, the enable signal EN = 1 always enables the divider flip-flop D − FF 1, turning it

into a simple ÷2 toggle flip-flop: D1 = Q (fig. 3.23). When P = 1, the phase shift flip-flop

D−FF 2 delays the Q signal of the divider D−FF 1 by one input cycle, pulling EN = 0 for one

clock cycle. Thus one clock edge is “swallowed” by the divider flip-flop D − FF 1, creating

a modulus 3 divider. This path is the critical timing path: The D1 input has to go low beforethe clock edge to be swallowed (“slack” in fig. 3.23).

For reasons that will be explained later, it makes sense to expand this basic ÷2/3 cell to a

higher modulus, e.g. to ÷8/9. The principle is the same as in the ÷2/3 cell: here, every

ninth pulse is swallowed. Simply adding an asynchronous ÷4 divider is not enough - you

would end up with a ÷8/12 divider. A little extra decoding logic (fig. 3.24) guarantees that

the P input of the ÷2/3 cell goes high only when P = 1, Q23 = 0, Q4 = 0 and Q8 = 0 which

happens once during each divide cycle. This pulse swallowing gives a total division ratio of 9.

There is an upper limit to the number of asychronous divider stages for a given input fre-

quency: when the time the clock edge needs to ripple through the asynchronous divider is

approximately equal to the input period, the divider will fail. At higher frequencies, the

prescaler may operate correctly again - with one clock cycle latency in the asynchronous di-

vider! This failure is easily overlooked when sweeping the input frequency in large steps.





= 1

Ref

Div

I0

02I

to VCO

EXOR

Figure 3.21: EXOR with unidirectional charge pump and integrating loop filter

D Q

Q

D−FF1

&

&DQ

Q

D−FF2

2 / 3

Fin Fout

P

inF

Fout

QP

D1

Divider /2 with enable

Phase Shift

criticalpath

=>

PP=0 => /2

P=1 => /3

EN

Figure 3.22: Basic 2/3 divider cell

How can we design a fully programmable counter from such a DMD prescaler which can

only be switched between two division ratios? The trick can be done with additional back-

ward counters which are clocked with the output frequency of the prescaler (fig. 3.25).

With each output pulse, the A- and the B counter are initialized and start counting backwards

with the output pulses of the prescaler. As long as A > 0, the ÷P + 1 mode is active, forthe rest of the time the prescaler divides by P. When the B-counter also has reached 0, an

output pulse is generated and A- and B-counter are initialized again. During one output cycle,

the input signal has been divided ÷P for A time and ÷P + 1 for B − A times. The resulting

division ratio of such a divider is (3.5.1):

Division Ratio of a Dual-Modulus Divider

N = B − A · P + A · P + 1 = BP + A; B > A (3.5.1)

The corresponding signals are shown in fig. 3.26 where P = 4, B = 5 and A = 3.

The prescaler ratio P limits the lowest division ratio: B has to be higher than A for proper

operation, which is quite obvious from the principle of operation. But B also has to be




3.5 Divider 49

Fin

Fout

D1

PQ

P

t

EN

Slack

÷3÷2 ÷2

P Switch P Switch

Swallow Swallow

Figure 3.23: Signals in a 2 / 3 divider cell

2 / 3

Fin Fout

P

inF

1

T−FF

Q

T−FF

Q

Fout

P=0 => /8P=1 => /9

criticalpath

Q4Q8

Q23

23P

P

Async. Divider /4

Figure 3.24: An 8/9 dual modulus prescaler

higher than P, otherwise there will be ”gaps” in the achievable division ratios N . Assume for

example P = 32 and B = 30. The highest division ratio will be 30·32+29 = 989 (3.5.1). The

lowest division ratio for the next higher value of B = 31 is 31 ·32 + 0 = 992, i.e. the division

ratios N = 990 or N = 991 cannot be reached with this architecture. In general, the minimum

division ratio that can be set with a prescaler P without gaps is

Minimum Division Ratio of Dual-Modulus Divider

B ≥ P ⇒ N ≥ P2 (3.5.2)

3.5.2 Multi Modulus Divider

A multi-modulus divider uses a different controlling mechanism: it usually consists of a chain

of ÷2/3 cells (fig. 3.27). Simply cascading some dual-modulus divider cells does not do the

job as can be seen easily: a division ratio like N = 129 cannot be constructed from a product

of 2’s and 3’s as it is a prime number! What we want is a construction that adds one extra

cycle per output period if the modulus control Pi = 1. This can be achieved with extra control

input and output pins M in and M out (fig. 3.28). The modulus enable input M in enables the

P input pin, the modulus enable output M out synchronizes the M in input and passes it on to

M in of the previous divider stage. This “daisy chain connection” ensures that each divider

stage swallows a maximum of one pulse per divide cycle (depending on the level at Pi). The





Fin Fout

÷ P / P+1

P

inF

P=0 => ÷PP=1 => ÷P+1

QB−Counter

Reload B

Q

A−Counter

Reload A

Fout

DMD Prescaler Programmable Counter

&

N=B·P+A

A

B

Figure 3.25: Dual-modulus divider

Q

B

outP

Fin

QA

= Fout

A=3A=0A=0 A=2 A=1A

A>0

B

A=3

B=4 B=3B=5 B=2 B=1B=1

A>0

B=5

B>1

N=B·P+A

÷P ÷P+1 ÷P ÷P+1

B>1t

Figure 3.26: Signals in a dual-modulus divider

resulting division ratio is:

Division Ratio of Multi-Modulus Divider

N = 2n + pn−1 ·2n−1 + . . . + p1 ·2 + p0 (3.5.3)

2 / 3

Fin Fout

M out M in

P

2 / 3

Fin Fout

M out M in

P

2 / 3

Fin Fout

M out M in

P

2 / 3

Fin Fout

M in

P

P0

P1

Pn−2

Pn−1

ouDIVRFin

Figure 3.27: Multi-modulus divider made from a Chain of 2/3 divider cells

Fig. 3.28 shows an improved 2/3 divider cell with modulus enable input. Speed is improved

further by shifting the P - NAND into D-FF2 (between the Master and the Slave stage) to

shorten the critical path. Synchronizing the programming word guarantees a fixed timing

relationship between programming word and divided clock. This is important if the division




3.6 VCO 51

ratio is switched dynamically like in Sigma-Delta Fractional-N synthesizers.

D Q

Q

D−FF1

2 / 3

Fin Fout

M out M in

P

1

&D−FF

DQ

Q

2

inF

inM

Fout

&M

out

EN

1D

D2

Divider /2 with enable

critical path

Phase Shift

PM_in = 0 => /2 P = 0 => /2

M in = 1 => P enabled P = 1 => /3

=>

Figure 3.28: Improved 2/3 divider cell with modulus enable

3.5.3 High-Speed Flip Flops

The core cell for high-speed dual- and multi modulus divider blocks is of course a high speed

flip-flop. Depending on the available technology and the required operations speed, there are

various circuit architectures:

Current Mode Logic This design style is copied from high-speed bipolar circuits:

Q

Clk

D

D

Q

Clk

Bias

"Slave""Master"

Figure 3.29: D-Flip-Flop in current mode logic

3.5.4 Synchronization

One point to note with Dual- and Multimode - Dividers is their latency: a constant delay in an

integer PLL introduces a constant phase error which is usually compensated for in the PLL.

In fractional-N PLLs, the divider delay can depend on the division ratio - this variable delay

/ phase error introduces non-linearities showing up as spurious sidebands!

3.6 VCO




Chapter 4

Fractional-N PLLs

Better to light a candle than to curse

the darkness.

Chinese Proverb

In principle, it is possible to achieve any wanted frequency resolution with a PLL by just

making the reference frequency small enough. But, as explained in chapter 2, a low reference

frequency demands an even lower loop bandwidth for stability reasons. And a narrow loop

bandwidth means sluggish transient response and bulky loop filter capacitors which is not

acceptable for most applications.

Besides that, a low reference and high target frequency require a high frequency division ratio

which degrades the noise performance of the PLL (see section 10.1).

For these reasons it would be nice to have a high reference frequency and a fine frequency

resolution at the same time by using a fractional division ratio. A frequency of e.g. f 0 = 900.1MHz could be synthesized with a reference frequency of f re f = 1 MHz and a division ratio

of N = 900.1 instead of using 100 kHz and N = 9001. Of course, it is not possible to divide

a frequency by a non-integer value1. But we can get away with a little cheating: if 9 out of

10 times the frequency is divided by 900 and once by 901, the division ratio average over 10

cycles will indeed be 900.1. And if we do it fast enough, no one will notice: The PD will try

to correct the phase error due to the periodic switching of the division ratio but the loop filter

is too slow to follow each excursion of the PD output. Hence, loop filter output and VCO will

settle at the desired average frequency f 0. Such a PLL is called Fractional-N PLL. As usual,

there is no free lunch: the drawbacks of Fractional-N PLLs are

• spurious sidebands created by periodic switching of division ratio

• increased circuit complexity

• increased sensitivity to component mismatch with some implementations

In contrast to the PLLs described so far, the division ratio N (t ) now is time dependent. In

spite of the low-pass characteristic, the resulting VCO frequency will still contain some of

the modulation of N (t ):

f VCO (s) = f re f N (s)T (s) (4.0.1)1At least not when using straight-forward digital techniques.

53



54 Fractional-N PLLs

This behavior determines spurious sidebands, phase noise and settling - it will be analyzed in

the rest of the chapter.

In addition to the functional blocksdescribed in the last chapters, a Fractional-N PLL contains

some new blocks (see figure 4.1):

• A divider that allows switching the division ratio between two (Dual-Modulus Divider)

or more (Multi-Modulus Divider) different values. In contrast to the ordinary pro-

gramming of the division ratio, this switching must be synchronized to the input signal

(fast!!).

• A logic block controlling the periodic switching of division ratio. This block generally

is some sort of counter / accumulator, it can be realized in many different ways. Some

implementations will be described below.

• Optionally, some circuitry to compensate for the inherent spurious sidebands.

The average output frequency f 0 depends on the number N F of ÷( N +1) cycles per fractional

modulus cycle T mod . One fractional modulus cycle consists of F mod reference clock cycles:

T mod = F mod · T re f . F mod is called the fractional modulus of the PLL, defining the minimum

fractional frequency step f mod = f re f /F mod . F mod can be as low as 5 or several orders of

magnitude larger, N F is in the range 0 . . . F mod −1. The average output frequency is

f 0, frac = ( N I + N F /F mod ) f re f = N I .F f re f

where .F is the short form for the fractional part. The frequency deviation from a “normal”,

integer PLL is therefore

∆ f 0, frac

=N F f re f

F mod

=N F

F mod T re f

(4.0.2)

EXAMPLE 2: Minimum frequency step of integer and fractional-N PLL

An Integer-N PLL with N = 900 and f re f = 1MHz produces a VCO output fre-

quency of f 0,int = 900MHz with a minimum frequency step of f re f = 1MHz.

When a Fractional-N PLL is used with F mod = 5 and N F = 1, the division ratio

is 4 times N = 900 and once N+1 = 901 in F mod = 5 reference clock cycles. This

gives an average division ratio of 900.2 and an average VCO output frequency

of f 0, frac = 900.2 MHz. The minimum frequency step is f mod = f re f /F mod =200kHz.

N

RF out

VCOLoop FilterReference

Accu

CO

Frequency

Fractional Part

Integer PartFreq. Word

mod

PFDf

÷N / N+1

Figure 4.1: Frequency synthesizer using fractional-n techniques




4.1 First Order Fractional-N PLLs 55

N = 10 N = 10 N = 10

N = 10N = 10 N + 1 = 11

N f

N=10.333

t

I I I

modF = 3

refI

DIV

PD/CP(initial)

PD/CP(final)

VCO

REF

Figure 4.2: Timing diagram of 1st order fractional-N PLL

Fractional-N PLLs achieve the same frequency resolution as an integer-N PLL with a refer-

ence frequency that is higher by a factor of F mod . The higher reference frequency lowers the

noise floor by 10logF mod . However, due to the periodic switching of division ratios, there is a

ripple on the VCO control voltage that is periodic with T mod , producing spurious frequencies.

Fractional-N PLLs with no further compensation of this periodic error are called first order ,

PLLs using an analog compensation mechanism are called second order and PLLs that dither

the error (Sigma-Delta-Modulator) are called third order .

4.1 First Order Fractional-N PLLs

All fractional-N PLL use the concept of averaging the frequency over a number of F mod

reference periods to achieve a fractional division ratio. The periodicity F mod (also called

modulus length) determines the frequency resolution of the PLL:

∆ f = f re f /F mod (4.1.1)

This can be easily seen from an example: when the division ratio is F mod − 1 times N I and

once N I + 1 during F mod cycles, the resulting average division ratio will be:

N =(F mod −1) N I + N I + 1

F mod

= N I + 1/F mod

The periodic switching of the division ratio is triggered by the phase accumulator , an accu-

mulator with modulus F mod that adds up N F every reference cycle. Each time an overflow

occurs, the division ratio is switched from ÷ N to ÷( N + 1) for one reference cycle.

Let’s assume the PLL is locked at the fractional frequency f 0 = N I .F · f re f . Fig. 4.2 shows

an example for a modulus of F mod = 3, N I = 10 and N F = 1, giving an average division ratio

of N = N I .F = 10 1/3. During the÷

N parts of the modulus cycle the divided VCO signal

arrives a little too early at the phase detector because the VCO is faster than the virtual signal

f 0,int = N I f re f (there is no such signal in the PLL) by ∆ f frac (see 4.0.2).





Ref. Cycle #1 #2 #3 #4 #5 #6 . . . Average

Modulus Cycle #1 #2

← T mod → ← T mod → N F = 1: Accu 5 → 0 1 2 3 4 5 → 0 . . .

Div. N + 1 N N N N N + 1 . . . N + 15

∆φ 02π

t =0

55

→ 0 15

25

35

45

55

→ 0 . . . 25

∆φ 02π

t =∞

35

→ −25

− 15

0 15

25

35

→ − 25

. . . 0

N F = 3: Accu 5 → 0 3 6 → 1 4 7 → 2 5 → 0 . . .Div. Ratio N + 1 N N + 1 N N + 1 N + 1 . . . N + 3

5∆φ 02π

t =0

55

→ 0 35

65

→ 15

45

75

→ 25

55

→ 0 . . . 25

∆φ 02π t =∞

35

→ −25

15

45

→ − 15

25

55

→ 0 35

→ − 25

. . . 0

Table 4.1: Operation of Phase Accumulator (F mod = 5)

4.2 Higher Order Fractional-N PLLs

In [RCK93] several methods for constructing a fractional-N frequency synthesizer are com-

pared to a synthesizer based on Σ − ∆ Fractional-N Synthesis which is described here for

the first time. Although the concept of Delta-Sigma-Modulation had been used in the design

of Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters for quite a while

back in 1993, this article was the first to apply that concept to the domain of frequency syn-

thesis, triggering the development of many new circuits and applications.

The methods used at that time to achieve fractional- N frequency synthesis were

• pulse swallowing (i.e. simple first order fractional- N PLL)

• phase interpolation where the phase error is partially compensated by a DAC at the

loop filter input

• Wheatley random jittering where a random number is added at the accumulator input

Each method has major drawbacks: The first on generates massive fractional spurs as we

have seen, the second reduces these spurs at least partially but requires precision analog com-

ponents and the last one reduces the fractional spurs at the cost of an increased noise floor.

Therefore, let’s first take a look at sampling, oversampling and delta-sigma-modulation:

4.2.1 Sampling and Quantization

An analog signal needs to be discretized in time (sampled) and amplitude (quantized) to bring

it to the digital domain. Nyquist was the first to find out that the sampling rate f S needs to

be at least twice as high as the signal bandwidth f B to reconstruct the original signal with-

out losses. The reason for this is that sampling creates images of the original signal around

multiples of f S. If f B > f S/2, the images overlap, folding back frequency components above

f S/2 into the base-band. These components are called aliases as a component at f 1 cannot

be distuingished from a component at f 1 − f S/2. The resulting distortion or increased noise

cannot be removed. For this reason, the signal needs to be band-limited with an anti-aliasing

filter to f B

≤f S/2. It can be shown (and nearly every book on communication theory does

it ...) that proper2 sampling is a procedure (at least in theory) from which the original signal2 f S > 2 f B




4.2 Higher Order Fractional-N PLLs 57

can be recovered without losses. A low-pass with f B ≤ f LP ≤ f s/2 removes the images of the

orginal signal around k f S, acting as a reconstruction filter.

Quantization is another story - the infinite amplitude resolution of the analog signal is reduced

to a discrete number of levels which inevitably creates distortions and noise. In general, it is

very difficult to predict the level of distortion as it depends not only on the quantization step

size but also on the signal amplitude and statistics. Fortunately, many real world signals have

a Gaussian amplitude probability density function which allows an easy calculation:

Figure 4.3: Quantization

Figure 4.4: Spectral density of quantization noise

Figure 4.5: Spectral density of quantization noise with oversampling

If the signal has a Gaussian amplitude distribution, the same will be true for the quantization

error qe as well. In this case the power spectral density of the quantization noise N q( f ) will

be flat:

e2n = N q( f ) =

q2e

f S=

q2e,rms

f S=

∆2

12

1

f S(4.2.1)

Beware: This formula is too optimistic for periodic signals - here, quantization noise won’t

be flat, containing harmonics and sub-harmonics that may be several dB’s above the noise





floor!

The total baseband quantization noise power depends on the bandwidth f B

. In the limit case

of Nyquist bandwidth, f B = f S/2:

S B, Nq =

f B

− f B

N q( f )d f =

f S/2

− f S/2 N q( f )d f = q2

e,rms =∆2

12(4.2.2)

Converters operating near this limit are therefore called Nyquist-rate converters.

Oversampling

When the sampling rate is larger than 2 f B (”oversampling”), the quantization noise power in

the base-band will be less - the part of the quantization noise that is stretched out above f Bwill be removed by the reconstruction filter (assuming f B = f LP):

S B = f B

− f B

N q( f )d f =∆2

12

2 f B

f S= S B, Nq

2 f B

f S=

S B, Nq

M (4.2.3)

where M is the oversampling ratio (OSR) f S/2 B. (4.2.3) shows that oversampling reduces

the quantization noise in the baseband by 10log M .

The signal-to-noise ratio (SNR) is defined as the ratio of signal power and (baseband) noise

power. Let’s assume the signal is a sinusoid (happily ignoring that its quantization noise will

not have a flat spectral density) with an amplitude A which uses the full input range of the

quantizer (2 A = FSR = 2 N ∆) without clipping. It’s signal power will be A2/2 = 2 N ∆2/8

SNR = 10logA2/2

q2e,rms

(4.2.4)

Another advantage of oversampling is the much relaxed requirements for the anti-aliasing

filter - normally, you would use a bulky analog filter with a bandwidth just below the sampling

frequency to preserve the full signal bandwidth. In an oversampling architecture, the anti-

aliasing filter just needs to prevent signal components above f S/2 from entering the ADC

which is far above the signal bandwidth. Signal and quantization noise between f B and f S/2

can be removed in the digital domain.

4.2.2 Delta Modulation

Delta modulation was originally developed to reduce the bandwidth for data transmission. It

is actually the simplest form of differential predictive coding: some known property of the

signal is exploited to compress the signal. When the sampling period is much higher than themain frequency components of the signal, bandwidth can be saved by transmitting only the

changes of the signal (”delta”) between samples (fig. 4.6 and 4.7). In its simplest form, delta

modulation approximates the input signal with a staircase function.

The signal is demodulated by integrating the delta samples and converting them back to the

analog domain.

In contrast to simple oversampling, the feedback in delta modulation forces the output of the

modulator to track the lower frequency components of the input signal. Therefore, quanti-

zation noise is reduced at low frequencies and pushed to high frequencies where it can be

filtered out more easily. Fig. 4.7 shows two potential sources of distortion in delta mod-

ulation: steep slopes cannot be tracked by the integrator (”slope overload”) and very slow

changes of the signal can create so called ”granular noise”. Increasing the step size ∆ reduces

slope overload but increases the granular noise and vice versa.





−1

+1 d (n)q

f−s(t)

Quantizer Sampler

Integrator DAC

Delta−Modulator Delta−Demodulator

s(t)

Integrator LP−Fil terDAC

Figure 4.6: Delta modulation and demodulation

1 1 11 1 11 1 1 1 1 1 1 111 10 0 0 0 0 0 0 0 0

TS

Integrator output

Delta modulated data stream

∆Signal

Input Granular NoiseSlope

Overload

Distortion

Figure 4.7: Delta modulation signal forms

4.2.3 Principle of Sigma-Delta Modulation (SDM)

Putting an integrator in front of the Delta Modulator reduces its distortions - the low-frequency

signal components are amplified which makes life easier for the delta modulator because the

signal auto-correlation is increased. This combination is called sigma-delta modulator (fig.

4.8a). Furthermore, demodulation is simplified as the sigma-delta data stream does not need

to be integrated - a DAC (which in its simplest implementation could be just a logic buffer)

and a low-pass filter are sufficient. The filter specifications can be quite relaxed as the sam-

pling frequency has to be much higher than the signal bandwidth.Implementation is further simplified by moving the integrator behind the comparator, can-

celling the integrator in the feedback path (fig. 4.8b). Due to this implementation, the Sigma-

Delta Modulator is also called Delta-Sigma Modulator, however, the transfer functions are

identical. Again, due to the feedback loop, quantization noise is concentrated at higher fre-

quencies.

Sigma-Delta Modulation is also used in a purely digital architectures: Here, the modulator

takes a digital signal with high bit resolution and converts it into a signal with higher sam-

pling rate (”oversampling”) and lower bit width (fig. 4.9a). A very efficient implementation

is achieved by swapping quantizer and delay stage (fig. 4.9 b+c): the delay stage is drawn

into the digital integrator, cancelling the delay in the feedback path. This structure is the

”classical” accumulator (fig. 4.10), containing an adder and a register (= delay). The transfer

function in the z-domain has a 1 − z−1 term in the denominator, indicating integrating behav-

iour; the z−1 term in the numerator mirrors the latency time of one sample.





d (n)q

−1

+1s(t)

SamplerQuantizer

DAC

Integrator

Integrator

− f

DAC

s(t)

LP−Filter

−1

+1

−

s(t)

SamplerIntegrator

DAC

Quantizer

f

DAC

s(t)

LP−Filter

d (n)q

Sigma−Delta−Modulator (analog) Sigma−Delta−Demodulator

⇓a)

b)

Figure 4.8: Analog-to-Digital Converter using sigma-delta modulation

Digital accumulators bring the quantizer for free - the carry overflow bit can be regarded as

MSB, signalling the upper half of the signal range.

Another implementation for the integrator with less latency is shown in fig. 4.11 - note that

there is no z−1 term in the numerator.Exactly as with the analog integrator, its digital counterpart canoverflow / saturate (depending

on the implementation). In the digital domain, there is a simple remedy is much simpler:

increase the word length of the accumulator to achieve a wider range.

So far, we’ve only used a handwaving approach, declaring that the quantization of the DSM

stream d q(n) is high-pass shaped. In order to look at things a little more closely, we replace

the accumulator by its transfer function (fig. 4.12). To simplify things even further, we

substitute the quantizer by adding the quantization noise en to the original signal. We have

not made any assumptions on the spectral shape of the quantization noise yet. The digital

output stream is

d q( z) = (s( z) − d q( z))z−1

1−

z−

1+ en( z)

=

s( z)

z−1

1− z−1+ en( z)

1 +

z−1

1− z−1

−1

= s( z) z−1 + en( z)1− z−1

noise shaping

(4.2.5)

The resulting bit stream contains the input signal, delayed by one sample ( H s( z) = z−1),

plus the quantization noise en, shaped with H n = 1 − z−1. H n is the transfer function of

a differentiator which suppresses slow changes of en (i.e. low frequencies) by taking the

difference between two consecutive samples. The frequency response of this time-discrete

transfer function is calculated by replacing the discrete frequency variable z by e jω T s :

H n e

jω T s = 1− e− jω T s = |1− cosω T s − j sinω T s|

=

(1− cosω T s)2 + sin2ω T s





−1

+1

z−1

z−1

f

digd (n)q

z−1

−1

+1d (n)q

z−1Quantizer

s(n)

−

Accumulatorb)

−1

+1d (n)q

z−1

s(n)

Quantizer Delay−

Accumulator

s(n)

DownsamplerFilter /

⇓

Modulator Demodulator

a)

⇓

Quantizer

s(n)

−

Accumulatorc)

Figure 4.9: Digital delta-sigma modulation

s (n)I z−11 − z−1

=s(n)

z−1

Is (n+1)z−1

Is (n)s(n+1)

z−1Is (n+1) Is (n)s(n+1)

⇓

Figure 4.10: Digital integrator (one sample delay)

=

2−2cosω T s =

4sin2 ω T s

2

= 2sin ω T s2 = 2sin π f

f S (4.2.6)

(4.2.6) shows that the quantization noise at the SDM output is indeed high-pass shaped in the

frequency range 0 . . . f S/4. At f S/2 the noise transfer function becomes zero again, it repeats

with a period of f S/2. The total noise power depends on bandwidth of interest f B:

σ 2n ( f B) =

+ f B

− f B

H 2n ( f ) · Se( f ) d f

=

+ f B

− f B

2sin

π f

f S

2 σ 2e f S

d f

=4σ 2e f S

f

2− f S

4π sin

2π f

f S

+ f B

− f B





z−1s (n)I

1 − z−1=

s(n)

1

Is (n+1)

Is (n)

Digital Integrator (no delay)

s(n+1)

Figure 4.11: Digital integrator (no delay)

z−1

1 − z−1 −1

+1d (n)q

−Accumulator Quantizer

s(n)

z−1

1 − z−1

d (n)q

e (n)n

−Accumulator Quantizer

s(n)

z−1

n−1e (n) (1−z )

d (n)q

⇓

⇓s(n)

Noise−shaping

Figure 4.12: Digital delta-sigma modulation - equivalent represenation for quantization noise

=2σ 2eπ

2π f B

f S− sin

2π f B

f S

(4.2.7)

applying the identities sin2 x +cos2 x = 1 and 1−cos x = 2sin2 x2. The interpretation of (4.2.7)

is easier when regarding two extreme cases - the noise power over the whole baseband inter-

val 0 . . . f S/2 and within a more ”practical” bandwidth f B f S/2:

Full baseband bandwidth: f B = f S/2:

In this case, the sin(. . .) part in (4.2.7) becomes zero and the total noise power is:

σ 2n ( f S/2) = 2σ 2e (4.2.8)

The result is the same as (xxx) which means the noise has only been shifted from low frequen-

cies to higher frequencies (”noise shaping”), but the total noise power has not been reduced.

However, the quantized noise can be filtered out more effectively:

Narrow signal bandwidth: f B f S/2:

In order to get a useful result, the sine function is approximated by x − x3/6 (Taylor series):

σ 2n ( f B f S/2) ≈ 2σ 2eπ

2π

f B

T s−2π

f B

T s+

1

6

2π f B

f S

3

=π 2σ 2e

3·

2 f B

f S

3

(4.2.9)

Here, oversampling improves the SNR by 30log f B/ f S , compared to a meager 10log f B/ f Sfor a system without noise shaping (4.2.3).





4.2.4 Different Architectures for Sigma-Delta Modulators

A plethora of different structures and architectures has evolved since the beginnings of thesigma-delta modulator. [NSE97] gives a good overview, here, only a few examples will be

shown:

x(n) xd(n)− −Quantizer

−1z

−1z

+1

−1

Figure 4.13: Second order digital sigma-delta modulator

The SDM in fig. 4.13 has a latency of one clock cycle, here, the most significant bit is stripped

by the quantizer and passed on to the output. It is scaled and fed back into the modulator.

z−1

xd(n)−Quantizer

x(n)

D(n)

D(n) − MSB(n)−1

−1

+1

x2

z

Figure 4.14: Second order digital sigma-delta modulator

The SDM in fig. 4.14 has a latency of zero clock cycles which has advantages for some

applications. The quantizer simply strips off the most significant bit MSB(n), the ”‘rest”’, i.e.

the truncation error D(n) - MSB, is fed back into the modulator. Its transfer function is given

by

H ( z) = z−12− z−1

It is stable for an input range of xxx.

4.2.5 Performance Comparison

The single-loop quantizers have two important drawbacks: due to the limited input range

there are issues with instabilities and they also susceptible to tones.

On the other hand, a drawback of cascaded quantizers (MASH) is the requirement for a

multi-bit DAC resp. multi-modulus prescaler. These multi-bit converters are more prone

to non-linearities than their one-bit counterparts. The noise shaping properties of these twotypes are also different [Rhee2000]: MASH quantizers have a higher corner frequency for the

noise transfer function but create more quantization noise at higher frequencies. This may be

a problem for some wideband applications.

Other Applications of SDM

Multipliers / Attenuators: A digital multiplier for a multi-bit signal has a large hardware

complexity - so why not convert the multi-bit signal to an oversampled one-bit stream? Mul-

tiplication of a one bit signal with a constant c is implemented as a multiplexor, switching

between −c and +c (fig. xxx).




Chapter 5

PLL Modeling and Simulation

All models are wrong; some models

are useful.

W. Edwards Denning, Statistician,

1900-1986

The simulation of PLLs is a challenging task due to the large range of time constants in

a typical loop. A frequency synthesizer for wireless applications may e.g. have an output

frequency of 4 GHz (T = 250 ps), a reference frequency of 26 MHz and a loop filter corner

frequency of 100 kHz (τ = 15.9µ s). In order to verify spectral purity, the loop filter voltage

has to calculated with a precision of a few µ V. Classical mixed-signal simulation can bevery time consuming, a faster method is to apply the event-driven approach well-known from

digital simulation. This approach is well suited to thegrowing digital complexity of frequency

synthesizers and clock and data recovery circuitry. The analog building blocks in the PLL

have to be described in a format suitable for event-driven simulation. This will be described

in the next sections:

5.1 Loop Filter

In most PLLs, the loop filter is a continuous-time, continuous-valued element (fig. 5.1). In

order to simulate the filter in a digital environment which is time-discrete and discrete valued,

it has to be modeled as a digital filter. This can be done by translating its transfer functionfrom the s-domain into the z-domain using the bilinear transform [Proakis, pp. 628-630].

The transformation gives the transfer function for a sampled filter with continuous-valued

coefficients which is exactly what you need for modeling purposes: in VHDL or Verilog, the

coefficients can be defined as real constants with almost arbitrary resolution.

If you want to implement such a filter on silicon for an all digital PLL, you need to quantize

the coefficients and input values as well. The trade-off between word length (i.e. resolution)

and silicon resources (i.e. required area / maximum speed) can be very tricky and is not

described here.

5.1.1 Bilinear Transform

The general transfer function of a filter in the s-domain is given by (factored or summation

form):

65



66 PLL Modeling and Simulation

R1

R3R2

C1 C3C2

R1

(voltage mode) (current mode)

to VCO

I

= V

/ R 1

PD/CPPD

P D

C P

V

= I

R 1

P D

C P

2nd pole

3rd pole

1st pole

Figure 5.1: Non-Integrating Loop Filters

H (s) =

M ∏

k =1

s − sk

N

∏l=1

s − sl

=

M ∑

k =0

sk s

k

N

∑l=0

sl sl

; M ≤ N (5.1.1)

where sk are the zeros and sl the poles of the filter.

The z-domain is used to describe dicrete-time processes. The so called bilinear transform

can be used to map the s-domain onto the z-domain:

Bilinear Transform

s → 2T S

z −1 z + 1

= 2

T S

1− z−1

1 + z−1

(5.1.2)

where T S is the sampling period of the discrete-time domain. This conformal mapping maps

the jΩ axis onto the unit circle in the z-domain, the left half plane is mapped into the inner

part of the circle, the right half plane onto its outer part.

Applying this transform gives the transfer function for a corresponding discrete-time (or dig-

ital) filter:

H ( z) =

M ∑

k =0

bk z−k

1 + N

∑k =1

ak z−k

; M ≤ N (5.1.3)

The number of poles N (the order of the filter) is the same as as in the continous-time repre-

sentation but the number of zeros M can be different.

(5.1.3) describes the general transfer function of a filter in the z-domain. This filter can be

realized effectively as a so called IIR (infinite impulse response) structure. (5.1.3) can be

realized as a cascade of two systems

H ( z) = H 1( z) H 2( z) (5.1.4)

where H 1( z) contains all the zeros and is an FIR system, H 2( z) describes an IIR system,

containing all the poles of H ( z):




5.1 Loop Filter 67

2 H (z) 1H (z)

1-a

0 b

b 1

2 b

b

-1z

v (n)out v (n)

in

-1z

-1z

-1z

M-1

M b

2 -a

N-1-a

N -a

-1z

-1z

Figure 5.2: Realization of an IIR filter in direct form I

H 1( z).

= M

∑k =0

bk z−k (5.1.5)

H 2( z).

=1

1 + ∑ N k =1 ak z

−k (5.1.6)

When H 1( z) is placed before H 2( z) in the signal path, the realization will look like fig. 5.2, itis called “direct form I”. Placing H 2( z) before H 1( z) gives a structure called “direct form II”

(fig. 5.3) that is more efficient because it needs less delays (i.e. registers).

v (n)out

v (n)in

1H (z)

2 H (z)

b 1

b

z

-1z 0 b

-1

M-1

M b

2 -a

1-a

-1z

N-1-a

N -a

Figure 5.3: Realization of an IIR filter in direct form II

The transformation procedure will be demonstrated in detail for a simple RC lowpass:

5.1.2 1st Order Low PassA first order RC lowpass with the transfer function





vout (s)

vin(s) =

1

1 + sC 1 R1 (5.1.7)

can be transformed into a digital filter using the bilinear transform:

H ( z) =vout (n)

vin(n)=

1

1 + 2C 1 R1T S

z−1 z+1

=

1

1 + k 11

1− z−1

1+ z−1

with k 11.

=2C 1 R1

T S

=1 + z−1

1 + k 11 + z−1 (1− k 11)

= K 11 + z−1

1 + a11 z−1

with K 1.

=1

1 + k 11

and a11.

= K 1 (1

−k 11) (5.1.8)

This low pass can be easily realized using a “direct form II” structure (fig. 5.4).

1b = 1

in v (n)

K

-a

0 b = 1

z -1

H (z) 2 H (z)

1out

v (n)

1

Figure 5.4: IIR implementation of 1st order RC low pass

This structure can be translated into VHDL or Verilog quite easily, where z−1 is the delay of one sample interval T s:

5.1.3 2nd Order Low Pass

A second order low pass with the transfer equation

vout (s)

vin(s)=

1

k 22s2 + k 21s + 1with k 21 = R1C 1 + R1C 2 + R2C 2 and k 22 = R1 R2C 1C 2 (5.1.9)

is mapped onto the z-plane in a similar way as the 1st order low pass:

H ( z) = vout (n)vin(n)

= 1k 22

z−1 z+1

2+ k 21

z−1 z+1

+ 1

=( z + 1)2

k 22 ( z− 1)2 + k 21 ( z −1)( z + 1) + ( z + 1)2

=z2 + 2 z + 1

z2 (k 22 + k 21 + 1) + z (2−2k 22) + k 22 − k 21 + 1

= K 2 z−2 + 2 z−1 + 1

a22 z−2 + a21 z−1 + 1(5.1.10)

with K 2

=1

k 22 + k 21 + 1, k

21= k

21

2

T S, k

22= k

22 2

T S2

and a22 = K 2 (k 22 − k 21 + 1) , a21 = K 2 (−2k 22 + 2)




5.1 Loop Filter 69

5.1.4 Third Order Low Pass

A third order low pass with the transfer equation

vout (s)

vin(s)=

1

k 33s3 + k 32s2 + k 31s + 1with k 33 = R1 R2 R3C 1C 2C 3,

k 32 = C 1C 2 R1 R2 +C 1C 3 R1 R2 +C 1C 3 R1 R3 +C 2C 3 R1 R3 +C 2C 3 R2 R3

and k 31 = R1C 2 + R2C 2 + R1C 3 + R2C 3 + R3C 3 + R1C 1

is transformed into a digital filter exactly as in the previous sections:

H ( z) = K 3b33 z

−2 + b32 z−2 + b31 z

−1 + 1

a33 z−3 + a32 z−2 + a31 z−1 + 1(5.1.11)

with K 3 =1

k 33 + k 32 + k 31 + 1, k 33 = k 33

2

T S

3

, k 32 = k 32

2

T S

2

, k 31 = k 31

2

T S

a33 = K 3 (−k 33 + k 32 − k 31 + 1) , a32 = 3K 3 (k 33 − k 32 − k 31 + 3) ,

a31 = K 3 (−3k 33 − k 32 + k 31 + 3) and b33 = 1, b32 = b31 = 3

5.1.5 Integrating Loop Filters

Integrating loop filters for PLLs are usually implemented together with a charge pump and

a tristate phase detector. They have a pole at the origin and at least one zero in the transfer

function to keep the loop stable (fig. 5.5).

Their transfer function can be converted to the z-Domain using the same method as described

R2

C2

C3C1

C1

C2

C3

R3

R1

R2

R3

to VCO

to VCO

PD/CP

PD

1st order

1st order

3rd order3rd order

2nd order

2nd order

−

+

b: Active Integratora: Charge Pump

Figure 5.5: Integrating Loop Filters

above:

vout (s)

vin(s)= xxx (5.1.12)

5.1.6 Loop Filter Modeling in VHDL

The following listing shows the basic implementation of a non-integrating IIR filter in VHDL

which is more or less self-explanatory:

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Common d e c l a r a t i o n s

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−





c o n s t a n t TS : r e a l : = r e a l ( TS 2 / f s )∗

5 . 0 e−

16 ;

−− 1 /2 s am pl in g i n t e r v a l

c o n s t a n t TSS : r e a l : = TS ∗ TS ; −− TS ∗∗ 2

c o n s t a n t TSSS : r e a l : = TS ∗ TS ∗ TS ; −− TS ∗∗ 3

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− f i r s t o r d e r f i l t e r c o n s t a n t s −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−c o n s t a n t k11 : r e a l : = R1 ∗ C1 / TS ;

c o n s t a n t K1 : r e a l := 1 .0 / ( k11 + 1 . 0 ) ;

c o n s t a n t a11 : r e a l := (−k 1 1 + 1 . 0 ) ∗ K1 ;

c o n s t a n t b11 : r e a l : = 1 . 0 ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− s e co n d o r d er f i l t e r c o n s t a n t s −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−c o n s t a n t k22 : r e a l := R1 ∗ R2 ∗ C1 ∗ C2 / TSS;

c o n s t a n t k21 : r e a l : = ( R1∗C1 + R1∗C2 + R2∗C2 ) / T S ;

c o n s t a n t K2 : r e a l : = 1 . 0 / ( k22 + k21 + 1 . 0 ) ;

c o n s t a n t a22 : r e a l := ( k22 − k21 + 1 . 0 ) ∗ K2 ;

c o n s t a n t a21 : r e a l := (− 2 . 0 ∗ k22 + 2 . 0 ) ∗ K2 ;

c o n s t a n t b22 : r e a l : = 1 . 0 ;

c o n s t a n t b21 : r e a l : = 2 . 0 ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− t h i r d o r de r f i l t e r c o n s t a n t s −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−c o n s t a n t k33 : r e a l : = C1 ∗ C2 ∗ C3 ∗ R1 ∗ R2 ∗ R3 / TSSS ;

c o n s t a n t k32 : r e a l : = ( C1∗C2∗R1∗R2+C1∗C3∗R1∗R2+C1∗C3∗R1∗R3

+ C2∗C3∗R1∗R3 + C2∗C3∗R2∗R3 ) / TSS ;

c o n s t a n t k31 : r e a l : = ( R1∗C2+R2∗C2+R1∗C3+R2∗C3+R3∗C3+R1∗C1 )

/ TS;

c o n s t a n t K3 : r e a l := 1 .0 / ( k33 + k32 + k31 + 1 . 0 ) ;

c o n s t a n t a33 : r e a l := ( −k33 + k32 − k 3 1 + 1 . 0 ) ∗ K3 ;

c o n s t a n t a32 : r e a l := ( 3 . 0 ∗ k33 − k3 2 − k 3 1 + 3 . 0 ) ∗ K3 ;

c o n s t a n t a31 : r e a l := (

−3.0

∗k33

−k 3 2 + k 3 1 + 3 . 0 )

∗K3 ;

c o n s t a n t b33 : r e a l : = 1 . 0 ;

c o n s t a n t b32 : r e a l : = 3 . 0 ;

c o n s t a n t b31 : r e a l : = 3 . 0 ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

I IR : p r o c e s s ( s c l k ) −− B a s i c I I R f i l t e r

b e g i n

i f s c lk ’ even t t h e n

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

−−F i l t e r D e f i n i t i o n : uncomment t h e n ee de d p a r t

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− F i r s t Or d er F i l t e r ( no z e r o )




5.1 Loop Filter 71

−−

−−mem1 <= C P v a l

∗K1

−a1 1

∗mem1;

−− v t u n e <= C P v a l ∗ K1 − a1 1 ∗ mem1 + b11 ∗ mem1;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− S ec on d O rd er F i l t e r ( n o z e r o )

−−−− mem2 <= mem1;

−− mem1 <= C P v a l ∗ K2 − a2 1 ∗ mem1 − a2 2 ∗ mem2;

−− v t u n e <= C P v a l ∗ K2 − a2 1 ∗ mem1 − a2 2 ∗ mem2

−− + b 2 1 ∗ mem1 + b22 ∗ mem2;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− T hi rd Or de r F i l t e r ( n o z e ro )

mem3 <= mem2;mem2 <= mem1;

mem1 <= CPval ∗ K3 − a31 ∗ mem1 − a32 ∗ mem2 − a33 ∗ mem3;

v t u n e <= CPval ∗ K3 − a31 ∗ mem1 − a32 ∗ mem2 − a33 ∗ mem3

+ b31 ∗ mem1 + b32 ∗ mem2 + b33 ∗ mem3;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

end i f ; −− e v e n t

en d p r o c e s s II R ;

The filter calculation is performed each time the clock signals_clk changes (s_clk’event),

i.e. twice per clock period. This clock is a kind of “ticker”, it is defined in yet another process

(also not shown). The clock frequency should be 10x ... 20x higher than the maximum input

frequency. Choosing a higher oversampling ratio improves the accuracy somewhat, however,a lot of events are generated which slow down simulation.

CPval is the state of the charge-pump (current multiplied with the input resistor of the filter)

or of the phase detector (voltage output). CPval is calculated in an extra process, here, non-

linearities of the charge-pump etc. can be incorporated if needed. mem1 etc. are the registers

( z−1 in the block diagrams). Values are shifted from mem1 to mem2 to mem3, the calculations

are performed from top to bottom and from right to left.

The sampling principle of the filter can be major problem in a PLL - this is true for an all-

digital PLL as well as for a behavioral simulation using a digital filter model. The reason

for this is that the filter has to run on a fixed sampling period T S1 while the charge pump can

basically switch at any time. This means, the filter will notice a change at the charge pumpoutput only with a delay of T S/2 in average. This is equivalent to the phase detector / charge

pump having an average timing error of T S/2 which has an disastrous effect for many sys-

tems unless you choose a very small sampling period. You’ll see some kind of beat frequency

effect as the PWM signal of phase detector interferes with the sampling period.

At least for behavioral modelling there is a solution: measure the time between the switching

of the phase detector / charge pump and the next sampling clock event and relate it to the

sampling period (“fractional” period). Then scale the filter input with this value - et voila!

This means, you translate the timing error into an amplitude error which can be handled by

the filter:

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− I I R f i l t e r w i th c o r r e c t i o n o f s a mp l in g e r r o r

1Ok, it is possible to use non-equidistant sampling, but you’ll be in REALLY deep water ...





−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−I IR : p r o c e s s ( s c l k , C P i )

v a r i a b l e T S f ra c v : r e a l ; −− f r a c t i o n a l t im e s t e p :

−− e v e nt d e l t a t im e r e l a t i v e

−− t o s a mp l in g p e r i od

v a r i a b l e T l as t v : t im e ; −− t im e o f l a s t c a l c u l a t i o n

v a r i a b l e f r a c f l a g : b o o l ea n ; −− f r a c t i o n a l c y c l e ?

v a r i a b l e f r a c f l a g d : b oo le an ; −− f r a c t i o n a l c y c l e ( p r e vi o u s ) ?

b e g i n

i f s c lk ’ even t or CP i ’ eve nt t h e n

i f (now − T l a s t v < TS 2t ) t h e n−− ” f r a c t i o n a l ” c y cl e : t i m e s i n c e l a s t e v e n t

−− i s l e s s t h a n TS :

T s fr a c v : = r e a l ( ( now − T l a s t v ) / f s ) / r e a l ( ( T S 2 t ) / f s ) ;

f r a cf l a g := t r u e ;

i f C P i = ’ 0 ’ t h e n −− CP h a s j u s t s w i t c h e d o f f

CPval <= T s f r a c v ∗ CP DC c ;

e l s e −− CP h as j u s t s w i t c he d on

CPval <= ( 1 . 0 − T s f r a c v ) ∗ CP DC c ;

end i f ; −− C P i

e l s e

−− n or ma l c y c l e

i f C P i = ’ 1 ’ t h e nCPval <= CP DC c ;

e l s e

CPval <= 0 . 0 ;

end i f ; −− C P i

f r ac f l a g d := f r a c f l a g ; −− s t o r e l a s t f r a c f l a g

f r a c f l ag := f a l se ; −− r e s e t f r a c f l a g

end i f ; −− t i m e s t e p

i f n o t f r a c f l a g d t h e n

T la s t v := NOW;

−−don ’ t s t o r e t i m e s t ep i f t h e l a s t one was a f r a c t i o n a l

−− o ne − o t h er w i se t h i s c y c l e wo u l d b e c a l c u l a t e d t w i c e

. . .

end i f ; −− i f n ot f r a c f l a g

end i f ; −− e v e n t

e nd p r o c e s s II R ;

5.1.7 Loop Filter Modeling Using Exponential Functions

Alternatively, the Laplace Transform can be used to calculate the step response of a filter:




5.2 VCO Modeling 73

5.2 VCO Modeling

The efficiency of VCO is increased tremendously by ignoring the amplitude information and

regarding only the zero crossings. The following simple VHDL model calculates the ideal

VCO period in fs. The result is scaled with a scaling factor f res which can be used to improve

the resolution (see below). Last cycle’s truncation error is added to the current period to avoid

accumulation of the error as this would give a period error of ca. 0.5fs (see section 5.3).

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− B e h a v i o r a l VCO m od el ( e x c e r p t )

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−. . .

b e g i n −− p r o c e s s FREQ GEN

v c o o u t <= ’ 0 ’ ;

p e r i o d t <= 3 00 p s ∗ f r e s ;

p e r io d e r r v := 0 . 0 ;

VCOLoop : l o o p

v c o o u t <= t r a n s p o r t ’1 ’ a f t e r VCODelay ,

’0 ’ a f t e r pe r i od t /2 + VCODelay ;

w ai t f o r p e r i o d t ;

p er io d v := f r e s / ( ( f 0 + kvco ∗ v t u n e i ) ∗ 1. 0 e −15)

+ p e r i o d e r r v ;

p e r i o d t <= ( p e r i o d v )

∗f s ;

−−p e r i o d i n f s

−− c a l c u l a t e t r u n c a t i o n e r r or :

p e r i o d e r r v : = p e ri o d v − r e a l ( ( p e r i o d v ∗ f s ) / f s ) ;

−− c a l c u l a t e d e v i a t i o n f ro m t a r g e t f r e q u en c y :

d e l t a f <= 1 . 0 e 15 / p e r i o d i d v ∗ f r e s − f t a r g ;

e nd l o o p VCOLoop;

en d p r o c e s s FREQ GEN;

v c o o <= v c o o u t ;

5.3 Accuracy Limitation of Sampled / Quasi-Analog Mod-els

The sampled nature of a digital simulator puts a limit to the achievable simulation accuracy.

Let’s have a look at the consequences:

5.3.1 Amplitude Quantization

Real numbers in VHDL are represented with double accuracy (64 bits) according to AN-

SI/IEEE Std 754-1985 (1 sign bit [S], 11 bits for the exponent [EXP], 52 bits [m] for the

mantissa). The value of such a real number is calculated from:

VALUE = (−1)S ∗ 2 EXP−1023 ∗1. mmm . . . m 52 bits





The 52 bits m of the mantissa (the fraction) have been normalized to have an integer part of

1, representing values in the range 1 . . . 2−

2−

52. As the normalized mantissa always has an

integer part of 1, it can be omitted in the binary representation (“hidden bit normalization”),

increasing the accuracy by one bit. The resulting accuracy of the fraction is

ε = 2−52 ≈ 2.2 ·10−16,

corresponding to approximately 16 decimal digits of accuracy.

The 11 bits for the exponent are biased with -1023, so the range of values is 2−1023 . . .2 ·21024.

In the decimal system, this corresponds to 1.1 ·10−308 . . .3.6 ·10308.

The gap between a number x and the next representation depends on the exponent, it is

∆ x = ε ·2

EXP

−1023

.This numerical range and accuracy is equivalent to “analog” simulators like Matlab or Spice

(which usually use the same binary representation), it should be more than sufficient for most

requirements.

5.3.2 Timing Quantization

In VHDL, events are timed using a 64 bit integer variable. The minimum timestep is T ε = 1

fs, the corresponding maximum time event takes place after 263 fs ≈ 2 1/2 hrs. This quanti-

zation creates a timing error T err ,q < T ε : if timing events are derived from calculations in real

format (see VCO model), the truncation will create the event a fraction of a fs earlier than

calculated: T qu = T id − ε . For autonomous (oscillating) systems, this timing error translates

into a frequency error f err :

Frequency error due to timing quantization

f err = f qu − f id =1

T id − T err ,q

− 1

T id

≈ 1 + T err ,q/T id

T id

− 1

T id

=T err ,q

T 2id

<T ε

T 2id

(5.3.1)

The average timing error can be brought to zero, giving a correct average frequency, e.g. by

summing up the error and correcting it in the next cycle. However, this correction will create

additional jitter with a uniform distribution in the range −T ε /2 . . .+T ε /2 with an RMS timing

error of T ε /(2√

3).

Usually, its spectrum is white up to the signal frequency (cyclostationary noise). In a first

order approximation2, this jitter is white PM noise (driven blocks) or FM noise (autonomousblocks).

EXAMPLE 3: Timing quantization error

A VCO model runs with a frequency near 4.0 GHz, corresponding to a period

of ≈ 250 ps. During the generation of the timing event, the fractional part of the

period (in fs) is truncated. This means, the period is always a little short - on

average3 by T ε /2 = 0.5fs. The resulting frequency error f err is (5.3.1)

f err ≈ T ε

2T 2vco,id

=1 fs

2 · (250 ps)2= 8kHz

2

assuming the error is uncorrelated3Only a crude approximation, the actual error depends on the period duration: when the VCO e.g. runs with

exactly 4 GHz, there will be no truncation error.




5.4 Noise Modeling 75

The resulting jitter is in the range of ±0.5fs, with a sigma of T ε /(2√

3) ≈ 0.29

fs. Referred to T vco

= 250 ps, the unit interval jitter is J UI ,rms ≈

1.2·10

−6. This

jitter is white FM noise with a PSD of ca. -134 dBc (1Hz) at 1 MHz offset.

5.4 Noise Modeling

5.4.1 Event Driven Approach

In event-driven languages like Verilog or VHDL, phase noise can only be represented in the

time domain i.e. as jitter. Therefore, the first step has to be to transfer phase noise specifica-

tions from the frequency into the time domain. This is not an easy task and is described for

some special cases in chapter 9.

Randon Number Generation

A random number source with a well defined characteristic is needed to model random

processes. Most programming languages offer some sort of pseudo-random number gen-

erator but its quality may be not sufficient for high-resolution simulations. Next, a simple

modulus arithmetic algorithm is described that produces pseudo-random sequences with a

length of 231− 2 and is suitable for 32 bit integer arithmetic. The random seeds may be odd

or even.

x(n) .= 75 ∗ x(n −1) mod (231 −1) (5.4.1)

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− PROCEDURE u n i d i s t

−−−− PURPOSE : G e n e ra t e a n u n i f o r m l y d i s t r i b u t e d n um be r

−− s tr ea m i n t h e r an ge [ 0 , 1 )

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− A l g o r i th m t a k e n f ro m :

−− T he A r t o f C om pu te r S y s t em s P e rf o rm a nc e

−− A n a l y s i s , R . J a i n 1 991 ( p . 4 4 3 )

−−−− h t t p : / / www . d e e p c h i p . com / p o s t s / 0 1 2 6 . h t m l

−− Mark G on za le s o f I n t e l

−−−− Usage ( s e e d1 v and r a nd 1 v a re o v e r w r i t t e n i n e ac h s t e p ) :

−−−− v a r i a b l e s e e d1 v : i n t e g e r := 1 23 ; −− i n i t i a l se e d

−− v a r i a b l e r an d1 v : r e a l ; −− o u t p u t

−−−− . . .

−−−− u n i d i s t ( s ee d 1 v , r a nd 1 v ) ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−





p r o c e d u r e u n i d i s t (

v a r i a b l e s ee d : i n o u t i n t e g e r ;

v a r i a b l e X : o u t r e a l ) i s

c o n s t a n t a : i n t e g e r := 16807; −− = 7 ∗∗ 5

c o n s t a n t m : i n t e g e r := 2147483647; −− = 2∗∗31 − 1

c o n s t a n t q : i n t e g e r := 127773 ; −− m D IV a

c o n s t a n t r : i n t e g e r := 2836 ; −− m MOD a

c o n s t a n t m r e a l : r e a l := r e a l (M) ;

v a r i a b l e s ee d d i v q : i n t e g e r ;

v a r i a b l e s ee d m od q : i n t e g e r ;

v a r i a b l e new seed : i n t eg e r ;

b e g i n

s e ed d i v q : = s eed / q ; −− t r u n c a t i n g−− i n t . d i v i s i o n

s ee d m od q : = s e ed mod q ; −− m o d u l u s

new seed := a ∗ seed mod q − r ∗ s e e d d i v q ;

i f ( new seed > 0) t h e n

s e e d : = n e w se e d ;

e l s e s e ed : = n ew s ee d + m;

end i f ;

X := r e a l ( s eed ) / m r e a l ;

en d u n i d i s t ;

An alternative in VHDL would be to use RAND() / GET_RAND_MAX() from the MATH_REAL

package to get a uniformly distributed pseudo-random number. Use SRAND(seed) to seed a

new random stream. However, sequence length is unknown, which might create false period-

icities.

The superposition of many microscopic uniform processes results in a macroscopic process

with gaussian distribution (central limit theorem). Therefore, one way to generate a gaussian

distributed random process is to generate some uniformly distributed samples and calculate

their average. For most applications, superposition of ten samples should be enough to ob-

tain one sample of a Gaussian process. One drawback of this approach is that the effective

sequence length of the resulting Gaussian process is only one tenth of the uniform process,

another one is of course the increased computational effort. Another aproach is described

in [PM96], where two uncorrelated uniform processes x1(n), x2(n) are transformed into two

uncorrelated gaussian processes xn,1(n), xn,2(n). First, one of the processes is transformedinto a random process x R,1(n) with Rayleigh distribution:

x R,1(n) :=

2log

1

1− x1(n)(5.4.2)

Two processes with Gaussian (normal) distribution (m = 0, σ = 1) can be derived from

x R,1(n) and x2(n):

xn,1(n) = cos(2π x2(n)) · x R,1(n) (5.4.3)

xn,2(n) = sin(2π x2(n)) · x R,1(n) (5.4.4)

The average value and standard deviation of xn,1(n), xn,2(n) is easily changed by adding an

offset m resp. scaling with a factor σ . The computational effort for calculating the transcen-




5.4 Noise Modeling 77

dental functions sqrt(), log(), sin() and cos() is quite high but at least the sequence length is

not reduced.

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− PROCEDURE n o r m di s t

−−−− Usage :

−− s e ed and norm m us t be v a r i a b l e s , n o t c o n s t a n t s !

−− . . .

−−−− n o r m d i s t ( s e e d1 v , s e e d2 v , s i gm a1 c , m c1 , n or m1 v ,

−− s i g ma 2 c , m c2 , n or m 2 v ) ;

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

p r o c e d u r e n o r m d i s t (

v a r i a b l e s ee d1 : i n o u t i n t e g e r ; −− S ee d f o r 1 s t r nd nu mb er

v a r i a b l e s ee d2 : i n o u t i n t e g e r ; −− S ee d f o r 2 nd r nd nu mb er

c o n s t a n t sigma 1 : i n r e a l ; −− S ig ma 1

c o n s t a n t m1 : i n r e a l ; −− A vg . 1

v a r i a b l e norm1 : o u t r e a l ; −− n o r m a ll y d i s t r i b u t e d

c o n s t a n t sigma 2 : i n r e a l ; −− S ig ma 2

c o n s t a n t m2 : i n r e a l ; −− A vg . 2

v a r i a b l e norm2 : o u t r e a l −− n o r m a ll y d i s t r i b u t e d

) i s

−−o u t p u t v a r i a b l e

c o n s t a n t TWO PI c : r e a l : = 2 . 0 ∗ MATH PI ;

v a r i a b l e r r a n d : r e a l := 0 .0 ; −− R a yl e i gh d i s t r i b u t e d random

−− numb . i n t h e r a ng e [ 0 , 1 )

v a r i a b l e rand1 : r e a l ; −− u n i f or m ly d i s t r i b u t e d

v a r i a b l e rand2 : r e a l ; −− random v a r i a b l e s

b e g i n

u n i d i s t ( s ee d 1 , r a n d 1 ) ;

u n i d i s t ( s ee d 2 , r a n d 2 ) ;

r ra nd := SQRT (2 .0 ∗ LOG ( 1 . 0 / ( 1 . 0 − ra nd 1 ) ) ) ; −− R a y l e i g h

−− d i s t r i b .norm1 := m1 + s igma1 ∗ COS( TWO PI c ∗ ran d2 ) ∗ r ra nd ;

norm2 := m2 + s igma2 ∗ SIN ( TWO PI c ∗ ran d2 ) ∗ r ra nd ;

en d n o r m d i s t ;

White Noise

In the simplest case, phase noise has a white spectrum and a gaussian distribution. It is spec-

ified by a single figure in the frequency domain because the power spectral density (PSD)

is constant over frequency. Correspondingly, in the time domain the jitter is completely

described by its standard deviation σ . In spite of its simplicity, this noise / jitter model de-

scribes many real-world systems with sufficient accuracy. The reason for this is that added

white gaussian noise is such an omnipresent phenomenon that it was even awarded an own

acronym (AWGN). AWGN is translated into timing error (or jitter) by nearly every signal





processing stage.

How can white phase noise be modeled in e.g. VHDL? First we’ll look at non-autonomous

blocks like a logic gate or a buffer. These blocks process an event at their inputs and pass it

on to the output with a certain latency. This latency depends on the slew rate at the input, the

speed of the actual circuit etc. The latency varies in a random fashion due to e.g. thermal

noise in the circuit.

5.5 Spectral Estimation of Simulation Results

In contrast to an analog or mixed-signal simulator, there is no easy way to regard simulation

results in the frequency domain with a digital simulator. One workaround to this dilemma is

described in [Kun98], where the period data of the VCO is written to a text file and analyzed

using a MATLAB script. Due to the simplified VCO model, only the VCO period data isavailable. Spectral data like phase noise and spurious sidebands are contained in the devia-

tions of the zero crossings from ideal times.

Summing up the periods yields the output phase of the VCO over time which approximates

the ideal VCO phase 2π f vco,id · t , a linear slope. However, running a Fourier analysis of this

”raw” phase data is a bad idea because the actual spectral information is smothered by the

spectral components of the linear slope, especially at low frequencies4. A much better res-

olution is achieved by first subtracting the linear phase due to the average VCO frequency

2π f vco · t which can be extracted easily from the period data. Assuming the PLL is in locked

state, the average frequency of the VCO is constant.

MATLAB can remove the slope automatically by giving the option ”detrending” for the

power spectral density calculation. A basic MATLAB script for analysis of the VCO spec-

trum looks like this:

% R ea d VCO P e r i o d D at a f r om t e x t f i l e

n r e a d = −1; % re ad a l l s am pl es

[ vco pe r iod s ] = t e x t re ad ( ’VCO data . t x t ’ , ’%f ’ , n read ) ;

% C a l c u l a t e # o f s am pl es , avg . , max . and s t d . d e v i a t i o n o f p e r i o d s

N sample = l e n g t h ( v c o p e r i o d s ) ; % No . o f s am pl es

T m = mean ( v c o p e r i o d s ) ; % A vg . p e r i o d

J m = s t d ( v c o p e r i o d s ) ; % S t d . Dev . o f p e r i o d s

s t d d p h i = J m / T m ; % S t d . Dev . o f p ha s e

max dph i= max ( ab s ( v c o p e r i o d s

−T m ) ) / T m ; % Max . Dev . o f p h as e

n f f t = 3 27 68 ; % = 2 ˆ 15

w in Le ng th = n f f t ;

o v e r l a p = f i x ( n f f t / 2 ) ; % 50% O v e r l a p

winNBW = 1 . 5 ;

rbw=winNBW/ ( T m∗ n f f t ) ;

% C a lc u l at e v e c t o r w i t h c u mu l a t i v e p ha se

c u m p h i v c o = 2 ∗ p i ∗ cumsum ( v c o p e r i o d s ) / T m ;

% Remove t h e l i n e a r p a r t o f t h e VCO p ha se and e s t i m a t e

% i t s Power S p e c t r a l D e n si t y4A constant slope in the time domain has a PSD increasing with 60dB / dec towards zero




5.5 Spectral Estimation of Simulation Results 79

[Sphi VCO , f ]= psd ( cum ph i vco , n f f t , 1 /T m, winL ength , ove r la p , ’ l i ne a r ’ ) ;

N f = l e n g t h ( f ) ;

% Ap p l y c o r r e c t s c a l i n g ( 2∗ D e l t a T / N FFT )? ?

Sphi VCO = winNBW ∗ Sphi VCO / n f f t ;

% F in d maximum a nd c o r r e s p o n d i n g f r e q u e n c y

[ MaxSphi2 VCO , Maxfs2 ] = max( Sphi VCO ) ;

f i g u r e ( 1 ) ;

c l f ;

s e m i l o g x ( f ( 2 : N f ) , 10∗ l o g 1 0 ( Sp hi 2 (2 : N f ) ) ) ;

h o l d on ;

x l a b e l ( ’ Frequency (Hz) ’ ) ;

y l a b e l ( ’ S \ p h i ( dB [ 1 Hz ] ) ’ ) ;t i t l e ( ’VCO PSD ’ , . . .

’ f o n t s i z e ’ , 1 2 , ’ f o n t w e i g h t ’ , ’ b o l d ’ ) ;

The actual estimation of the power spectral density of the dicrete-time VCO phase data is

performed using Welch’s averaged, modified periodogram method. This method reduces the

variance in the spectral estimate at the cost of reduced frequency resolution.

[P XX , f ] = psd (X, N FFT , Fs , N WINDOW, N OVERLAP, ’ l i n e a r ’ ) ;

The time discrete data X is split into sections of length N_FFT, overlapping by N_OVERLAP.

An overlap of NFFT/2 (50%) usually gives good results. Each segment is ”detrended”, i.e.

the constant linear slope is removed before it is windowed with a Hanning window of length

N_WINDOW = N_FFT. The magnitude squared DFTs with length N_FFT of each segment are

averaged and stored in the vector P_XX with length NFFT/2. The parameter Fs is only neededto generate the second vector f with the properly scaled frequency data for the x-axis of the

PSD - plots. It has the same length as P_XX.

Other windowing functions are possible as well, e.g. KAISER(512,5) for a Kaiser window

with order 5 and with length 512. Additionally, the confidence interval for the PSD can be

stored as well by

[ P XX , P xx c , f ] = ps d (X , N FFT , Fs ,N WINDOW,N OVERLAP, p , ’ l i n e a r ’ ) ;

where p is a scalar (range 0 . . . 1, default 0.95) and P_xxc is a matrix with 2 rows containing

the p * 100% confidence interval for P_xx.




Part II

Spurious Sidebands

81



Chapter 6

Reference Frequency Feedthrough

Musik wird storend oft empfunden,

dieweil sie mit Gerausch verbunden.

Wilhelm Busch

Overview: In this chapter, the mechanisms of spurious sideband creation

are explained using the example of disturbances on the loop filter voltage.

After a little modulation theory, the effects of sinusoidal and general periodic

disturbances are analyzed. The important cases of DC currents flowing into the loop filter and of short error pulses are presented in detail.

6.1 FM / PM Modulation Basics

Spurious sidebands are created by a disturbing signal that somehow interferes with the car-

rier, creating additional tones besides the carrier. A little modulation theory is needed before

diving into the more practical issues of spurious estimation and avoidance. In this chapter,

modulation of the VCO tuning voltage by the reference frequency will serve as an example

for a disturbing signal because it is a common problem (fig. 6.1) and can be analysed in a

relative painless way.

When e.g. up- and down-pulses are not perfectly synchronized or otherwise mismatched, a

net error current ie(t ) flows into the loop filter that is periodic with the reference frequency

f re f . It is converted by the loop filter impedance Z LF (s) into a voltage error ve(t ) of the VCO

control voltage (see chapter 2.5.2). At the VCO output, they can be observed as spurious

sidebands around the carrier frequency f 0 (see fig. 1.1) with offsets of ±k f re f ; k = 1,2, . . ..

In order to analyze the effect of these disturbances, a little modulation theory is needed: The

PLL is assumed to be in locked state with a static VCO control voltage V CTRL. The ideal VCO

output frequency ω 0 has a constant part - the base frequency ω B at zero control voltage - and

a tuned part ∆ω ctrl = 2π K vcoV CTRL. The tuning sensitivity of the VCO describes the relation

between a change in control voltage and the resulting change in output frequency. It is given

by K vco .= ∂ f 0/∂ vctrl . K vco is always somewhat dependent on the DC value of the control

voltage, V ctrl , but this will be ignored here. In addition to these static components, a small

83



84 Reference Frequency Feedthrough

fVCO

fout

fref

fref

fsys

f = f / NVCOref

+PD

CP

1

R

F(s)

1

N

1

D

fref

fref

Phase Detector /Charge Pump

Filter

Loop

N−Divider

ReferenceDivider

LO−DividerVCO

Figure 6.1: Spurious generation due to reference frequency leakage

, φωvco vco

N1

V ctrl + ve

i up

i e

i dn

φ=φdiv vco

N

φdiv

refφ

PD

down

upVCO

Divider

Charge Pump

Loop Filter

cut here

to open loop

F(s)

Phase Detector

Figure 6.2: Block schematic of a PLL

error voltage ve(t ) sits on top of V CTRL (|ve| V CTRL, see Fig. 1.1), causing an unwanted

frequency modulation of ∆ω e(t ) = 2π K vcove(t ). The output signal of the VCO is given by:

svco(t ) = Acos(ω Bt + ∆ω CTRLt + ∆ω e(t ) t )

=Acos

(ω

0t

+ ∆ω

e(t )

t )

(6.1.1)

= Acos(ω 0t + 2π K vcove(t ) t )

showing that ve(t ) causes a frequency modulation. The effect of ve(t ) can be analyzed more

easily when it is given as a phase modulation1. Frequency modulation is transformed into

phase modulation by integrating the modulation signal:

∆φ e(t ) =

t

−∞ω e(τ ) d τ = 2π K vco

t

−∞ve(τ ) d τ (6.1.2)

Using (6.1.2), the frequency modulation of the VCO (6.1.1) can be expressed as a phase

modulation:

1The reason for this is the term cos(. . . ve(t )t . . .) that cannot be expanded using Bessel functions as described in

the appendix.




6.2 Sinusoidal Disturbance of Tuning Voltage 85

svco(t ) = A cos(ω 0t + ∆ω e(t ) t )

= A cos

ω 0t +

t

−∞ω e(τ ) d τ

= A cos

ω 0t + 2π K vco

t

−∞ve(τ ) d τ

(6.1.3)

= A cos(ω 0t + ∆φ e(t ))

In the next sections, some typical disturbances of the VCO control voltage caused by refer-

ence frequency feedthrough are analysed.

6.2 Sinusoidal Disturbance of Tuning Voltage

We first look at the case of a sinusoidal modulation signal ve(t ) = m cosω 1t with amplitude m

and frequency f 1: This disturbance can be caused e.g. by e.g. a signal coupling capacitively

onto the control voltage or by charge pump pulses, heavily filtered by the loop filter. Using

(6.1.2), the phase of the modulating signal is calculated as:

∆φ (t ) = 2π K vco

t

−∞mcosω 1τ d τ

=mK vco

f 1sinω 1t

= µ sinω 1t where µ = mK vco/ f 1 (6.2.1)

(see appendix G.5 about the integration), µ is called modulation index. In a proper PLL de-

sign, disturbances and hence the modulation index are small, in this case the output spectrum

can be approximated using the Low Modulation Index Approximation (D.1.3) described in

appendix D:

Low Modulation Index Approximation

svco(t ) = Acos(ω 0t +µ sinω 1t )

≈ Aµ

2cos(ω 0t +ω 1t ) + cosω 0t − µ

2cos(ω 0t −ω 1t )

(6.2.2)

The resulting VCO output signal has two new components at f 0 ± f 1 with relative levels of:

s±1 ≈ µ

2=

mK vco

2 f 1≡ 20log

µ 2

dBc (6.2.3)

(6.2.3) shows that the modulation effect decreases with the modulation frequency - this is a

consequence of the integrating behaviour of the VCO concerning its control signal. The exact

spectrum of the VCO output signal is given in the appendix D: (D.1.1) shows that the output

signal has additional sideband spurs at ±k f 1 (k = 2, 3, . . .) around the carrier, created by the

non-linearity of frequency modulation. In contrast to that, the low-modulation index FM ap-

proximation (6.2.2) predicts only sidebands at ± f 1 which is only approximately correct for

low modulating indices.

Note: Spurious levels in this paper are always given relative to the carrier amplitude A,

sometimes with the pseudo-unit dBc (c : carrier). As most spurs are symmetrical with respect





to the carrier, usually no difference is being made between lower and upper sidebands, i.e.

s+1

= s−1

= s1.

f 0 f +f0 n

f −f0 n

|S (f)|

f 0f0 f +f0 n

f +f0 n

|S (f)|

ff

A02

0N /4

02µ2

A /8

02

A /2

00

02

A /4

02µ2

A /16A0

20N /8

0

Single sided Double sided

Figure 6.3: Comparison of single and double sided notation

In this paper, spectra are given in “engineering notation”, i.e. using only positive frequencies

(unless noted otherwise)2 - see also appendix A on this topic. Spectra of real-valued (real

life) signals are always symmetric with respect to the 0 Hz point. “Engineering” spectra are

denoted with a single index, “mathematical” spectra with a double index:

S0( f ) = 2S00( f ) for f ≥ 0

This definition ensures that energy / power of “engineering” and “mathematical” spectra are

the same.

EXAMPLE 4: Spurs caused by a sinusoidal disturbance

The VCO control voltage (K vco =50MHz/V) is disturbed by a sinusoidal signal

with the frequency f 1 = 200kHz and amplitude m = 1mV. What does the output

spectrum look like? The disturbance causes a frequency modulation of the VCO

with a modulation index of µ = mK vco/ f 1 = 0.25, producing the first sideband

spurs ( f 0 ± f 1) at 20log(µ /2) = −18dB below the carrier (6.2.3).

Due to the nonlinearity of frequency modulation there are also higher order

harmonics not predicted by (6.2.2): The exact calculation (D.1.1) gives sec-

ond order sideband spurs ( f 0 ± 2 f 1) with levels of 20log(µ 2/8) = −42dBc.

This means, a modulation index of 0.25 is not “low”. In order to keep second

(and higher) order harmonics below e.g. -100dBc, a modulation index less thanµ = √

8 ·10−100/20 = 0.009 is necessary. Using the data above, this corresponds

to a maximum amplitude of m = f 1µ /K vco = 36µ V, producing first order spurs

of 20log(µ /2) = −41dBc. Obviously, the VCO input is a very sensitive node in

the system!

Note: A low-modulation index FM spectrum is identical to the spectrum of a double side

band (DSB) AM signal with an AM modulation index µ AM = m/ A < 1 except for the phase

reversal of the lower sideband. However, power spectrum and occupied bandwidth are the

same. FM with a high modulation index (e.g. FM radio) has a lot of excess bandwidth due

to higher order harmonics. Therefore, low-modulation index FM is also called “Narrowband

FM”:2Not to be confused with positive / negative offset frequencies from the carrier!




6.3 Periodic Disturbances of Tuning Voltage 87

s AM

(t ) = A+µ AM

2cos(ω

0t −ω

1t ) + cosω

0t +

µ AM

2cos(ω

0t +ω

1t )

6.3 Periodic Disturbances of Tuning Voltage

In most cases, disturbances of the loop filter voltage will not be sinusoidal because many

signals on-chip are switched signals with a high harmonic content.

However, the procedure for calculating the effect of these disturbances is quite similiar to last

section: A periodic signal ve(t ) with the fundamental frequency f 1 can be decomposed into

an infinite Fourier series (see appendix A):

ve(t ) =∞

∑k =1

ck cos(k ω 1t +φ k )

where ck is the amplitude of the k-th harmonic and φ k is its phase. It has been assumed thatve(t ) is DC-free (c0 = 0) because a locked PLL compensates static and slow3 changes of the

VCO output frequency ω 0.

The spurious sidebands created by such a signal can be calculated in a similiar fashion as for

sinusoidal disturbances: each harmonic of the modulating signal is upconverted around the

carrier separately (fig. 6.4).

mod|S (f)| |S (f)|vco

reff 2fref

f

vco,mod|S (f)|

f0 ref−f f0 f0+f reff0

x =

ff

Figure 6.4: Periodic Disturbance of Control Voltage

However, this is only allowed for low modulation indices where frequency modulation be-

haves in a nearly linear way and superposition can be applied. At the VCO output, the

amplitude of the k-th harmonic is attenuated by 1/k f 1 due to the integrating behaviour of the

VCO:

svco(t ) = Acosω 0t +

∞

∑k =1

µ k

2 (cos(ω 0t + (k ω 1t +φ k )) − cos(ω 0t − (k ω 1t +φ k )))where µ k =

K vcock

k f 1(6.3.1)

is the modulation index for the k-th harmonic. A periodic disturbance of the VCO control

voltage with fourier coefficients ck produces spurious sidebands with relative levels sk of

Spurious Sidebands Caused by Periodic Disturbance

sk

≈µ k

2

=K vcock

2k f 1

; k = 1,2, . . . (6.3.2)

3frequencies within the loop bandwidth.





(6.3.2) allows an easy simulation / calculation of the spurious sidebands of a locked PLL:

• Run a transient simulation of the PLL long enough until it is in locked state.

• Run a Fourier analysis on the VCO control voltage waveform. This gives the ck ’s.

• Multiply ck by K vco/(2k f re f ) to obtain the relative amplitude of the k-th spurious side-

band.

In contrast to that, it is nearly impossible to obtain this result directly from the VCO’s phase

with a harmonic balance or periodic steady-state analysis, especially when analyzing a fre-

quency synthesizer with a high ratio between VCO and reference frequency: many reference

cycles are needed before the PLL is locked and the phase error is low enough to start a fourier

analysis. In periodic steady state analysis, the simulation needs to cover at least one cycle of

the lowest frequency in the circuit (reference frequency in this case) which takes a lot of com-

puting time as many VCO cycles have to be simulated in the same time. Achieving a locked

state in a periodic steady state analysis is therefore impossible with the average computing

power available today.

6.4 Sidebands Induced By DC Leakage Current

When a DC error current ie(t ) = I L flows into an integrating loop filter (Type II PLL)4, the

output voltage ve(t ) will be a ramp (see fig. 6.5), reset by the PD/CP every T re f . A DC

leakage current can be caused e.g. by lossy capacitors in the loop filter or ESD damage of the

charge pump output. At the reference frequency, the loop filter can be approximated by the

equivalent loop filter capacitance C ∗1 (see section 2.5.2) which is approximately equal to theanti-ripple capacitor C 1:

riseTTref

IL

Tw

I cp

i (t)cp

v (t)e

m

t

t

Figure 6.5: Disturbance Caused by DC Leakage Current I L

ve(t ) =I L

C ∗1· t for 0 ≤ t < T re f

In a closed loop, ve(t ) is reduced to zero at the end of each reference cycle ( t = T re f ) by a

short charge pump pulse of opposite polarity. If I L

I CP, the charge pump pulse is very

4Type I PLLs are relatively immune to this kind of disturbance because they don’t integrate the leakage current -

here, a DC current merely generates an constant offset that is compensated by the loop.




6.4 Sidebands Induced By DC Leakage Current 89

short and the rise time of the voltage ramp is T rise ≈ T re f , i.e. ve(t ) can be approximated by a

periodic sawtooth function saw(t) with an amplitude m of

m ≈ I L

C ∗1· T re f (6.4.1)

As usually, the DC part (m/2) of ve(t ) is suppressed by the locked loop:

ve(t ) = m

saw

t

T re f

− 1

2

(6.4.2)

where saw(t ) is the periodic sawtooth function with period and amplitude of 1. This requires

that the sum of the charges due to I L and I CP is zero over each period:

I cp T w = I L

T re f − T w

≈ I LT re f forT w T re f

The Fourier coefficients of sawtooth function ve(t ) are:

ck =m

π k ; k=1,2,...

The level of the VCOoutput spurious sidebands canbe calculated using (6.3.2) with f 1 = f re f :

Spurious Sidebands Caused by DC Leakage Current

sk =K vcom

2π k 2 f re f =

K vco I L

2π C ∗1 k 2 f 2re f

; k = 1,2, . . . (6.4.3)

(6.4.3) allows to estimate quickly the effect of design changes, e.g. how much spurious side-

bands are reduced by increasing the reference frequency or the loop filter capacitance. Or,

how much the leakage current requirements can be relaxed while maintaining the same spu-

rious performance. (6.4.3) also shows once more that a high K vco makes the system more

sensitive to leakage currents into the loop filter (and to modulation effects in general) and

should be avoided if possible.

EXAMPLE 5: Spurs due to DC leakage current

An integrating loop filter with the following elements (see fig. 2.11)

C 2 = 5.6nF, R2 = 3.3k Ω ⇒ T 2 = 18.5µ s ( f 2 = 8.6kHz), b = 15.4C 1 = 390pF ⇒ T 1 = T 2/b = 1.2µ s ( f 1 = 132kHz)

C 3 = 120pF, R3 = 8.2k Ω ⇒ T 3 = 1µ s ( f 3 = 162kHz - post-filter)

is used in a PLL with reference frequency f re f = 200kHz and K vco = 80MHz/V,

the DC leakage current is I L = 80nA. As f re f f 2, the equivalent loop filter

capacitance is C ∗1 ≈ C 1. The amplitude of the resulting sawtooth voltage (6.4.1)

on the loop filter voltage is m ≈ 1mV. With this data, the spurious sidebands

without a post-filter can be calculated (6.4.3). The attenuation of the post-filter

| A3( f )| is calculated separately (see section 2.6):

Sideband No. 1 2 3 5

Offset Frequency [kHz] 200 400 600 1000

Spurious (no post-filter) 0.065 0.016 0.0073 0.0023

Spurious [dBc] (no post-filter) -24 -36 -43 -52

| A3( f )| [dB] (post-filter) -2 -8 -12 -16

Spurious [dBc] (w/ post-filter) -26 -44 -55 -68





Note: Alternatively, the spurious sidebands can also be calculated by multiplying the Fourier

transform of the error current icp (t ) with the loop filter transfer function. Although this

way is more complicated than analyzing the sawtooth error voltage directly, this method

has advantages with more complex error currents like the ones of fractional-N PLLs (chapter

8):

icp (t ) = I L − I cp · rectt

T w

∞

∑k =−∞

δ (t − kT re f )

−• I cp ( f ) = 2 I CP

T w

T re f

∞

∑k =1

sincπ kT w

T re f ·δ f − k

T re f ≈ 2 I L

∞

∑k =1

δ

f − k

T re f

for f 1

T w

because

sinc

π kT w

T re f

≈ 1 for kT w T re f

The frequency spectrum of the loop filter error voltage V e( f ) is calculated by

V e( f ) = I cp ( f ) · Z LF ( f )

≈ 2 I L

∞

∑k =1δ f −

k

T re f ·1

2π C ∗1 k f re f

⇒ V e

k f re f

=

I L

π C ∗1 k f re f

(6.4.4)

Using (6.3.2) once more to calculate the spurious response, gives the same result as (6.4.3):

sk ≈K vcoV e

k f re f

2k f re f

=K vco I L

2π C ∗1 k 2 f 2re f

6.5 Narrow Pulses on the Tuning Voltage

Often, the disturbances of the VCO control voltage are short pulses v p(t ) (Fig. 6.6) with arepetition rate equal to the reference frequency f re f . Their pulse width T w usually is much

shorter than the pulse period T re f = 1/ f re f .

A very narrow pulse can be approximated by a dirac pulse

v p(t ) ≈ wδ (t ) −• V p( f ) ≈ w (6.5.1)

where

w =

+T re f /2

−T ref /2v p(t )dt ≈ V p( f ) for f 1/T w (6.5.2)

w is the area or weight of the pulse. A dirac pulse with weight w has a flat spectrum with a

spectral amplitude density of w. For real life narrow pulses this is only approximately true as

long as f 1/T w (fig. 6.6).




6.5 Narrow Pulses on the Tuning Voltage 91

V (f) = w sinc fT /2

sinc fT

v (t)p

V (f)p

p π w2

wT

Tr

1/Tw w2/T

w=mTw

w=mTw

w=m(T + T )w r

pV (f) = w

pV (f) = w sinc fTπ w

1/Tw w2/T 1/Tr

w2/T

π r

mf

w

(w)

2m

f

f

w

w

mf

w

w=(w)

t

t

t

t

Figure 6.6: Spectra of Single Short Pulses v p(t )

Periodic short pulses are expressed mathematically by folding a single pulse v p(t ) with a peri-

odic dirac function ↑↑↑(t /T re f ). In the frequency domain, this corresponds to multiplying the

Fourier transformed pulse V p( f ) with the periodic dirac frequency function f re f ↑↑↑( f / f re f )(6.5.3), i.e. the spectrum of the single pulse V p( f ) (dashed line in figure 6.7) is the envelope

of the periodic dirac frequency function:

v (t)e

reff

V (f)e

ref(w/T )

ref(w/T )

ref(w/T )1/T

w 2/Tw w3/T

2/TwwT

wT

refT

f

f

f

2m

m

(w)(w)

t

t

t

Figure 6.7: Spectra of Periodic Short Pulses ve(t )

ve(t ) = v p(t ) ∞

∑n=−∞

δ (t − nT re f ) −• V p( f )

T re f

∞

∑n=−∞

δ

f − n

T re f

(6.5.3)

(for the definition of the periodic dirac function see (A.4.5) and (A.4.6)). If the pulses are

very narrow, they can be approximated by periodic dirac pulses with a constant weight w:

ve(t ) ≈ w∞∑

n=−∞δ (t − nT re f ) −• w

T re f

∞∑

n=−∞δ

f − n

T re f

(6.5.4)





Such a pulse train has spectral lines at multiples of f re f with constant fourier coefficients of

ck

= 2w/T re f

. Using (6.3.1), the resulting VCO output signal becomes:

svco(t ) ≈ A

cosω 0t ±

∞

∑k =1

K vcow

k cos

ω 0 ± k ω re f

t

(6.5.5)

This leads to a really simple formula for the magnitude of sidebands produced by short pulses:

Spurious Sidebands Caused by Short Disturbances

sk ≈ wK vco

k ; k = 1, 2, . . . (6.5.6)

i.e. the spurious levels created by short pulses5 on the VCO control voltage are independent of the actual pulse shape and the reference frequency, they are only determined by the pulse

weight w and the VCO tuning sensitivity K vco.

The following examples illustrate this result:

A rectangular pulse train with an amplitude m, a pulse width T w and a repetition period of

T re f has a duty cycle α = T w/T re f and pulse weights of w = mT w (see Fig. 6.7). Its fourier

(magnitude) coefficients are:

ck = 2mα · sink πα

k πα = 2mα sinc(k πα ) ; k = 1,2, . . . (6.5.7)

This means, the pulse spectrum has lines at k f re f , modulated by a sinc(x) function with thefirst zero at f re f /α = 1/T w (see Fig. 6.7). For narrow pulses, α 1 and sinc(k πα ) ≈ 1, i.e.

the first few coeffients have a constant magnitude of ck ≈ 2mα = 2w/T re f , the DC content of

the pulse train is mα .

When this pulse train modulates a VCO, spurious sidebands result. Their relative amplitudes

sk are calculated with (6.3.2) and (6.5.7):

sk =mα K vco

k f re f

sinc(k πα ) ≈ mα K vco

k f re f

=wK vco

k for k 1/α (6.5.8)

EXAMPLE 6: Short rectangular pulses

Narrow rectangular pules with a width of T w = 3ns, an amplitude of m = 13mV

and a repition frequency of f re f = 200kHz disturb a VCO with a gain of K VCO =50MHz/V. What is the amplitude of the spurious sidebands?

⇒ α = 3ns · 200kHz = 6 ·10−4, w = mT w = 39pVs

⇒s1 = 2 ·10−3 ≡ -54dBc

s2 = 1 ·10−3 ≡ -60dBc

. . .

The first zero of the sinc(x) function is at 1/T w = 333MHz, which means the ap-

proximation is valid up to at least 1/(10T w) ≈ 30 MHz - far above the reference5“Short” meaning T w T re f /k , where T re f /k is the period of the k-th harmonic of f re f .




6.5 Narrow Pulses on the Tuning Voltage 93

frequency.

In praxis, triangular pulses are more common, usually mismatches of up- and down current

source create short current pulses that produce a triangular error voltage when integrated by

the loop filter:

A triangular pulse train with an amplitude m, a pulse width T w and a repetition period of

T re f has a duty cycle α = T w/T re f and pulse weights of w = mT w/2 (see Fig. 6.7). Its fourier

(magnitude) coefficients are:

ck

= mα ·

sink πα /2

k πα /2 2

= mα sinc2(k πα /2) ; k = 1,2, . . . (6.5.9)

The pulse spectrum is similiar to the spectrum of the rectangular pulse train: spectral lines

at k f re f are modulated by a sinc2( x) function with the first zero at 2 f re f /α = 2/T w (see Fig.

6.7). For α 1, the first few coeffients have a constant magnitude of ck ≈ mα (the sinc2( x)function is ≈ 1). The DC content is mα /2. Similiar to (6.5.8), the spurious levels at the VCO

output are:

sk =mα K vco

2k f re f

sinc2(k πα /2) ≈ mα K vco

2k f re f

=wK vco

k for k 1/α (6.5.10)

EXAMPLE 7: Short triangular pulses

T w = 4nS, f re f = 200kHz, K VCO = 40MHz/V, m = 1mV

⇒ α = 4ns · 200kHz = 8 ·10−4, w = mT w/2 = 2pVs

⇒s1 = 8 ·10−5 ≡ -82dBc

s2 = 4 ·10−5 ≡ -88dBc

. . .

The first zero of the sinc2( x) function is at 2/T w = 666MHz.

Both examples demonstrate that it is sufficient to calculate the weight of the disturbance

pulses when the pulses are short enough. This allows to estimate the magnitude of spurious

sidebands at the VCO output without doing a Fourier analysis.

The effect of static mismatch of the charge pump currents is analysed next: In locked

state, the total charge Qup + Qdown that is pumped into an integrating loop filter during one

reference cycle by iup and idown needs to be zero - otherwise the average VCO control voltage

and hence the carrier frequency would drift. Most phase detectors / charge pumps produce

pulses in locked state with a certain minimum length - the so called Anti-Backlash (ABL)-

Length T ABL - to avoid deadzone effects. When one of the currents is lower than the other by

∆ie, the corresponding pulse will be longer by ∆t e to compensate for the current mismatch: If

e.g. the Down-Current is idn = −i1 and the Up-current is iup = i1 −∆ie, the difference of the

pulse durations ∆t e will be:





iup

−idn

te

∆ TABL

cpi (t)

v (t)e

ei (t)

t

t

t

Figure 6.8: Mismatch of Charge Pump Currents

Qup + Qdown = 0

⇒(i1

−∆ie) (T ABL + ∆t e)

−i1T ABL = 0

⇒ ∆ieT ABL = ∆t e(i1 −∆ie)

⇒ ∆t e = T ABL∆ie

i1 −∆ie

≈ T ABL∆ie

i1(6.5.11)

The weight of the error pulses is calculated separately for the two time steps ∆t e and T ABL (fig.

6.8): First, the error current is ie = iup = i1 −∆ie for a period of ∆t e, then ie = iup + idn = −∆ie

for a period of T ABL. The error voltage is equal to the error current integrated in C 1, which is

simply a voltage ramp. The resulting pulse has the shape of a triangle with a steep rise. The

weight, i.e. the area of the pulse, is calculated graphically:

w =∆t e

2

∆ieT ABL

C 1+

T ABL

2

∆ieT ABL

C 1

=T 2 ABL∆ie

2C 1

1 +

∆ie

i1 −∆ie

(6.5.12)

(6.5.12) shows the strong influence of T ABL on the spurious performance.

The spurious level at the output of the VCO is easily calculated from the pulse weight using

(6.5.6), i.e. sk = wK vco/k .

EXAMPLE 8: Spurious sidebands due to charge-pump mismatch




6.6 The Magical Mystery Spur: Dividing Spurious Sidebands 95

t ABL = 4nS, i1 = 4mA, ∆ie = 0.5mA, C 1 = 1nF, K VCO = 40MHz/V

⇒∆t

e= 0.57ns, w = 4.6pVs

⇒s1 = 1.8 ·10−4 ≡ -75dBc

s2 = 9.1 ·10−5 ≡ -81dBc

. . .

6.6 The Magical Mystery Spur: Dividing Spurious Side-

bands

One of the mysteries in the design of frequency synthesizers is the relationship between spu-

rious sidebands and frequency dividers: Measurements show that a frequency divider by N

divides the carrier frequency by N (obviously ...), reduces the level of spurious sidebands by

20 log N dB (less obvious) and leaves their distance from the carrier unchanged (magic!).

Why is that so? Some books try to explain these effects in the frequency domain, but this

approach is somewhat dubious because frequency division is non-time invariant and highly

nonlinear. A frequency divider always includes clipping / limiting (digital circuits!), there-

fore, we only need to deal with phase / frequency modulation. If the input signal to the divider

is amplitude modulated, this modulation is converted to phase modulation in the first limiting

stage.

fc

1/f m2 1/f m1

S (f)FM

m1+f+fm2

+fm2m1+f

0f + f∆

0 1f + f∆

0f + f∆3

0f + f∆2

f0

f0

f0

f (t)FM

1/f m1+2f m1m1+f

ft

t fa)

b)

Figure 6.9: Instant Frequency and Spectra of Divided, FM Modulated Signals

It is important to distinguish the different terms used in frequency modulation:

• Carrier Frequency: the average frequency f 0 of zero transitions of s(t )

• Modulation Frequency: the frequency f m of the modulating signal which creates the

spurious sidebands. As shown in the sections above, modulating a carrier with fre-

quency f 0 with a weak sinusoidal signal with frequency f m creates spurious sidebands

at f 0 ± f m.





• Frequency Deviation: the instantaneous frequency deviation ∆ f of the carrier created

by the modulation signal.

• Modulation Index: the quotient of modulation frequency and frequency deviation

µ = ∆ f / f m. The modulation index is influenced by the amplitude m of the modulation

signal or the sensitivity of the modulator (usually the VCO). However, it does not

depend on the modulation frequency: increasing f m raises ∆ f by the same amount.

• Deviation Ratio: the modulation index for the highest modulation frequency

• Bandwidth: nearly all of the power of a frequency modulated signal lies in a band-

width of f 0, B. As an empirical rule of the thumb (Carson’s Rule), the bandwidth is

f 0, B ≈ 2(δ f + f m) = (µ + 1) f m.

EXAMPLE 9: Applications for Frequency Modulation

FM-Radio (UKW) uses pre-emphasis to improve the signal-to-noise ratio by

boosting high frequencies before modulation6. This is done with a simple RC-

highpass (τ = 70µ s, f B = 2.3kHz):

f 0 = 100 MHz, f m = 20 . . .15, 000 Hz, at 20kHz the modulation index is lim-

ited to a maximum of 5 to restrain the bandwidth: µ max = 5(15kHz) ⇒ f 0, B ≈2(5+ 1) ·15kHz = 180kHz. Channel spacing in UKW - Radio is 200 kHz which

explains the choice of µ max.

GSM Mobile Phones:

6Remember: FM attenuates high frequencies




Chapter 7

Other Sources of Spurious

Sidebands

Inside every large problem is a small

problem struggling to get out.

Hoare’s Law of Large Problems

Overview: This chapter shows different causes for the generation of spurious sidebands and their effects. Knowing the mechanism of sideband gener-

ation helps to identify their sources.

Often the PLL designer is confronted with the problem of nasty spurious sidebands without

knowing their source(s). The way amplitude and frequency of these sidebands change with

the PLL frequency can help to track down their cause and eliminate them. In the following

chapter, some possible causes for spurious sideband generation and their characteristics are

shown. A first rough separation can be made by the way the spurs move in the spectrum when

the PLL frequency is changed. The names α -, β - and γ -spurs have been coined for three very

distinctive kinds of sidebands, allowing a quick classification:

Classification of spurious sidebands

• α -Spur: A sideband whose offset depends on the output frequency f out . It has one

fixed component at n f sys (fig. 7.1).

• β -Spur: A sideband whose offset depends on the VCO frequency f VCO . There is no

fixed component at the divided output (fig. 7.4).

• γ -Spur: A sideband with a constant offset from the carrier, it moves with the carrier

and has no fixed component (fig. 7.6).

Some general points:

97



98 Other Sources of Spurious Sidebands

• In systems where the VCO-Frequency is also the output frequency, α - and β - spurs

are identical.

• Most sidebands come in symmetric pairs around the carrier: FM / PM modulation is

symmetric around the carrier anyway1, additive disturbances (AM) are converted to

PM / FM in every limiting or otherwise non-linear stage.

• Strong (> −30 dBc) spurious sidebands also create higher order sidebands with lower

amplitudes at k times the offset due to non-linearities of PM / FM.

• The source of disturbances can be tracked by varying supply voltages, reference cur-

rents etc. If e.g. the CP is the source, sideband amplitudes rise with CP current, if some

logic block creates the noise, increasing its supply voltage will do the same.

7.1 Spurious Sidebands Depending on the Output Frequency(α -Spurs)

When the RF output frequency f out interferes with the reference frequency or the system

frequency or their harmonics, a characteristic sort of spurious sidebands is generated, defined

as α - spurs (fig. 7.1).

fout2 ∆

fout

∆fs

∆fs

f∆ out

∆ s outf = f − n f sys

910.2 MHz910

3 5 * 2 6 M H z

( f i x e d )

Figure 7.1: Characteristic behaviour of alpha spurs

Spurious sidebands due to RF output interfering with the system frequency

f s,in j = f out ± ( f out − n f sys) ; n such that f out − n f sys

< f sys/2 (7.1.1)

= n f sys and 2 f out − n f sys

Due to the formation mechanism, the fixed spur is unmodulated while the mirror spur has

twice the bandwidth of the output signal f out .

7.1.1 RF Leakage Into the System Frequency Path

In the last chapter, examples have been shown for LF signals disturbing the loop filter volt-

age and thus creating spurious sidebands. Suprisingly, also frequencies far above the loop

bandwidth and the system frequency can disturb the PLL output. The mechanism here is

downsampling, the interfering signal mixes with multiples of the system frequency and folds

signal components down into the “baseband” (0 ≤ f < f sys/2). In general, VCO and output

frequency will be no integer multiples of the system frequency because they are derived from

a fraction of the system frequency (due to reference divider, fractional-N principle or FM

modulation in the mixer stage). The latter two can be especially troublesome, because the

output frequency can be so close to a system frequency harmonic that the resulting mixing1Except for complex modulation schemes.




7.1 Spurious Sidebands Depending on the Output Frequency (α -Spurs) 99

product falls within the loop bandwidth. And both VCO and RF output driver produce strong

signals that can be “heard” all over the chip (fig. 7.2).

fvco

fout

fref

fref

fsys

1

N

F(s)1

D+

PD

CP

1

Rfsys

ref vcof = f / N

f outα( −spur)

f VCOβ( −spur)

Filter

N−Divider


DividerReference

Loop

DividerVCOLO−

Figure 7.2: Downsampling of RF components into the system frequency path

The mechanism is described in detail in the appendix (C.1). In a nutshell, the spectrum of the

“intruding” signal S RF ( f ) is mixed down with a suitable harmonic of the system frequency

n f sys. n must be chosen such that the resulting frequency difference | f RF − n f sys| < f sys/2.

The most likely place for this to happen is the system frequency path. Here, the edges are

sharp enough and the frequency is high enough to produce harmonics that reach well intothe RF region. There are two sensitive spots along this path where analog and digital worlds

meet: the input of the system frequency amplifier where an external sinusoidal signal is con-

verted into the fast-switching system clock. The other one is the charge pump where a DC

reference current is scaled up and chopped with the system/reference frequency. If an RF

signal couples onto the sinusoidal input signal, the charge pump reference current or on the

supplies of these blocks, it can be easily converted down to the baseband - see example 10.

The resulting spectrum shows one spur at n f sys and one mirrored around the carrier with an

identical offset. Shifting the carrier therefore results in one stationary spur and one moving

with twice the frequency shift of the carrier (fig. 7.1).

Additionally, there may also be spurs at multiples of the offset due to the non-linearities of frequency modulation.

The sharper the edges in the system frequency path are, the higher will be the amplitude of

the harmonics. This means, very high frequency components can be downsampled into the

base band. On the other hand, the circuit becomes much more robust against low frequency

injection and inherent noise because the region of high gain / high sensitivity is passed in a

very short time. This effect is usually dominant, therefore the system / reference path is con-

structed with high speed gates. However, the system can be made robust against RF injection

by low-pass filtering the sinusoidal system signal and the bias lines.

Once the high frequency signal has been folded into the baseband, it behaves like the low

frequency injection described in section 7.3.4. If e.g. a 962.2 MHz signal leaks into the sys-

tem path with a frequency of 26 MHz, it will mix with the 37th harmonic of the 26 MHz

signal (962 MHz), producing a component at 200 kHz. This low frequency component will

modulate the system frequency and the PLL output signal like described above.





∆f = 200kHzs

Ssample

5226 78 MHz

Sout∆f

s

910.2 MHz910

( 3 5 * 2 6 M H z )

SVCO

∆fs

∆fs

∆fs

∆fs

(w/ spurs)

3640.8 MHz

Sout

∆fs

∆fs

∆fs

∆fs

910.2 MHz910

(w/ spurs)

35*26MHz

(fixed)

:4

SPD

∆fs

∆fs

∆fs

0.40.2 26 MHz

f

SLF

∆fs

0.40.2 26 MHz

f

Loop FilterCharacteristic

sample

(undisturbed)

Figure 7.3: Downsampling of TX output (910.2 MHz) by the system frequency (26MHz)

EXAMPLE 10: Spurs caused by downsampling

An RF signal of 910.01 MHz couples onto the biasing path of a charge pump,creating an RF current with an amplitude of 1µ A at the charge pump output. The

DC current of the charge pump is 1 mA, it switches with a reference frequency of

26 MHz and a duty cycle of 0.3. The 35th harmonic of the reference frequency

is at 910 MHz, mixing the RF signal down to 10 kHz. There is usually no loop

filter attenuation at that frequency and the signal will directly modulate the VCO.

At the RF output, this gives two spurs, one at 910.0 MHz and one at 910.02 MHz

with amplitudes of ck = 1µ A ·α sinc(35πα ) = 0.03µ A. Assuming a load resis-

tor of 1k Ω and a VCO steepness of 60 MHz/V, it will create sidebands with an

amplitude of

sk = 0.03µ A ·1k Ω · K VCO /(2 ·10kHz) = 0.09 = −21 dBc (!!)

α -spurs: leakage of RF output signal into system / reference path

Mechanism: The RF output frequency is downsampled by the system / refer-

ence frequency.

Frequency Offset: Equal to the difference of RF frequency and nearest harmβ -spurs: system / reference frequency harmonicsonic of reference

/ system frequency

Amplitude: Attenuated with loop filter characteristic

PLL Mode: Fractional and integer mode.




7.2 Spurious Sidebands Depending on the VCO Frequency (β -Spurs) 101

Note: When the carrier is modulated, s(t ) = Acos(ω 0t +ω mod (t )t ), the down-converted sig-

nal has the same modulation: s LF

(t ) = Acos(∆ω

s(t ) +ω

mod (t )t ). When this signal is multi-

plied with the modulated carrier in the PLL, you will get one unmodulated sideband and one

sideband with twice the modulation depth:

sout (t ) = Acos(ω 0t +ω mod (t )t ) modulated carrier

·

1 + A cos(∆ω st +ω mod (t )t )

s LF : downconverted signal

= Acos(ω 0t +ω mod (t )t )

+ AA

2

cos(ω 0t −∆ω st )

unmodulated sideband

+cos(ω 0t + ∆ω st + 2ω mod (t )t )

modulated sideband (2x)

(7.1.2)

Leakage of System Frequency Into the RF path

α -Spurs can also be generated the other way round: the system frequency or its harmonics

may leak into the RF path (e.g. modulating the TX buffer or the modulator). The resulting

sideband picture is the same (?):

7.2 Spurious Sidebands Depending on the VCO Frequency

(β -Spurs)

When the VCO frequency f VCO interferes with the reference / system frequency or their

harmonics, a characteristic sort of spurious sidebands is generated, coined β - spurs (fig.

7.4).

fout

fVCO

∆fs

∆fs

∆fs

∆fs

fout∆

fout5∆fout−3∆

:4

∆ s VCOf = f − n fsys

fout4∆

fout8∆

909.85 910.05 MHz3640 3640.2 MHz

( f i x e d )

1 4 0 * 2 6 M H z

Figure 7.4: Characteristic behaviour of beta spurs for D = 4

Frequency of β -Spurs

f s,in j, LO =f VCO

D± ( f VCO − n f sys) ; n such that

f VCO − n f sys

< f sys/2

=D + 1

Df VCO − n f sys and n f sys − D −1

Df VCO (7.2.1)

7.2.1 VCO / LO Leakage Into the System / Reference Frequency Path

Similiar to the mechanism described in the last section, the VCO / LO signal instead of the

divided signal f out can leak into the system / reference frequency path (fig. 7.2). The resulting





spuriuos spectrum looks more complicated (7.2). For e.g. D = 4, one spur moves with 5 times

the frequency shift ∆ f out

= f VCO

/ D of the output frequency, the other one with three times

∆ f out in the opposite direction (fig. 7.4). These spurs enter the PLL via the reference path,

their amplitude is attenuated by the loop filter.

7.2.2 System Frequency Harmonics’ Spurious

As the system / reference frequency directly influences in-band phase noise performance, it

is driven with a very high slew rate to avoid phase noise degradation. This means, the on-chip

signal contains a lot of harmonics that can interact with RF signals on chip.

A harmonic near the VCO frequency (the carrier) is amplified by the VCO resonant char-

acteristic by 6 dB/oct (20 dB/dec) when it gets close to the carrier. In a PLL, the loop will

attenuate frequencies near the carrier with 20 dB/dec for a type I PLL (non-integrating loop

filter) and with 40 dB/dec for a type II PLL (integrating loop filter). As these two effects

work against each other, signals close to the VCO frequency will have a constant gain within

the loop bandwidth for a non-integrating loop filter. With an integrating loop filter, these

signals will be attenuated with 6 dB/oct the closer they get to the carrier. The VCO itself and

the VCO buffer act as limiters which convert the additive disturbances into PM modulation at

both sides of the carrier. Therefore, such an additive signal always creates its “mirror partner”

at the other side of the carrier.

f VCO

f = f / NVCOref

fref

fref

f sysf sys

1

N

+PD

CP

1

RF(s)

.n fsys

1

D

fout

Filter

N−Divider


DividerReference

Loop

VCOLO−DividerLO−Buffer

Figure 7.5: Spurious generation due to system frequency harmonics

This effect is only noticable when the disturbing signal (or one of its harmonics) is very close

to the oscillating frequency. Harmonic components of the system frequency near the VCO

oscillation frequency are a common example for this case of disturbance.

(7.2) shows that at the VCO frequency there is one spur with a fixed frequency of n f sys.

However, after the division by D, only the offset to the carrier remains unchanged, not the

frequency itself. Therefore, both spurs move around in the spectrum (fig. 7.4).

EXAMPLE 11: Spurious caused by harmonics of the system frequency

The 37th harmonic of the 26 MHz reference frequency is at 962.0 MHz. A VCO

oscillating at 962.2 MHz can amplify this harmonic and produce a spurious side-

band at 962.0 MHz. The mirror spurious is created with the same amplitude and




7.2 Spurious Sidebands Depending on the VCO Frequency (β -Spurs) 103

opposite frequency offset at 962.4 MHz.

If the VCO is followed by a divider stage by 4, the VCO needs to be tuned

to 4 · 962.2 MHz = 3848.8 MHz to produce the target frequency. The nearest

harmonic of the system frequency is 148 · 26 MHz = 3848.0 MHz. When this

harmonic is amplified by the VCO, sidebands will be produced at an offset of

±800 kHz, i.e. at 3848.0 MHz and at 3849.6 MHz. The division by 4 leaves

the spurious offset unchanged, so you’ll end up with spurious sidebands at 962.2

MHz ±800 kHz = 959.4 / 963.0 MHz. Due to the division, none of the resulting

sidebands at the output is a harmonic of the system frequency which makes it

difficult to track down the source of the spurs.

Note: This mixing effect also takes place in every other non-linear circuit blocks like the

VCO buffer or divider stages. However, as these blocks have no resonant gain, the resulting

modulation will be small under normal circumstances. There will be no frequency depen-

dency of the spurious for disturbed blocks outside the loop.

β -spurs: system / reference frequency harmonics

Mechanism: Harmonics of the reference / system frequency are injected into

the VCO.

Frequency Offset: Equal to the difference of VCO frequency and nearest harmonic

of the disturbing signal.

Amplitude: Within loop BW: Depends on loop filter type, is amplified byVCO resonance (20 dB /dec.) but attenuated by the loop near

the carrier (20 / 40 dB/dec). Outside loop BW: attenuation by 20

dB/dec

PLL Mode: Fractional and integer mode.

7.2.3 Fractional-N Spurs

Due to their operation principle, fractional-N frequencysynthesizer generate lots of frequency

components that are not harmonically related to the reference frequency: A fractional-N PLL

can increase the output frequency in fractional steps of the reference frequency (hence itsname ...). This fractional channel resolution is achieved by averaging the division ratio over

MOD reference cycles. The resulting VCO frequency is ( N + F / MOD) f re f with a minimum

step size of f re f / MOD. Therefore, spurious sidebands may pop up at strange, unexpected

frequencies. Due to the fine frequency granularity, the VCO can be set to oscillate very close

to harmonics of the reference or system frequency, which may lead to the different spurious

sidebands described above.

Although chapter 8 deals with fractional spurs in detail, here’s a quick look at their symptoms

- we will see that they behave very similiar to the other β -spurs described above.

Mechanism: Systematic Fractional Sidebands

The cyclical variation of division ratios creates a cyclical systematic phase error at the phase

detector. This results in several systematic spurs with a minimum spacing of f re f / MOD

(described in detail in chapter 8). More and more of these spurs will disapear in the phase





noise floor for synthesizers with a higher modulus because the power per spurious line is

reduced. However, there is a strong periodic component at an offset from the carrier of

± f frac = ±F / MOD · f re f . This effect is especially strong for short modulus sequences and

first order fractional modulators, it can be simulated / calculated in advance. Due to non-

idealities (see below) you will probably see these spurs also with higher order fractional

modulators.

Mechanism: Modulus Control Disturbances

Even with higher order fractional-N modulators, the bit lines from the modulator controlling

the multi-modulus divider have a spectral content like the first order fractional-N modula-

tor. Especially when the modulator is off-chip, the single bit lines can create switching noise

which e.g. interacts with the phase detector. Clocking the modulator and toggling its output

at times when the PD is insensitive can eliminate this problem (staggered timing).

Mechanism: Non-Linearities in Higher Order ModulatorsNon-linearities in the loop can be troublesome with higher order fractional modulators, they

create spurious sidebands with an offset of f frac. This is especially critical with type II PLLs

- here the PD / CP operate with very short pulses and the linearity of charge vs. phase error

is mediocre. In order to improve linearity, often a small offset current is injected into the

loop filter which increases the minimum on-time of the CP (also good for lab testing). Type

I PLLs are much more linear in this respect due to their long turn-on time.

In spite of the different mechanisms, the effect of fractional spurs are all similiar:

β -spurs: fractional-N synthesizer

Frequency Offset: Equal to the fractional part f frac, therefore, one sideband always

falls on the integer frequency (VCO domain), (weaker) side-

bands at other frequency offset can also be created.

Amplitude: Is attenuated by loop filter characteristic / loop gain, therefore it

depends on the frequency offset. For certain fractional values,

the spur is stronger (e.g. min. / max. fractional part, half integer

- see chapter 8).

PLL Mode: Only in fractional mode.

7.3 Spurious Sidebands Tracking the Carrier (γ -Spurs)

Spurious sidebands that keep their offset to the carrier when the carrier frequency is changed,

are called γ - spurs (fig. 7.6).

fout

fVCO

/

∆ sf = fsys

∆ fs∆ fs

∆ f∆ f

∆ f

Figure 7.6: Characteristic behaviour of Gamma-spurs




7.3 Spurious Sidebands Tracking the Carrier (γ -Spurs) 105

7.3.1 Reference Frequency Modulating the VCO

fVCO

fout

fref

fref

fsys

f = f / NVCOref

+PD

CP

1

R

F(s)

1

N

1

D

fref

fref


FilterLoop

N−Divider

ReferenceDivider

LO−DividerVCO

Figure 7.7: Spurious generation due to reference frequency leakage

Spurs created by reference frequency have been covered in great detail in the last chapter:

the reference frequency f re f is the update frequency of the the phase detector which is gener-

ated by the reference divider. Here, the system frequency f sys is divided by R: f re f = f sys/ R.

Fractional-N synthesizers have a high reference frequency to gain noise performance, they

often use the system frequency as reference frequency: f re f = f sys, R = 1.

The reference frequency is present at the output of R and N divider, at the phase detector and

the charge pump2. This frequency mainly disturbs the VCO via its tuning input or supply

voltage (see fig. 7.7).

Especially the charge pump produces pulses with high energy, emitting disturbances at its

supplies and output. These disturbances may cause ripple on the VCO tuning input (improper

loop filter design, improper current return path for charge pump current, capacitive coupling

across the loop filter) or its supplies (improper supply decoupling). In all these cases, the

reference frequency directly modulates the VCO frequency, generating spurious sidebands at

an fixed offset of ±k f re f from the carrier at the VCO output (see fig. 7.9). The higher spurious

frequencies (k > 1) can be produced by the inherent non-linearity of frequency modulation

or by harmonics of the disturbance itself (or both).

Another possible modulation point is the VCO buffer and distribution (see 7.2.2). In any case,

the sidebands move with the VCO frequency, keeping their offsets (fig. 7.6). This is also true

with an LO-divider D behind the VCO - the frequency offset of the spurious sidebands is still

∆ f s = ±k f re f , however, their amplitude is reduced by 20log D.

Spurious sidebands due to reference frequency leakage

f s,re f =f VCO

D± k f re f ; k = 1,2, . . . (7.3.1)

The amplitude of these sidebands drops with at least 20 dB/dec (6 dB/oct) modulation fre-

quency due to the integrating behaviour of the VCO. For example, the 3rd harmonic of a

VCO disturbance is attenuated by 3 · 6 = 18dB more than the fundamental. The reference

frequency is always above the loop bandwidth, but it depends on the coupling path whether

the loop characteristic has an influence on these spurious.2Exception: An EXOR phase detector produces twice the reference frequency at its output (see section 3.2.2).





7.3.2 System Frequency Modulating the VCO

fVCO

f = f / NVCOref

fref

fref

1

N

F(s)+PD

CP

1

R1

D

fout

fsys fsys

Filter

N−Divider


DividerReference

Loop VCO

LO−Buffer

LO−Divider

Figure 7.8: Spurious generation due to system frequency leakage

Disturbances related to the system frequency f sys behave in a similiar way as f re f distur-

bances: The system frequency is applied to the chip via an external crystal or a crystal oscil-

lator module and converted to a logic signal on chip. This system frequency can leak into the

output path by directly modulating the VCO via its tuning input or supplies (improper shield-

ing or supply decoupling) - see fig. 7.8. Exactly as in the f re f case, the VCO is frequency

modulated by a (comparatively) low frequency signal, producing sidebands with an offset of ±k f sys around the carrier (fig. 7.9):

Spurious sidebands due to system frequency leakage

f s,sys =f VCO

D± k f sys; k = 1,2, . . . (7.3.2)

SVCO

3984 MHz

(clean)

Sdist

∆fs

∆fs

∆fs

5226 78 MHz

f

x

SVCO

∆fs

∆fs

∆fs

∆fs

3984 MHz

(w/ spurs)

Sout

∆fs

∆fs

∆fs

∆fs

1992 MHz

:2

∆f = 26MHzs

Figure 7.9: Reference / system frequency modulating the VCO




7.3 Spurious Sidebands Tracking the Carrier (γ -Spurs) 107

γ -spurs: VCO modulation by system / reference frequency

Mechanism: Direct frequency modulation of VCO frequency via tuning input

or supplies.

Frequency Offset: Independent of carrier frequency, alway with an offset of ±k f re f

resp. ±k f sys.

Amplitude: Independent of carrier frequency, amplitude is attenuated with

1/ f mod due to integrating VCO behaviour.

PLL Mode: Both fractional and integer mode.

7.3.3 Reference / System Frequency Modulating the LO Distribution

Other possible modulation points for f re f or f sys are the VCO buffer and distribution, also

called LO (Local Oscillator) buffering and the LO divider (fig. 7.10): especially when the

buffering / divider are realized with single ended circuits to save power, f re f or f sys may cause

phase modulation of the (divided) LO signal. The difference to frequency modulation at the

VCO itself is that this modulation takes place outside the loop - the spurious amplitude is not

attenuated with increasing modulation frequency, which means you may also see spurious

component far away from the carrier. Reference and system frequency and their harmonics

can create a “picket fence” of spurs when the decoupling is not done properly. It is hard to

distuingish whether the LO buffering or LO divider is affected: in both cases (7.3.1) resp.

(7.3.2) describe the spur behaviour.

fout

fref

fref

fsys

f = f / NVCOref

+PD

CP

1

R

F(s)

1

N

1

D

fVCO

fref

fref , fsys

fref


FilterLoop

VCO

N−Divider

ReferenceDivider

LO−Divider

Figure 7.10: Spurious generation due to modulation of LO buffer and divider





γ -spurs: PM modulation of LO buffer or divider

Mechanism: Phase modulation of LO buffers via supplies or parasitic cou-

pling.

Frequency Offset: Independent of carrier frequency, always with an offset of

±k f re f resp. ±k f sys.

Amplitude: Independent of carrier and modulation frequency. Other influ-

ences depend on source of disturbance - if the CP is the source,

spurious amplitudes rise with CP current, if some logic block

creates the noise, increasing its supply voltage will do the same.

PLL Mode: Both fractional and integer mode.

7.3.4 LF Injection into the System Frequency Path

The system frequency path is also a hot spot for disturbances to enter the system: phase

modulation of the system frequency with low frequencies (i.e. not much higher than the

loop bandwidth) directly modulates the PLL output! Again, improper supply decoupling or

capacitive coupling onto the signal path are the most likely causes for this. Divider stages at

the output of the reference or N-divider can also be dangerous: divider stages often have a

significant backlash from the output to the input, creating a phase modulation with half the

reference frequency. In contrast to that, the reference frequency itself in an Integer-N PLL

has no impact on the system frequency path: If it modulates the input of the system frequencyamplifier, spurious on the system frequency will be created at f sys ± f re f . Behind the reference

divider, they will still have the same offset, i.e. be at f re f ± f re f = 0 and 2 f re f . The DC

component has no effect, the other one is just a harmonic of the reference frequency and is

far outside the loop bandwidth. A well designed loop filter should get rid of this component

(if not, you’ll see reference spurious anyway: see 7.3.1). Fractional-N synthesizers operate

with frequency components that may be well within the loop bandwidth, that’s why they have

plenty more options for trouble.

fvco

fout

fref

fsys

1

N

F(s) 1D

+PD

CP

1

Rfsys

ref vcof = f / N

2

1

f / 2ref

reff / 2

fref

Filter

N−Divider

LoopCharge PumpVCO LO−Divider

Phase Detector /

ReferenceDivider

Figure 7.11: LF injection into the system frequency path

A disturbance with frequency f dis directly translates into spurious sidebands at the output:




7.4 Intermodulation Effects 109

Spurious sidebands due to low frequency injection into the system frequency

f s,in j =f VCO

D± k f dis; k = 1,2, . . . (7.3.3)

Harmonics of the disturbance signal will also appear at the PLL output (k > 1). The same is

true if the disturbance is very strongand non-linearitiesof the PM start showing. Disturbances

within the loop bandwidth are transferred with a flat frequency characteristic, outside they are

attenuated with the loop characteristic.

γ -spurs: PM modulation of reference / system frequency

Mechanism: Phase modulation of reference / system path via supplies or par-

asitic coupling by a LF disturbance.

Frequency Offset: Independent of carrier frequency, alway with an offset of ±k f dis .

Amplitude: Independent of carrier frequency, amplitude is constant as long

as f dis is within the loop bandwidth.

PLL Mode: Fractional mode or other system parts with sub-reference fre-

quencies.

7.4 Intermodulation Effects

A signal processing stage with a non-linear transfer characteristic (i.e. any real circuit :-) )produces intermodulation distortions. This means, when a signal with two or more frequency

components passes through that stage, it will produce harmonics of the input frequencies and

other new frequency components. In the appendix C.4, the output signal has been calculated

for a signal containing two frequencies which is passed through a stage with linear gain and

square and cubic distortion terms.

Even in this simple example, the output signal has a DC offset and contains harmonic com-

ponents (distortion) at 2ω 1 and 2ω 2, 3ω 1 and 3ω 2. It also contains mixed components (inter-

modulation) at ω 1 ±ω 2, 2ω 1 ±ω 2 and ω 1 ±2ω 2. Single ended stages usually show even and

odd order distortions while differential stages have a strong suppression of even order dis-

tortions (a2 in this example). Therefore, differential stages have much less DC offset due to

intermodulation and generate less components at twice the input frequencies (2ω 1 and 2ω 2)

and also less first order intermodulation (ω 1 ±ω 2). In real systems, the cofficients ak may

also be negative.




Chapter 8

Spurious of Fractional-N PLLs

Better to light a candle than to curse

the darkness.

Chinese Proverb

8.1 Spurious Sidebands of First Order Fractional-N PLLs

The periodic switching of the division ratio is triggered by the phase accumulator , an accu-mulator with modulus F mod that adds up N F every reference cycle. Each time an overflow

occurs, the division ratio is switched from ÷ N to ÷( N + 1) for one reference cycle.

Ref. Cycle #1 #2 #3 #4 #5 #6 . . . Average

Modulus Cycle #1 #2

← T mod → ← T mod → N F = 1: Accu 5 → 0 1 2 3 4 5 → 0 . . .

Div. N + 1 N N N N N + 1 . . . N + 15

∆φ 02π

t =0

55

→ 0 15

25

35

45

55

→ 0 . . . 25

∆φ 02π t =∞

35

→ −25

− 15

0 15

25

35

→ − 25

. . . 0

N F = 3: Accu 5 → 0 3 6 → 1 4 7 → 2 5 → 0 . . .Div. Ratio N + 1 N N + 1 N N + 1 N + 1 . . . N + 3

5∆φ 02π

t =0

55

→ 0 35

65

→ 15

45

75

→ 25

55

→ 0 . . . 25

∆φ 02π

t =∞

35

→ −25

15

45

→ − 15

25

55

→ 0 35

→ − 25

. . . 0

Table 8.1: Operation of Phase Accumulator (F mod = 5)

Let’s assume the PLL is locked at the fractional frequency f 0 = N I .F · f re f . Fig. 4.2 shows

an example for a modulus of F mod = 3, N I = 10 and N F = 1, giving an average division

ratio of N = N I .F = 10 1/3. During the ÷ N parts of the modulus cycle the divided VCO

signal arrives a little too early at the phase detector because the VCO is faster than the virtual

signal f 0,int = N I f re f (there is no such signal in the PLL) by ∆ f frac (see 4.0.2). This constant

frequency offset corresponds to a phase deviation of

111



112 Spurious of Fractional-N PLLs

∆φ 0(t ) = 2π ∆ f 0, fract =2π N F

F mod T re f t or ∆φ 0(kT re f ) =

2π kN F

F mod

On average, the deviation of the VCO phase from N I f re f exceeds 2π every F mod / N F cycles.

Table 4.1 shows that the phase accumulator overflows with the same frequency, triggering

a ÷( N + 1) cycle each time. This is equivalent to swallowing one VCO cycle or removing

an excess phase of 2π . This means, the phase accumulator tracks the phase deviation of the

VCO and removes it when it exceeds 2π .

The phase deviation at the VCO apears ÷ N at the phase detector as a phase error ∆φ e(t ) :

∆φ e(t ) =∆φ 0(t )

N =

2π N F

NF mod T re f

t for 0 ≤ t ≤ T mod (8.1.1)

The phase error is only sampled at multiples of T re f :

∆φ e(kT re f ) =2π kN F

NF mod

The phase error at the phase detector corresponds to a timing error of

∆t e(kT re f ) =∆φ e(kT re f )

2π · T re f =

kN F

F mod N · T re f ≈ kN F

F mod

· T 0 (8.1.2)

This periodic timing error at the phase detector produces unwanted error pulses at the charge

pump output.

For simplicity reasons, we regard the case N F = 1, which is not only most easy to calculate but

also gives the worst spurious performance: The phase error at the PD ∆φ e(t ) rises continously

during the÷ N period (the VCO clock is early) and is reduced by 2π / N when one VCO period

is swallowed during the ÷( N + 1) period. This means ∆φ e(t ) has a sawtooth characteristic

with a maximum of 2π / N at t = T mod = F mod T re f (see 8.1.1):

∆φ pd (t ) =2π

N saw

t

T mod

(8.1.3)

where saw(t ) is the periodic sawtooth function with a period and an amplitude of 1. In a

locked loop, the DC component is eliminated, therefore the phase error changes from −π / N

to +π / N rather than from 0 to 2π / N within F mod cycles. The timing error of

∆t pd =∆φ pd (t )

2π · T 0 (8.1.4)

at the phase detector is sampled with the reference clock period T re f , i.e. F mod times per T mod .

Therefore, ∆t PD is stepped through

∆t pd = −1

2T 0,

−1

2+

1

F mod

T 0,

−1

2+

2

F mod

T 0, ... ,

1

2T 0 (8.1.5)

Mathematical Description

When the PLL is locked, sometimes the divided VCO phase will be late and sometimes early

compared to the reference clock. The resulting output of the phase detector ve(t ) will be a




8.1 Spurious Sidebands of First Order Fractional-N PLLs 113

pulse train with varying pulse width T w,k , delay ∆T k and amplitude ak (for an up/down PD,

otherwise ak

will be constant). The sequence repeats with a period of T mod

= F mod

T re f

:

ve(t ) =

F mod −1

∑k =0

ak · rect

t −∆T k

T w,k

train of rect pulses

∗

n=∞

∑n=−∞

δ (t − nT mod ) repeat every T mod

(8.1.6)

The Fourier transformation of (8.1.6) is performed using the following transformations:

Rect −Pulse : rect(t /T w) −• T w sinc(π f T w)

Delay : s (t −∆T ) −• S ( f ) · exp(− j2π f ∆T )

Periodicity : s(t ) ∗ n=∞∑n=−∞

δ (t − T mod ) −• S( f ) · 1

T mod

n=∞∑n=−∞

δ ( f − n/T mod )

The result is given in (8.1.7) where the rect pulses in the time domain translate to sinc pulses

in the frequency domain with a complex factor corresponding to their delay. As this train

of rect pulses has a periodicity of T mod , the spectrum consists of lines every 1/T mod . The

amplitude of the spectral lines is given by the superposition of sinc terms which has to be

calculated at f = n/T mod :

V e( f ) =F mod −1

∑k =0

ak T w,k sinc

π f T w,k

·exp(− j2π f ∆T k )

superposition of complex weighted sinc pulses

· 1

T mod

n=∞

∑n=−∞

δ

f − n

T mod

filter at f =n/T mod

=

n=∞

∑n=−∞

F mod −1

∑k =0

ak T w,k

T mod

sinc

π

nT w,k

T mod

· exp

− j2π

n∆T k

T mod

at f = n

T mod

0 else

(8.1.7)

The next step is to calculate the delays ∆T k and pulse widths T w,k and to multiply the spectrum

V e( f ) at the CP / PD with the loop filter response.

The level of the VCO output spurious sidebands can be calculated using equation 6.3.2 with f 1 = f mod :

EXAMPLE 12: Spurious sidebands of first order fractional-N synthesizer

T 0 = 1ns, N = 1000, K vco = 50MHz/V, F mod = 5, I pd = 4mA, C 1 = 1nF, f mod =200kHz




114 Spurious of Fractional-N PLLs




Part III

Phase Noise and Jitter

115



Chapter 9

Phase Noise and Jitter

Time is just an illusion.

Albert Einstein

Overview: This chapter gives an introduction into the concepts of phase

noise and jitter, and how to translate specifications between the two domains.

9.1 Jitter

”Jitter is defined as that short-term noncumulative variations of the signifi-

cant instants of a digital signal from their ideal positions in time” (SONET spec-

ifications ITU-T-G.701).

For most engineers, the concept of jitter is understood more easily than the concept of phase

noise - the first one describes undesired fluctuation of signal transition times, the second one

deviations from the line spectrum of an ideal oscillator in the frequency domain. Both con-

cepts are used to describe regular clock or oscillator signal with only slight non-idealities

Phase noise is prevalent when spectral purity is a concern as in wireless communication sys-

tems, jitter is the concept of choice for applications dealing with timing accuracy as in clock

and data recovery.

Although signal theory gives methods to translate jitter into phase noise and vice versa, this is

not so easy in praxis: It is necessary to know the full spectral characteristic (including phase

information!) resp. autocorrelation data to do so.

9.1.1 Jitter of Driven Systems (PM Jitter)

This sort of jitter can be generated in every digital gate - the delay of a digital stage is deter-

mined by the slew rate of the input signal and by the switching threshold of the digital input.

When the switching threshold varies due to e.g. thermal noise or disturbances of the supply

voltage, the delay is varied slightly, introducing jitter. This kind of jitter can be minimized by

stable supply voltages and fast edges of the digital signals although the latter may cause high

frequency disturbances. It is also called PM (phase modulation) jitter because the frequency

at the output is identical to the input frequency, this kind of jitter is synchronous. Its mean

117



118 Phase Noise and Jitter

value is zero and its variance is bounded. In the following, it is assumed that the disturbing

signal has a white spectrum and a Gaussian distribution and that its amplitude is small enough

that the circuit responds in a linear way to the noise. In this case, the phase variation of sn(t )will also be white. In a PLL, all blocks except the reference oscillator and the VCO exhibit

PM Jitter.

9.1.2 Jitter of Autonomous Systems (FM Jitter)

A free running oscillator is an autonomous system, its output period may vary over time, its

jitter is called FM (frequency modulation) jitter. Since the variation of a signal transition

does not depend on the one before the jitter is accumulating which means the phase drifts

without bound. As with PM jitter, it is assumed that the disturbing signal which produces the

jitter has white spectrum, Gaussian distribution and a sufficiently small amplitude to permit

linear calculation. In praxis, these assumptions are not necessarily correct: on top of the

white thermal noise, there is usually flicker noise with a 1/f spectrum and often periodic

components.

9.2 Jitter Measures

As jitter is a random effect, it can only be characterized using statistical terms. All of the

jitter measures below use the standard deviation σ of some term describing the variation of

period length, their dimension is time. Depending on application and metric, sometimes the

1 σ value is specified, sometimes the 3σ and sometimes a min-max value (silently assuming

a certain σ value). Some jitter metrics just specify an integral statistical value while some

allow deeper insights in the jitter characteristics because they depend on the measurement

duration, some of them depend on the measurement duration:

9.2.1 Cycle Jitter (or Cycle-to-Cycle Jitter)

This is the jitter definition that most people mean when talking about jitter as a single number,

it is also called jitter per clock cycle and is independent of the observation time. The cycle

jitter J c measures the variance of the period τ compared to the average period τ :

J 2c = σ 2(τ − τ ) = lim N →∞

1

N

N

∑k =1

(τ k − τ )2

(9.2.1)

Frequency drift is not covered by this metric (because the period average τ varies over time),

it merely describes the magnitude of period fluctuations.

9.2.2 Period Jitter

This jitter measure describes the displacement of one clock edge relative to the preceding

edge. The period jitter J p is defined as the standard deviation of the difference between two

successive transitions, T k = t k +1 − t k . As it is a measure over one cycle, it cannot distinguish

between PM- and FM-Jitter and is independent of the observation time.

J 2 p = σ 2(T k ) = lim N →∞

1

N

N

∑k =1

(t k +1 − t k )2

(9.2.2)

Slow changes like 1/f noise modulation of the period are suppressed by this jitter metric.

Period jitter is an important specification for digital timing, since it gives the minimum /

maximum duration of a clock cycle which is needed e.g. for sythesis constraints.




9.3 Phase Error 119

9.2.3 Long-Term Jitter

This jitter metric is a generalized version of the period jitter, it measures the standard devia-tion of the timing difference between a signal transition and the n-th succeeding one. When

J l,n is known for all n, the jitter process can be fully characterized.

J 2l,n = σ 2(t k +n − t k ) = lim N →∞

1

N

N

∑k =1

(t k +n − t k )2

(9.2.3)

If (9.2.3) looks familiar - that’s because J 2l,n is a measure for the auto-correlation of the period

duration.

9.2.4 Accumulated Jitter

9.2.5 Absolute Jitter9.2.6 Allen-Variation

Allen-Variation is a usual time-domain measure for oscillatorshort-term stability: It measures

the rms change in successive frequency measurements for short gate times (milliseconds

to seconds) and is important in timing applications. It typically improves as the gate time

increases until it becomes a measurement of the long term drift or aging of the oscillator.

9.3 Phase Error

The jitter metrics described above were absolute measures. Often, one is more interested in

the variation of edge timing, relative to the period. This measure is called phase error φ e, it

also describes a property in the time domain (in contrast to phase noise, see below). Jitter

and phase error are related by:

φ e [rad] = 2π f 0 σ J or φ e [deg] = 360 · f 0 σ J (9.3.1)

where σ J is one of the jitter metrics described above. Peak jitter translates into peak phase

error and RMS jitter into RMS phase error. However, phase error measures rely on a fixed

period 1/T 0, therefore not all jitter measures can be translated into phase errors.

Often, the peak-peak phase error is of interest (e.g. in digital systems where a minimum clock

period must be guaranteed). When the error signal is noise with a gaussian distribution,

σ φ = φ e, RMS

i.e. the standard deviation σ φ of the phase error φ e(t ) is equal to the RMS phase error. Now,

it can be calculated how often a certain peak phase error is exceeded: For example, the phase

error becomes larger than the 3σ value (or 3 times the RMS phase error) in 0.3% of the

transitions (in average). Mathematically put:

p% = 100% ·erfc

φ e, pk √2φ e, RMS

(9.3.2)

= 100% ·erfc

φ pk , pk

2φ e, RMS

(9.3.3)

This means, there is a p% probability that the phase error becomes larger than a certain peak

phase errorφ e, pk . For details about Gaussian distribution and error function seeappendix G.1.





Another measure for the phase error is the Error Vector Magnitude (EVM) used with phase

modulation schemes like QPSK. Here, each transmitted value or symbol is regarded as a

vector (phase / amplitude space). When the phase of the signal is wrong by φ e, there is

an error vector whose magnitude | E | is a measure for signal integrity (assuming there is no

amplitude error):

| E |2 = 2 R2 −2 R2 cosφ e

= 2 R2(1− cosφ e)

≈ 2 R2

1− (1− φ 2e

2)

; cosφ e ≈ 1− φ 2e

2

⇒ | E | ≈ Rφ e [rad] (9.3.4)

where the cosine has been approximated by the first term of a series expansion which is onlyvalid for small phase errors.

The relative EVM is given in percent, i.e. the radius has been set to one:

EVM ≈ 100% ·φ e [rad] (9.3.5)

= 100% · π

180 ·φ e [deg] (9.3.6)

9.4 Phase Noise

As mentioned in the introduction, one of the main concerns in PLL design for wireless ap-plications is the noise performance (jitter performance for applications that are rooted more

in the time domain rather than the frequency domain). PLLs are mainly used to generate the

local oscillator (LO) frequency which is used for downconverting (receive path) the wanted

signal from the RF domain into the baseband. Phase noise reduces the sensitivity of the re-

ceiver because weak signals are “smothered” in the LO noise. Additionaly, strong signals at

nearby frequencies can be mixed into the signal path, reducing the selectivity. In the transmit

path, the LO is used to upconvert the signal from the baseband to the RF domain. Here, LO

noise leads to emission of unwanted frequencies which disturbs neighbor channels and may

violate limits set by e.g. the ETSI or FCC. Besides, a noisy LO increases the bit error rate of

the transmitted data.

An ideal oscillator waveform would be noiseless, for the case of a sinusoidal waveform withamplitude A and frequency f 0 the signal can be described by s(t ) = A cos(2π f 0t +φ ). In the

real world, there is always noise, affecting phase and amplitude of the signal:

s(t ) = An(t )cos(2π f 0t +φ n(t )) (9.4.1)

(9.4.1) shows a signal with random amplitude modulation and phase modulation (phase jit-

ter), An(t ) and φ n(t ). While the Fourier transform of an ideal sinusoid shows two dirac pulses

at ± f 0, the noise creates “skirts” around f 0. The energy of the signal is no longer concen-

trated at a discrete frequency, it is spread over a larger frequency range. The better the quality

of the generated signal is, the narrower this frequency band will be. Initially, the energy of the

noise will be distributed equally between amplitude noise An(t ) and phase noise φ n(t ). How-

ever, every oscillator has an amplitude limiting mechanism (otherwise the amplitude would

grow infinitely), be it by the non-linearity of the oscillating devices or by a dedicated ampli-

tude control mechanism. In PLLs with digital circuitry (frequency synthesis, clock-and-data




9.4 Phase Noise 121

recovery, ...) the amplitude is limited anyway. In both cases, the amplitude noise contribution

can be neglected, reducing the noise power by 3 dB1:

s(t ) = Acos(2π f 0t +φ (t )) (9.4.2)

It is assumed that the phase noise φ n(t ) is purely random signal. This is not generally true

- φ n(t ) may have periodic content that shows as discrete lines (spurious sidebands) in the

frequency spectrum, as shown in chapter 6.

[...]

The relative noise power (or noise-to-signal ratio) is equal to the RMS phase error φ e, RMS:

N φ

P= (σ J , RMS ·2π f 0)2 = φ 2e, RMS [rad] (9.4.3)

Using the Wiener-Khinchine Theorem, the relative power of the phase noise can also be

calculated in the frequency domain:

N φ

P= 2

∞

f min

L( f ) df (9.4.4)

where L( f ) is the relative phase noise density in W/Hz at an offset f from the carrier. L( f ) is

symmetric around the carrier, but only one side is regarded in (9.4.4). Hence, the factor 2 is

needed to get the total phase noise power.

Therefore, when the total phase noise power is known, it’s easy to calculate the RMS phase

error:

φ e, RMS =

2 ∞

0 L( f ) df (9.4.5)

When using PLLs, nearly all the produced noise power is contained in the passband. There-

fore, the integration is usually simplified by taking the loop bandwidth as the upper integra-

tion limit. Near zero frequency offset from the carrier the noise power becomes very large.

However, the minimum frequency of interest depends on the needed time frame: If e.g. the

analysis runs over a period of 1ms, the minimum frequency of interest is 1kHz. Lower fre-

quencies do not have an influence on the measurement.

1This is not true for frequencies far from the carrier.




Chapter 10

Noise In The PLL

There is no carrier, there is only

concentrated noise.

B.-G. Goldberg

In the chapters 6.3 and in the Appendix A it was shown that periodic disturbances on the VCO

control voltage are converted up around the carrier frequency f 0, creating discrete spurious

sidebands.

Noise on the control voltage, vn

(t ), has a similiar effect1 The resulting output spectrum of the

VCO now contains the noise spectrum V n( f ), folded around the carrier, instead of discrete

spurious sidebands. Usually, vn(t ) has a sufficiently low amplitude to use the low-modulation

index approximation. The spectrum of the VCO output voltage with broadband noise on the

control voltage looks very similiar to (6.3.2) (see D.4):

VCO Spectrum with Noise on the Control Voltage

Svco( f ) ≈ A

δ ( f − f 0) +

K vco

2

V n(| f − f 0|)| f − f 0|

(10.0.1)

i.e. V n( f ) is upconverted around the carrier and multiplied by 1/| f − f 0| (-20dB/dec) due

to the integrating behaviour of the VCO (fig. 10.1). If the bandwidth of vn(t ) is larger than

BW = f 0/2 there will be additional folding back of noise components with harmonics of the

carrier (not shown).

10.1 Noise Transfer Properties of the PLL

The various noise sources inside and outside a PLL are transferred differently to the PLL

output. The noise transfer function from all noise sources to the output can be calculated

using the model in fig. 10.2 [Roh97, p.114]:

1This can be shown by splitting broadband noise into many narrowband noise signals that can be treated like a

sinusoid.

123



124 Noise In The PLL

V (f) n

f n f

0 f +f 0 n

f 0 n −f

log |S (f)| vco

−20dB/dec

f 0

f +f 0 n

f 0 n −f

|S (f)| vco

1/f

Figure 10.1: Upconversion of Noise Around the Carrier f 0

ω 0 , φ0

∆φn,0

φ0 N

φ +∆φ00

N

1

+

CP

PDF(s)

vn,LFn,det

i

vn,det

φ ref

∆φn,ref

∆φn,div

Loop Filter

Divider

VCO

Phase Detector /

Charge Pump

Figure 10.2: PLL Block Diagram Showing Various Noise Sources

Phase Noise Components in a PLL

∆φ 2O(s) = C 2(s)

∆φ 2re f + ∆φ 2div +

v2n,det

K 2φ

+ 1

1 + GH (s)2

K VCO

s 2

v2n, LF + ∆φ 2vco(s) (10.1.1)

The resulting phase noise ∆φ 2O(ω ) is double side band noise, single sideband noise L (ω ) is

simply half of ∆φ 2O(ω ).

(10.1.1) has two terms with different behavior: phase noise from the reference clock, ∆φ re f ,

from the divider output, ∆φ div and from the output of the phase detector / charge pump vn,det

is low-pass filtered with the closed loop transfer function |T ( jω )| (fig. 10.3). These three

noise components are often (but not quite correctly) called PLL noise, N PLL. Closed loop

gain was defined (2.1.16) as:

T (s) =φ Oφ re f

=G(s)

1 + GH (s)=

KF (s)s + KF (s)/ N

≈ N for ω ω c

G( jω ) ∝ (ω c/ jω ) p− zfor ω ω c




10.1 Noise Transfer Properties of the PLL 125

This means, inside the loop bandwidth the noise is multiplied by N , outside it is attenuated

∝ 1/ f p

− z where p is the order of the PLL and z is the number of zeros of the loop filter

transfer function.

| T(j ) |

∼ ωz−p

ωc

log ω

N

−3dB

ω

Figure 10.3: Noise Transfer Function for Reference Clock, Divider and PD / CP

In contrast to that, phase noise from the VCO, ∆φ vco is high-pass filtered - inside the loop

bandwidth it is attenuated by the open loop gain 1/GH (s) (2.1.15), i.e. low frequencies are

attenuated most. Outside the loop bandwidth, the VCO noise is no longer controlled by the

loop, its transfer function is simply one (fig. 10.4):

1

1 + GH (s)=

1

1 + KF (s)/ Ns≈ 1/GH ( jω ) =

N jω

KF ( jω )for ω ω c

1 for ω ω c

Inside the loop bandwidth, the higher order poles of the loop filter have no effect - they kick

in at frequencies near and above f c. This means for an integrating loop filter that only the

pole at the origin (integrator) (and the VCO pole itself, of course) affect the transfer function.The VCO noise transfer function grows with ω 2 (40 dB/dec) for this kind of loop filter (solid

line in 10.4). A non-integrating loop filter has a more or less constant transfer function inside

the loop bandwidth and VCO noise is transferred to the output proportional to ω (20 dB/dec,

dashed line in 10.4).

Noise from the loop filter, vn, LF , (e.g. from the loop filter resistors) can be treated like phase

noise from the output of the VCO, additionally it has to be multiplied with the VCO transfer

function K VCO /s.

log 1/ | 1+GH(j ) |

ωc

ω

∼ ω2∼ ω

ω

1

(Typ 2)(Typ 1)

Figure 10.4: Noise Transfer Function for VCO

Next, the contributions of different noise sources will be analysed in more detail:

10.1.1 The Famous PLL Noise Formula

Often, one is only interested in the integral effect of PLL noise. Phase error in a GSM trans-

ceiver or the RMS jitter for communication systems are examples for this. Figure xxx shows





clearly that nearly all noise power is contained in the passband of the PLL (this becomes

even more obvious when using a linear instead of the logarithmic dB scale). Here, the noise

is usually dominated by reference clock, divider and CP/PD, scaled with the division factor

N , see (2.1.16) and figure 10.3.

This allows to simplify the general formula (10.1.1)

∆φ 2O(ω ) ≈ N 2

∆φ 2re f + ∆φ 2div +

v2n,det

K 2φ := N 0,PD

for ω < ω c

Often, things can be simplified even more - in a well designed system the noise performance

of the reference path is superior to the actual PLL block, therefore its noise contribution can

be neglected. And as the customer doesn’t care whether the noise is being produced by the

phase detector or the divider, these two terms can be combined into noise referred back to the

input of the phase detector, N 0,PD.

In order to compare the noise performance of different PLLs, it would be great to specify

a single figure for the inband phase noise. However, the phase noise at the output not only

depends on the division ratio N but also on the reference frequency f re f . A handwaving

explanation for this goes like that: in locked state, the input signals of the phase detector both

operate on the reference frequency. The amount of jitter on each edge does not depend on the

frequency, it is determined by temperature, supply voltage, slew rate and some other design

and system parameters. However, the number of jittery edges per second and hence the noise

power is proportional to the referency frequency: N 0,PD ∝ f re f . The leads to the famous PLL

inband noise formula:

Famous PLL Inband Noise Formula

L 0 = L PD

f re f =1 Hz + 20log N + 10log f re f

1 Hz(10.1.2)

When e.g. the reference frequency is doubled, the divider ratio N can be halfed to achieve the

same output frequency. This increases the noise due to the phase detector by 10log2 = 3dB,

but reduces the noise gain of the PLL by 20log2 = 6dB, giving a performance improvement

of 3 dB.

Typical values for the phase noise floor at the phase divider areL

PD f re f =1 Hz = −200 . . . −220dBc(Hz). See example 13on how to use this formula in praxis.

EXAMPLE 13: Comparison of Inband Phase Noise of different PLLs

The inband phase noise floor L 0 of three different PLLs is measured:

f 0 f re f N L 0 L PD

f re f =1 Hz L 0(1.8GHz)

PLL A 1.4 GHz 200 kHz 7000 -81 dBc -211 dBc -78.9 dBc

PLL B 3.8 GHz 400 kHz 9500 -75 dBc -210.5 dBc -81.4 dBc

PLL C 0.9 GHz 26 MHz 34.62 -93 dBc -198 dBc -87 dBc

In the table above, (10.1.2) has been used first to calculate the phase noise at

the phase detector for a reference frequency of 1 Hz, L PD

f re f =1 Hz . From this




10.2 Noise Contributors in the PLL 127

value, the phase noise at an output frequency of 1800 MHz has been calculated.

PLL C has a non-integrating loop filter with relatively long turn-on times of the

CP. This leads to a higher noise floor L PD, referenced back to the PD. Still, the

inband phase noise L 0 is very low due to the low division ratio N .

10.2 Noise Contributors in the PLL

10.2.1 Divider Noise

For most applications, the noise produced by divider stages does not dominate the total phase

noise in a PLL. Well designed TTL and CMOS dividers show a noise floor around -160 .. . -

170 dBc/Hz. Due to their lower slew rates, dividers using current mode techniques (ECL,CML) only reach -155 . . . -150 dBc/Hz. The noise level goes up at frequencies near the car-

rier due to flicker noise and modulation effects, but otherwise it is white.

The most important property of dividers with relation to noise and spurious sidebands is that

dividing the frequency by a factor N also reduces phase noise and spurious sidebands by the

same amount (20 log N in dB’s). This noise reduction is independent from the physical im-

plementation, i.e. it doesn’t matter whether the frequency is divided using a digital divider or

an analog mixer. It also works the other way round - when the signal frequency is multiplied

using e.g. a PLL, the noise and spurious levels are increased with the multiplication factor.

As multiplication and division are non-linear operations, the effect is best explained in the

time domain: the absolute jitter of a signal is not reduced by a division by N , however, the

period length is increased by the same factor.However, the spacing of spurious sidebands from the carrier is not reduced by frequency di-

vision as might be expected: If e.g. a 3.9 GHz signal with spurious sidebands at ±200kHzis

divided by 2, the divided carrier has a frequency of 1.8 GHz (as expected) but the the side-

bands are still spaced by 200kHz. A handwaving explanation for this is: looking at the time

domain once more, we see that the position of the edges of the carrier signal are modulated in

time (jitter and sidebands). Removing e.g. every other edge (division by 2) does not change

the way how the edges move to and fro over time. This is especially true as the spectral

components we are interested in have a much lower frequency than the carrier.

As this is not very intuitive, the proof in [Roh97, pp. 102 - 105] is repeated here: The spurious

signal at the divider input is described as a carrier of frequency ω 0 modulated by a sine wave

of frequency ω m:2

sin(t ) = Acosω 0t + ∆ f

f msinω m

(10.2.1)

where ∆ f is the peak frequency deviation of the carrier. The quotient φ p = ∆ f / f m is the

peak phase deviation, also called modulation index µ . For low peak phase deviations φ p 1

(narrowband FM), the low modulation index approximation can beused, expanding the signal

into the carrier and the two sidebands:

sin(t ) ≈ A cosω 0t Carrier : vc

+ Aφ p2

(cos(ω 0 +ω m)t − cos(ω 0 −ω m)t ) Modulation or Noise: vn

(10.2.2)

This form is very useful to find the relationship between power spectral density and phase

noise of a signal:

2This could also be a narrowband noise signal.





Phase noise L ( f m) is defined as the noise-to-signal power ratio in a 1 Hz bandwidth per

sideband at an offset of f m

from the carrier:

L in( f m) =v2

n( f m)

v2c

=φ 2 p ( f m)

4=

φ 2rms( f m)

2(10.2.3)

The total noise density is the noise in both sidebands and will be called N φ

N φ ( f m) = 2L ( f m) = φ 2rms( f m) (10.2.4)

The phase φ i(t ) of the input signal is given by

φ i(t ) = ω 0t +∆ f

f msinω mt (10.2.5)

its instantaneous frequency by

ω i(t ) =d φ i(t )

dt = ω 0 +

∆ f

f mω m cosω mt = ω 0 + ∆ω (t ) (10.2.6)

A frequency divider by N divides frequency and phase by N , giving an output phase of

φ o(t ) = φ i(t )/ N =ω 0t

N +

φ p N

sinω mt (10.2.7)

and an output (fundamental) frequency of

ω o(t ) = ω i(t )/ N =d φ o(t )

dt =

ω 0 N

+∆ f

N f mω m cosω mt =

1

N (ω 0 + ∆ω (t )) (10.2.8)

This result does not mean that the distance of the modulating signal from the carrier has been

reduced by N - the term ∆ω (t )/ N only means that the amount of frequency modulation is

decreased by a factor of N . Narrowband FM approximation has to be used once more to see

what happens to the spurious sideband:

sout (t ) = Acos

ω 0t

N +

φ p

N sinω mt

≈ Acos

ω 0t

N

+

Aφ p2 N

cos

ω 0 N

+ω m

t − cos

ω 0 N

−ω m

t

(10.2.9)

This shows that the sidebands still are a distance of

± f m from the carrier after a frequency

division by N . The phase noise at the output of the (noiseless) divider is:

L out ( f m) =v2

n( f m)

v2c

=φ 2 p ( f m)

4 N 2= L in( f m)/ N 2 (10.2.10)

The phase noise power of the spurious sidebands (or other noise at the divider input) is re-

duced by N 2 after a frequency division by N , i.e. by 6 dB for a division by 2 and by 20 dB

for a division by 10.

So far, a noiseless divider has been assumed. In reality, the divider stages themselves add

phase noise which may become dominant for very low noise input signals or long divider

chains. In a divider chain, the last divider is the most critical one for noise performance be-

cause noise of the preceding divider stages is reduced by the subsequent stages. In a well de-

signed divider, the first stages are optimized for high switching speed (high input frequency)

and the last stages as well (high switching speed = low phase noise).





10.2.2 Phase Detector and Charge Pump Noise

For this noise analysis PD and CP are regarded as one block. Phase detector noise usually

consists of phase noise from the phase detector itself (switching uncertainty) and current

noise from the charge pump or voltage noise from the output buffer. The noise at the output

of the phase detector v2n,det ( f ) is transferred to the VCO output with the transfer function (see

eqn. 10.1.1)

∆φ 2O(s)

v2n,det

=C 2(ω )

K 2φ ≈

N

K φ

2

for ω ω cG(ω )

K φ

2

=

K VCO

ω F (ω )

2

∝ ω z− p for ω ω c

(10.2.11)

The same equations apply for transferring current noise from the output of the PD/CP to theoutput of the VCO - just replace v2

n,det ( f ) by i2n,CP( f ) and use the corresponding K φ definition

in A/rad.

Inside the loop bandwidth, the phase detector transfer function is flat, it is proportional to the

division ratio, N 2 and inversely proportional to the phase detector gain, K 2φ . Outside the loop

bandwidth, the noise is attenuated with ( f c/ f ) p− z where p is the order of the PLL and z is

the number of zeros in open loop transfer function.

When the charge pump current is doubled, K φ is doubled as well. This means, the contribu-

tion of intrinsic phase detector / charge pump noise to the total PLL in-band noise improves

by 6dB. However, the noise current increases as well: Doubling the charge pump current by

adding a second uncorrelated noisy source increases the noise current by√

2 or 3 dB. This

improves the signal-to-noise ratio of the CP current by 3 dB. When the current is doubled

“noiselessly”, e.g. by increasing the ratio of a current mirror (producing no noise of its own),

the noise current is doubled as well (+ 6 dB). Here, you don’t gain in SNR.

From this, one would expect little or no noise improvement from cranking up the charge

pump current. In reality however, the charge pump current often has a huge influence on PLL

phase noise - the explanation is that the charge pump current influences other PLL parameters

as well (see box ”When the CP current is doubled”).





When the CP current is doubled:

- K φ is doubled as well which improves in-band PD noise suppression by 6 dB. However,

the wider noise bandwidth (see next point) “eats” up a part of this gain.

- loop and noise bandwidth increase by approximately√

2 (for a second order system

with reasonable damping ζ ). The higher loop bandwidth attenuates VCO in-band noise

by 3 dB (Type I PLL) or 6 dB (Type II PLL). At the same time, the higher noise

bandwidth emphasises the PD - noise components. It depends on the actual VCO

and reference noise parameters whether the total integrated phase noise is reduced or

increased.

- in a type I PLL, the duty cycle of the CP is halved because the tuning voltage for

a given frequency has to stay constant. This means, increasing CP current reduces

the on-times of the CP and therefore the amount of current noise fed into the loop

filter per reference period. It is shown below that this reduces the charge pump noise

contribution by approx. 3 dB.

- not much changes in a Type II PLL: here, the CP operates with a very low duty cycle

anyhow - in locked state, the CP is active only during the ABL (anti-backlash) pulses.

This means, that the CP normally doesn’t dominate the total phase noise at the VCO

output, here, the PD with its timing uncertainties often is the main noise source.

In praxis, it may be very difficult to estimate whether charge pump, phase detector, VCO or

some other noise source dominates the inband phase noise of a PLL.

Next, the charge pump noise3

will be regarded in detail: Noise from the CP is switched noise(for details see C.3): every time the charge pump is active, a noise current is transferred into

the loop filter. This noise may come e.g. from the bias circuitry, the actual output devices

or from substrate coupling. Its (unswitched) small-signal current noise power must be deter-

mined first (e.g. by an AC noise simulation) in order to calculate the resulting switched noise

power. As the noise current usually scales with the charge pump current, it makes sense to

define a “Current Noise-to-Signal-Ratio” NSRi.

= i2n/ I 2CP to compare different measurements

/ simulations.

The switching operation folds the noise around multiples of the switching (=reference) fre-

quency f re f . Spectrum and power of the output noise therefore depend on the pulse width T w,

reference frequency and input noise bandwidth f n. The effective noise power in the “base-

band” (0 . . . f sw/2) at the CP can be calculated as

N i,CP( f ) = α k i2n( f ) where α =

T w

T re f

(10.2.12)

The exponent k is in the range 1 . . .2; it is determined by pulse width, noise bandwidth etc.

(see chapter C.3): k = 1 when the CP noise is white or current has a very wide noise band-

width compared to the reference frequency, k = 2 when its noise bandwidth is less than f re f /2.

This noise power density can be referred back to the PD input by dividing it by the PD gain

K 2φ (only valid inside the loop bandwidth). Taking half of this value gives the two-sided noise

power density Sφφ (noise power is split between positive and negative frequencies). Sφφ is

convenient to use because it has the same numeric value as phase noise L ( f ):

3The same calculations can be done for a PD with voltage output.





L PD,iCP( f ) = Sφφ ,PD,iCP( f ) =

N i,CP( f )

2K 2φ =

α k i2n( f )

2 I 2CP/4π 2 = 2π 2

α k

SNRi( f ) (10.2.13)

Finally, the phase noise value at the VCO output is obtained by multiplying L PD,iCP( f ) with

the divider ratio N 2:

In-band CP noise contribution

L iCP( f ) = 2 N 2π 2α k SNRi( f ) (10.2.14)

EXAMPLE 14: PLL phase noise due to CP noise

A chargepump drives a current of 1 mA into an averaging loop filter with a first

resistor of 1k Ω and a duty cycle of 1:4 (α = 0.2), giving an average loop fil-ter voltage of 200 mV. The PD/CP has a gain of K φ = 1mA/2π . The reference

frequency is 26 MHz and the VCO output frequency 858 MHz, requiring a divi-

sion ratio of N = 33. The CP produces a white noise current density of in = 250

pA/ √

Hz.

The resulting Noise-to-Signal Ratio is NSRi = 6.25 ·10−14 /Hz or -132 dBc (Hz).

As the noise is white (very wide bandwidth), the noise power must be scaled with

α (k = 1) or the noise current with√α . This gives an effective noise current of

in,e f f =√α in ≈ 112pA/

√Hz. Referred back to the PD, the in-band phase noise

is:

L PD,icp = i2n,e f f /2K 2φ = α · i2

n/2K 2Φ = 2.47 ·10−13rad2/Hz

or

L PD,icp = 10log(2π 2α ) + NSRi = 6dB−132dBc(1Hz) = −126dBc(1Hz)

At a reference frequency of 1Hz, the PD input phase noise would be:

L PD,icp

f re f =1 Hz = −126dBc(1Hz) −10log(26 MHz/1Hz) = −200dBc(1Hz)

At the output of the VCO, this noise appears multiplied by N 2 (inband only):

L o,icp = 20log N +

L PD,icp = 20log N + 10log(2π

2

α ) + NSRi= 20log33+ 6dB− 132dBc(1Hz) = −95.6dBc(1Hz)

In order to achieve a loop filter voltage of 400 mV, the duty cycle must be in-

creased to 2:3, i.e. α must be doubled. This increases the phase noise at the

output (same calculation as above) by 3 dB to -92.6 dBc (1 Hz).

Assume now the noise is bandlimited to f re f /2 with a current noise density of

300 pA/ √

Hz ( NSRi = -130.5 dBc(Hz) ). In this case, noise power is scaled with

α 2, giving phase noise results of L o,icp = -101 dBc (1 Hz) [α = 0.2] and -95 dBc

(1 Hz) [α = 0.4]. Here, the phase noise due to the charge pump current grows

by 6 dB when the on-time of the charge pump is doubled.





10.2.3 Reference Noise

Noise from the reference input L re f ( f ) directly influences in-band phase noise at the VCOoutput L O,re f ( f ):

L O,re f ( f ) = N 2L re f ( f ) for f f p (10.2.15)

EXAMPLE 15: PLL phase noise caused by reference noise

A 26 MHz reference oscillator should contribute less than -100 dBc to the in-

band phase noise of a PLL operating at 1.9 GHz. What is the maximum phase

noise of the reference oscillator?

L re f ( f ) <−

100dBc

−20log1.9GHz/26MHz =

−137.3dBc

10.2.4 VCO Noise

Typically, a free running VCO usually has a phase noise characteristic shown in fig. 10.5:

log f 1 fl

−20db/dec

−30db/dec

m L (f )

f m

f

White Noise Noise Floor1/f Noise

Figure 10.5: Open loop VCO phase noise at an offset of f m from the carrier

For frequencies above f f l , the output noise is white phase noise, caused e.g. by the output

buffer, termination resistor etc. In the frequency range between f c and f f l , the output phase

noise is dominated by white noise in the VCO core devices (flat spectrum). This noise mod-

ulates the carrier, resulting in a -20 dB/dec. characteristic. The flicker noise of VCO core

devices drops with -10 dB / dec, producing a -30 dB/dec. characteristic at the output.

10.2.5 Noise of Loop Filter Resistors

Noise from the output of the loop filter is transferred to the PLL output with the transfer

function ∆φ 2n,O(s)/v2n, LF (s). Outside the loop bandwidth, |T (s)| 1, the loop filter noise

directly modulates the VCO:





∆φ 2n,0

(s)

v2n, LF

= 1

1 + GH (s)2K

VCOs

2

≈ K VCOs

2

for ω ω c (10.2.16)

Inside the loop bandwidth, |GH ( jω )| 1, and the transfer function becomes

∆φ 2n,O(s)

v2n, LF (s)

≈ 1

GH ( jω )

K VCO

ω

2 for ω ω c

=

N ω

KF (s)

K VCO

ω

2

≈ N (ω )

K φ 2

for Type I PLLs N (ω )ω C ∗1

K φ

2

for Type II PLLs(10.2.17)

The last simplifications can be made because inside the loop bandwidth, the transfer function

of non-integrating loop filters F (s) ≈ 1 (Type I PLL). Integrating loop filters can be approx-

imated by F (s) ≈ 1/sC ∗1 (Type II PLL), where C ∗1 is the equivalent loop filter capacitance

(see xxx). K was defined as K .

= K VCO K φ . This means, Type I PLLs simply transfer the loop

filter noise to the output (scaled by N /K φ ) while Type II PLLs attenuate the low frequency

components of loop filter noise. Outside the loop bandwidth, both PLLs attenuate the noise

with 1/ω .

The loop filter characteristic also filters the noise of the resistors themselves. This noise spec-

trum N (ω ) at the output of the loop filter has to be calculated first. In praxis, the output noisespectrum of the loop filter will be determined using small-signal noise analysis.

EXAMPLE 16: PLL phase noise due to noisy loop filter resistors

A 2.2k Ω resistor in a non-integrating loop filter may dominate the noise. N = 70,

K φ = 3V/ π rad, T=300K. Inside the loop bandwidth, this resistor causes single-

sideband (factor 1/2) phase noise L ( f ) of:

L ( f ) =1

24kT R

N

K φ 2

= 1.82 ·10−17V2/Hz4900

0.91V2rad−2

= 1.92 ·10−13rad2/Hz = −127dBc/Hz

assuming that the noise from the VCO is pure phase noise (no amplitude noise).

Example: The noise due to the loop filter resistor R2 in a standard three element integrating

loop filter (fig. 2.12, R2 = 1k Ω, C 1 =1.5 nF, C 2 =12 nF) can be calculated as follows: K φ =

0.5mA/2π rad, K vco = 40 MHz/V, N = 70, BW???

First, the noise spectrum at the output of the loop filter must be calculated: The noise spec-

trum of R2, v2n, R2/∆ f = 4kT R2 is low-pass filtered by C 1 and C 2 [LR00]:





v2n, LF ( f ) =

C 1

C 1 +C 2

2 v2n, R2

1 +

R2C 1C 2

C 1+C 2ω 2

=1

b2

4kT R2

1 +

f f 1

2=

2.04 ·10−19V 2/ Hz

1 + ( f /119kHz)2(10.2.18)

using the definitions of (2.5.2)

b.

=C 1 +C 2

C 1= 9; f 1 =

1

2π T 1=

C 1 +C 2

2π R2C 1C 2= 119kHz

Inside the loop bandwidth, the spectral noise density at the loop filter output due to R2 is

constant, 2.04 ·10−19V2 /Hz. The closed loop noise transfer function can be approximated by(10.2.17), using the equivalent loop filter capacitance C ∗1 ≈ C 1 +C 2. The phase noise at the

output of the VCO is

L R2( f ) =1

2v2

n, LF

N ω C ∗1

K φ

2

= 1.02 ·10−19V 2/ Hz · (0.075rad s/V · f [Hz])2

= 5.69 ·10−22rad2 · ( f [Hz])2 = −212dBc/Hz + 20log f for f f 1

Outside the loop bandwidth, the noise from the loop filter (10.2.19) directly modulates the

VCO (10.2.16). Inserting (10.2.18) into (10.0.1), the VCO power density spectrum for f > f 0 + f c (upper sideband) can be calculated:

S2vco( f ) =

AK vco

2

2V 2n ( f − f 0)

( f − f 0)2

=

AK vco

2b

24kT R2

( f − f 0)2

1 +

f − f 0

f 1

2 (10.2.19)

This result directly gives the phase noise L ( f ) per sideband around the carrier at f 0 (drop

the amplitude A, phase noise is measured in dBc):

L R2( f ) = B f 21

f 2

f 21 + f 2 ; B .= 4kT R2

K vco

2b

2

= 1.28 ·10−4Hz2 = 5.1 ·10−3rad2/s2

≈ 8.41 ·107rad2/s4

f 4= +79.2dBc/Hz−40log f for f f 1

Example: An R3C 3 post filter is added to the loop filter of the last example with R3 = 2.2k Ωand C 3 = 47pF. The noise from R3 is high-pass filtered by C 1 and C 2. At frequencies above

f 4 = 1/(2π R3C ∗1) = 5 kHz, the noise of R3 is transferred to the loop filter output, attenuated

by ≈ 0.7: v2n, LF = 2.55 ·10−17 V2 /Hz. Inside the loop bandwidth, the resulting phase noise is

L R3( f ) =1

2v2

n, LF N ω C ∗1K φ

2

=1

22.55

·10−17V 2/ Hz

·(0.075 rad s/V

· f [Hz])2

= 7.10 ·10−20rad2 · ( f [Hz])2 = −191dBc/Hz + 20log f for f f c





Obviously, the noise contribution of R3 dominates the total loop filter noise. At 1 kHz, this

loop filter has a contribution of -131 dBc/Hz, at 10kHz of -111 dBc/Hz to the total output

noise. Compared to the first example, the integrating loop filter contributes more in-band

phase noise. This is certainly not a general result as loop BW, loop filter elements etc. have

a strong influence. But the loop gain drops with -40dB/dec for an integrating loop filter and

only with -20dB/dec for a non-integrating one.

The total (phase) noise power of the VCO output voltage is calculated by integrating L (s)from f c to ∞ (the integration starts outside the loop bandwidth f c) and doubling the result to

account for the lower noise sideband:

Pn = 2

∞

f c

B f 21

f 2 f 21 + f 2d f

= −2 B

f ∗− 2 B

f 1arctan

f ∗ f 1

∞ f c

= 2 B

1

f c+

1

f 1

arctan

f c

f 1

− π

2

(10.2.20)

using equation (G.5.7).




Part IV

Related Fields

137



Chapter 11

Modulation and Demodulation

11.1 Digital Modulation

11.2 Digital Demodulation

The job of the demodulator is to re-extract the modulation signal m(t ) from the instantaneous

frequency f i(t ). Analog PLLs have been used to demodulate FM signals for quite a long

time, but since the 1990s more and more digital architectures have evolved. All demodulator

architectures can be derived from the same signal processing principle:

Ideal FM Discriminator: The ideal FM discriminator consists of a differentiator followed

by an envelope detector. In order to remove AM disturbances, usually the signal is firstsent through a limiter. The harmonics of the resulting square wave are then suppressed with

a bandpass filter to obtain a nearly sinusoidal signal again. The center frequency of the

bandpass should be equal to the carrier frequency, its bandwith large enough to not distort the

modulation.

In practical implementations, the above principle can only be approximated:

• Time Delay / Phase Shift: The differentiation process of the ideal FM discriminator

can be approximated by a time delay and subsequent subtraction. A typical application

of this principle is phase noise measurement equipment using a variable delay line. For

low-performance applications the time delay may be realized using an all-pass filter, the

subtraction is performed by an EXOR gate. This detector is also called quadrature or

coincidence detector because the phase shift ideally is 90 deg. at the center frequency.

• Slope Detector: Another approximation to the ideal differentiator is the frequency dis-

criminator which converts frequency deviation from a center frequency into amplitude

variation1. The simplest and oldest implementation exploits the frequency selectivity

of an LC - tank tuned to a frequency slightly above the carrier frequency. An FM signal

across the tank will be converted to AM by its frequency sensitivity. This technique has

severe drawbacks, the most notable being its non-linearity because the voltage across

the tank is proportional to the square of the frequency. Distortions increase when the

maximum frequency deviation approaches the center frequency of the LC tank. Crystal

detectors apply the same principle by using the frequency selectivity of crystals. In its

simplest form, one crystal is needed per channel, that’s why this kind of receiver was

mainly used for walkie-talkies or radio amateur applications with a limited number of

channels.1Remember that a differentiation in the time domain is equivalent to multiplication by f in the frequency domain.

139



140 Modulation and Demodulation

• Zero Crossing Detector: Approximates the instant frequency by counting the number

of zero crossings within a gating time interval T G

where f −

1

c T

G f −

1

B. The devi-

ation from the carrier frequency is the momentary modulation data. This principle is

well suited to simple, fully digital demodulators.




Part V

The Toolbox

141



Appendix A

Fourier and Laplace Analysis and

Synthesis

If your only tool is a hammer, you

tend to see all problems as a nail.

Anonymous

Fourier analysis is a family of mathematical techniques, all based on decomposing signals

into sinusoids (see also [Smi99] and [Luk85]). Depending on the signal (periodic or non-

periodic, time-discrete or continous) and the personal flavour (complex vs. real notation),there are several methods to translate a signal between time and frequency domain.

Real life signals are always real valued (i.e. not complex valued) and can be represented

using sinusoids with positive frequencies only (single sided Fourier transform). I call this the

“engineering” form of the Fourier synthesis. For complex signals and for some calculations,

it is more convenient to use the “mathematical” form of the Fourier transform that also in-

cludes sinusoids with negative frequencies (double sided Fourier transform). In this case, I

use double indices (e.g. ckk ) for coefficients and functions. Attention: the single-sided “engi-

neering” coefficients / functions have twice the value of the “mathematical” counterparts!

When the signal of interest is periodic (and infinite), it can be decomposed into a series of

discrete, harmonically related sinusoids. This is called a Fourier series (A.1). When the

signal is not periodic, it can be described by a Fourier integral (A.2). When the signal is

time-dicrete, i.e. sampled, the discrete Fourier transform or DFT (A.3) is used.

A.1 Fourier Series

A periodical signal ve(t ) with period T 1 = 1/ f 1 = 2π /ω 1 can be decomposed into a sum

of harmonic sine / cosine functions with frequencies k f 1 (k = 0,±1,±2, . . .), the so called

Fourier series. The complex coefficients ckk are called Fourier coefficients:

ve(t ) =∞

∑k =−∞

ckk e j2k π f 1t (A.1.1)

ckk =1

T 1

T 1

0ve(t )e− j2k π f 1t dt (A.1.2)

143



144 Fourier and Laplace Analysis and Synthesis

(A.1.1) is called Synthesis Equation or Inverse Transform, (A.1.2) is called Analysis Equation

or Forward Transform. Real life signals ve(t ) are always real valued. In this case, c

kk and

c−kk are complex conjugates, i.e. c−kk = c∗kk = |ckk |e− jφ kk , c0 is real. (A.1.1) can be rewritten

using only positive frequencies ck .

= 2ckk :

ve(t ) = c0 +∞

∑k =1

|ck |cos(k ω 1t +φ k ) or (A.1.3)

= a0 +∞

∑k =0

(ak cosk ω 1t + bk sink ω 1t ) where (A.1.4)

a0 =1

T 1

T 1

0ve(t ) dt (DC Part)

ak =2

T 1 T 1

0ve(t )cos(k ω 1t ) dt , k = 0, 1,... (DC and Real Part)

bk =2

T 1

T 1

0ve(t )sin(k ω 1t ) dt , k = 1,2, . . . (Imaginary Part)

|ck | =

a2k + b2

k ≥ 0 , c0 = a0 (Magnitude)

φ k = arctan

−bk

ak

(Phase)

The “mathematical” form (A.1.1) uses positive and negative frequencies (double sided Fourier

series), while (A.1.3) and (A.1.4) use only positive frequencies (single sided Fourier series).

The coefficients of (A.1.4) are twice as large, because only the positive side of the spectrum is

used. In literature, both single and double sided Fourier transforms can be found. Therefore,equations and coefficients may vary by a factor of two from publication to publication. Here,

with a few exceptions, only positive frequencies are used because spectrum analysers don’t

support negative frequencies yet ...

A.2 Fourier Integral

A non-periodic function vn(t ) cannot be decomposed into a Fourier series. Instead, it is

possible to calculate the Fourier integral for vn(t ), i.e. calculate the frequency spectrum

V nn( f ) for vn(t ):

vn(t ) = F−1 V nn( f ) =

∞

−∞V nn( f )e j2π f t d f (A.2.1)

V nn( f ) = Fvn(t ) =

∞

−∞vn(t )e− j2π f t dt (A.2.2)

Again, (A.2.2) is called Analysis Function or Forward Transform and (A.2.1) is called Synthe-

sis Function or Inverse Transform. V nn( f ) has the dimension amplitude/frequency, therefore

it is called amplitude density spectrum. Usually, V nn( f ) is complex valued.

In general, vn(t ) can be a complex valued function, too. For real world, real valued functions

vn(t ), the frequency spectrum V nn( f ) for negative and positive frequencies is conjugate com-

plex, i.e. V ∗nn(− f ) = V nn( f ) .= V n( f )/2 (A.2.1). In this case, (A.2.2) be rewritten using only

positive frequencies:




A.3 Discrete / Fast Fourier Transform 145

vn(t ) = ∞

0a( f )cos2π f t + b( f )sin2π ft d f where (A.2.3)

a( f ).

= 2 ReV nn( f ) = 2

∞

−∞vn(t )cos2π ft dt (Real Part) (A.2.4)

b( f ).

= 2 ImV nn( f ) = 2

∞

−∞vn(t )sin2π ft dt (Imaginary Part) (A.2.5)

Often, these equations are expressed in ω = 2π f instead of f . Simply replace f by ω /2π and d f by d ω /2π in (A.2.3), (A.2.4) and (A.2.5) to re-write the equations in ω .

A.3 Discrete / Fast Fourier Transform

The additional noise floor created by a discrete Fourier transform is:

NF FF T (dB) = 10log3 N DFT

π ENBW ??? (A.3.1)

where N DFT is the number of DFT samples and ENBW is the equivalent noise bandwidth of

the window function. For a rectangular window, the ENBW is the same as its bandwidth, for

a Hanning window, ENBW = 1.5∆ f .

A 4096 point DFT with an effective noise bandwidth of 10 kHz creates a noise floor




A.4 Some Fourier Transformations

The following transformations are two-sided (positive and negative frequencies):

Similiarity : a · s(bt ) −• a

|b|S

f

b

Dirac pulse : δ (t ) −• 1

Rect pulse : rect

t

T w

−• T w

sinπ T w f

π T w f = T w sinc(π T w

Sinc pulse : sinc( f 0t ) −• 1

f 0rect

f

f 0

Periodic δ − function :∞∑

n=−∞δ (t − nT ) −• 1

T

∞∑

n=−∞δ

f − n

T

Periodic signal :

∞

∑n=−∞

s(t − nT ) = s(t ) ∞

∑n=−∞

δ (t − nT ) −• S( f )

T

∞

∑n=−∞

δ

f − n

T

Periodic. rect . signal : rect

t

T w

∞

∑n=−∞

δ (t − nT ) −•∞

∑n=−∞

T w

T sinc

π nT w

T

δ

f

Ideal sampler : s(t )∞

∑n=−∞

δ (t − nT ) −• 1

T

∞

∑n=−∞

S

f − n

T

Sample & Hold ( Zero Order Hold ) : rectt

τ s(t )∞

∑n=−∞

δ (t − nT ) −• τ

T sinc(πτ f )

∞

∑n=−∞

S f − n

T

Cosine function : cos 2π f 0t −• 1

2[δ ( f − f 0) +δ ( f + f 0)]

Sine function : sin 2π f 0t −• j

2[δ ( f − f 0) −δ ( f + f 0)]

Fourier series :∞

∑k =0

ck cos k ω 1t −•∞

∑k =0

ck

2[δ ( f − k f 0) +δ ( f +

C h r i s t i a nM¨ unk e r

P h a s e N o i s e a n d S p ur i o u s S i d e b a n d s i nF r e q u e n c y S y n t h e s i z er s v 3 .2

D e c e m b e r 2 0 ,2 0 0 5



Bandpass transform : s(t ) · cos2π f 0t −• 1

2[S( f − f 0) + S( f + f 0)]

Freq. shift : s(t ) · e j2π f 0t −• S( f − f 0)

Delay : s(t −∆T ) −• S( f )e− j2π f ∆T = S( f )e− j f ∆

where ∆φ .=

2π ∆T

T 0

Integrator :

t

−∞s(τ )d τ −• S( f )

j2π f +

1

2S(0)δ ( f )

Step function : ε (t ) −• δ ( f )

2+

1

j2π f

C h r i s t i a nM¨ unk e r

P h a s e N o i s e a n d S p ur i o u s S i d e b a n d s i nF r e q u e n c y S y n t h e s i z er s v 3 .2

D e c e m b e r 2 0 ,2 0 0 5



148 Fourier and Laplace Analysis and Synthesis




Appendix B

Noise

Eine Theorie sollte so einfach sein

wie mglich, jedoch nicht einfacher.

Albert Einstein

B.1 Statistical Terms

• ensemble

• expectation 1st and 2nd order, variance, mean

• stationary process: E vn(t ) = vn(t )

• cyclostationary process: [Kun98], [PK04]

B.2 Thermal Noise

Thermal noise is a fundamental physical phenomenon that is present in any linear passive

resistor. Its amplitude distribution is Gaussian and the spectral density is flat. The maximum

available noise power of a resistor, i.e. the noise power that can be transferred into a matched

load is1

Pn = kT ∆ f in W (B.2.1)

where T is the absolute Temperature in Kelvin and k = 1.38 · 10−23VAs/K is Boltzman’s

constant. Noise power of a resistor only depends on the temperature and the bandwidth of

interest. At room temperature (T= 300K), the available thermal noise power of a resistor over

a 1-Hz bandwidth is about 4.1 ·10−21 W or -174dBm. The well-known mean-squared noise

voltage (current) per bandwidth ∆ f of a resistor R (also called thermal noise spectral density)

is easily derived from (B.2.1):

v2n/∆ f = 4kT R in V2/Hz (B.2.2)

or1using only positive frequencies as usual

149



150 Noise

i2n/∆ f =

4kT

R in A2

/Hz (B.2.3)

These values are the open circuit (v2n) / short circuit (i2

n) values. The thermal noise spectral

density of a 1k Ω resistor at room temperature is v2n/∆ f ≈ 16.6 · 10−18V2 /Hz or -168 dBV.

Written in rms form, this gives vn/√

∆ f ≈ 4nV/√

Hz. The equivalent current spectral den-

sity is i2n/∆ f ≈ 1.64 ·10−24A2 /Hz or in/

√∆ f ≈ 4pA/

√Hz

Since the channel in a MOSFET is basically a controlled channel resistor, r ch, it exhibits ther-

mal noise (which is also its dominant source of noise). This noise source is best represented

by a noise current generator i2d ,n from drain to source with a value of

i2n,T =

4kT γ

r ch

∆ f (B.2.4)

where 1/r ch is the channel conductance of the MOSFET and γ is a constant depending on the

operation region. In the linear region near V DS = 0, the channel conductance is equal to the

drain-source conductance 1/r ch = gds ≈ β · (vGS − vT ) and γ = 1. The channel conductance

of long devices in the saturation region is ≈ gm where gm =

2β I D = β (vGS − vT ) and

β ≈ W / L ·µ C ox. Due to field effects, γ has a value of approx. 2/3. This gives the formula for

MOS drain noise current density often found in text books

i2n,T (sat.) ≈ 8kT

3gm∆ f =

8kT

3

2β I D∆ f (B.2.5)

Referred back to the input, this gives an equivalent noise voltage of

v

2

n,T (sat.) = i

2

n,T g

2

m ≈8kT

3gm ∆ f (B.2.6)

EXAMPLE 17: White drain noise current of a MOSFET in saturation

A MOSFET at room temperature with a gm of 10 mS in saturation creates a noise

current of

i2n,T (sat.) ≈ 8kT

3gm∆ f = 1.1 ·10−24A2/Hz

This is equivalent to an rms current of in/√

∆ f ≈ 10.5pA/√

Hz, the noise current

produced by a resistor of 145 Ω.

However, in short devices, γ can be much larger (2 ... 3 or even more). This is caused by hotelectrons, producing excess noise.

In any case, thermal noise of a MOSFET in saturation increases with√

I D. Decreasing the

bias current of a MOSFET gives worse noise performance: if e.g. the bias current is reduced

by a factor of 2, the thermal drain current noise is reduced by√

2. However, the load resistor

must be increased by a factor of 2 in order to get the same voltage signal swing. This increases

the noise voltage by√

2, the SNR gets worse by√

2. The larger load resistor may also add

noise - turn up the current for good noise performance!

B.3 Flicker Noise (1/f Noise)

Additionally, there is also flicker noise in many devices (BJTs, resistors, MOSFETs...), which

is caused by imperfections in the crystal and the gate oxide interface. The spectral density of




B.4 Shot Noise 151

flicker noise drops with 1/ f β , its magnitude is described by the empirical constants K f and

β (≈

1).

i2n, f =

K f g2m

C oxW L

∆ f

f β =

K f I Dµ

L2

∆ f

f β (B.3.1)

or, referred to the input:

v2n, f = i2

n, f g2m =

K f

C oxW L

∆ f

f β (B.3.2)

The total noise of a (long) MOSFET in saturation is given by

i2n =

8kT

3

2β I D∆ f

+

K f I Dµ

L2

1

f β ∆ f

thermal noise flicker noise

(B.3.3)

K f depends on process and temperature, typical values are 10−24 . . . 10−22V2F.

The frequency where the flicker noise starts to grow larger than the thermal noise is called

flicker noise corner frequency, for MOSFETs it can be in the range of a few kHz up to several

MHz. Bipolar junctions and even resistors also show flicker noise, however with much lower

corner frequencies (a few ten Hz up to several kHz).

B.4 Shot Noise

B.5 Bandlimited NoiseThe theoretical spectral power density of white noise, e.g. (B.2.2) or (B.2.3), is flat - this

would give infinite total noise power if the bandwidth of interest was infinite. In praxis, sig-

nals and noise are always low-pass signals, therefore, the noise power is limited to sensible

results (E.4).

C

C

R R

−

+

−

+out V n

2v / f = 4kTR ∆

out V

Figure B.1: Equivalent Circuit for Noise of RC Lowpass

Noise generated by a resistor R is filtered by a capacitor C . The resulting noise across the

capacitor appears filtered by a one pole low-pass filter with the time-constant τ RC = RC . This

can be seen easily by splitting the noisy resistor into a noisefree resistor and a noise source

with v2n/∆ f = 4kT R (see fig. B.1). The resulting output voltage has a spectrum of [GM84, p.

689], [GT86, p.505ff]:

v2n,out ( f )

∆ f =

v2n( f )

∆ f

1/ j2π f C

R + 1/ j2π f C

2 =4kT R

1 + (2π f τ RC )2(B.5.1)




152 Noise

The total noise power is calculated by integrating the filtered noise spectral density over the

whole frequency range using (G.5.6):

Pn =

∞

0

4kT R

1 + (2π f τ RC )2

d f ; τ RC .

= RC

=4kT R

2πτ RC

arctan2π f τ RC

∞0

= 4kT R1

4τ RC

.= 4k T Rf n =

kT

C (B.5.2)

−3dB f f

n

v (f)/ f n,out ∆2

f

4kTR

Figure B.2: Noise transfer function and equivalent noise bandwidth

where f n = 1/4τ RC = π /2 f −3dB is the equivalent brick wall bandwidth giving the same total

noise power at the output as the actual transfer function (see fig. B.2). The noise power at

the input is proportional to R, the -3dB frequency of the RC - filter is proportional to 1/ R.

Therefore, the output noise power is independent of R and can only be reduced by increasing

C .

(B.5.2) can also be used to calculate the noise power of an independent noise source filtered

by a noisy RC filter - simply add its spectral noise density v2n/∆ f to the 4kT R within the

integral.




Appendix C

Switching and Sampling

C.1 Switched Signals

When a signal is switched periodically, the switching creates multiple copies of the signal

spectrum in the frequency domain (fig. C.1). These copies of the original signal spectrum

will overlap when the signal bandwidth f BW is larger than half the switching frequency f sw/2

(Nyquist criterium).

We will assume that the switching signal m(t ) is a perfect rectangular signal with frequency

1/T sw and pulse width T w, its duty cycle is α = T w/T sw. 1 The power of this signal can be

calculated easily in the time domain, it is Pm = α m2. The spectrum of m(t) is given by:

m(t ) =∞∑

k =−∞rect

t − kT sw

T w

= rect

t

T w

∞

∑k =−∞

δ (t − kT sw)

−• T w

T sw

sinc π T w f ∞

∑k =−∞

δ

f − k

T sw

=∞

∑k =−∞

α sincπ k α .

=ckk

δ

f − k

T sw

= M ( f ) (C.1.1)

The modulation with m(t) can be described by a multiplication in the time domain which is

equivalent to a convolution in the frequency domain (figure C.1):

ΦSS,mod ( f ) = ΦSS( f ) M 2( f ) = ΦSS( f ) ∞

∑k =−∞

(α sincπ k α )2 δ

f − k

T sw

(C.1.2)

=∞

∑k =−∞

c2kk ΦSS( f − k /T sw) (C.1.3)

The resulting spectrum shows multiple copies of the original spectrum at frequencies S( f −k f sw) weighted with the amplitude of the switching signal’s k-th harmonic. Although the

original signal s(t ) is a bandpass signal, the modulated signal smod (t ) also has components

at DC. This process is also called “downsampling”. At the same time, components may be

generated at higher frequencies (“upsampling”). This effect is often used on purpose for1The results can be adapted to non-rectangular signals if needed.

153



154 Switching and Sampling

2α

wT

wT

w2/T

w1/T

m(t)

2M (f)

Φ (f)SS,mod

Φ (f)SS

mods (t)

Tsw

1/Tsw

f

==

m

x*

s(t)

t

t

t f

f

Figure C.1: Switched Signal

frequency conversion, but fast switching signals (⇒ lots of harmonics) up- or downconvert

signals or noise to unexpected frequencies.

C.2 Sampled Signals

C.3 Switched (Cyclostationary) Noise

When a wide-band signal (e.g. noise) is switched, the switching creates multiples of the

noise spectrum in the frequency domain (fig. C.2). These copies of the original noise spec-

trum will overlap when the noise bandwidth f n is larger than half the switching frequency

f sw/2 (Nyquist criterium).

modn (t)

Tsw

m(t)

wT

wT

N0

α N0

α2

w

1/Tw

2/T1/Tsw

1/Tsw

Φnn,mod

2(f)

Φnn(f)

2

2M (f)

=

x *

=

1

n(t)

t

t

f

f

f

f

ft

Figure C.2: Switched white noise, narrow pulses

The switching signal m(t ) is a rectangular signal with frequency 1/T sw and pulse width T w,




C.3 Switched (Cyclostationary) Noise 155

its duty cycle is α = T w/T sw. The power of this signal can be calculated easily in the time

domain, it is Pm

= α m2. The switching operation has no gain, so m is set to one.

m(t ) =∞

∑k =−∞

rect

t − kT sw

T w

= rect

t

T w

∞

∑k =−∞

δ (t − kT sw)

−• T w

T sw

sinc π T w f ∞

∑k =−∞

δ

f − k

T sw

=∞

∑k =−∞

α sincπ k α

.=ckk

δ

f − k

T sw

= M ( f ) (C.3.1)

The noise signal is modulated (multiplied) with m(t ) which is equivalent to a convolution in

the frequency domain (figure C.2):

Φnn,mod ( f ) = Φnn( f ) M 2( f )

= Φnn( f ) ∞

∑k =−∞

(α sincπ k α )2 δ

f − k

T sw

(C.3.2)

=∞

∑k =−∞

c2kk Φnn( f − k /T sw)

= N 0

·

∞

∑k =−∞

c2kk = N 0

·Pm for Φnn( f ) = N 0 (C.3.3)

1/Tw

wT

wT

Tsw

m(t) α2

N0

2M (f)

1/Tsw

1/Tsw

Φnn,mod

2(f)

α0

N

Φ (f)2

nn

modn (t)

=

x*

=

1

t

t

t

f

f

f

n(t)

Figure C.3: Switched white noise, wide pulses

When the noise is white with a flat spectral power density N 0, (C.3.2) can be simplified. The

remaining sum term in (C.3.3) is the sum of the squared harmonics’ amplitudes of m(t ), i.e.

it is equal to the power of the modulation signal (see eqn. E.3.1), Pm = α m2 = α . The noise

power density is simply proportional to the duty cycle α of the modulation signal (C.3.3):

v2n,out /∆ f = α · v2

n,in/∆ f where α = T w/T (C.3.4)





This is a bit suprising, one should expect that the output power is proportional to α 2. A

somewhat “hand-waving” explanation for this is: The amplitude of the harmonics of M 2( f )is proportional to α 2. However, with increasing α the first zero of the sinc2( x) at 1/T w moves

down in frequency and the high frequency content of M 2( f ) is reduced. For white noise with

unlimited bandwidth, the resulting total noise power is proportional to α .

α2

modn (t)

m(t)Tsw

wT

wT

w1/T

w2/T1/Tsw

N0

2M (f)

fn

1/Tsw

Φnn,mod

2(f)

Φnn(f)

2

=

x

*

=

n(t)

1

f

f

f

t

t

t

Figure C.4: Switched bandlimited noise, narrow pulses α 1

When the noise has a limited bandwidth Bn, things become more complicated: Every dirac

pulse in the frequency domain in (C.3.2) corresponds to a line in the spectrum of the mod-

ulation signal (frequency and magnitude). Every spectral line folds noise, i.e. shifts a copy

of the noise in frequency and adds it to the total output noise, multiplied by its weight (the

magnitude of the corresponding spectral line) (see figure C.4, thin lines in Φ2nn,mod are the

contributions of each spectral line). This mechanism is explained very well in [GT86, p.508-

510], though for the case of sample & hold. An integrating loop filter does not sample the

noise, therefore, results cannot be compared directly.

α2

w2/T

w1/T

N0

wT

wT

Tsw

Φ (f)2

nn1/Tsw

Nα2

0

1/Tsw

fn

m(t)

modn (t) Φnn,mod

2(f)

2M (f)

=

x*

=

1

t

t

n(t)f

f

f

t

Figure C.5: Switched bandlimited noise, wide pulses




C.3 Switched (Cyclostationary) Noise 157

A rule of the thumb can be constructed as follows: Usually, the bandwidth of interest is

the “base band” 0 . . . f sw

/2, higher frequencies are filtered out by the loop filter. Due to

the switching of the input noise spectrum, copies of the spectrum are generated at higher

frequencies. The number of input noise bands folded back into the base band depends on the

ratio of the input noise bandwidth Bn and switching frequency f sw: A number of 2 Bn/ f sw

copies of the input noise spectrum is folded back into the base band. The multiplication

factor for each noise band is given by (α sincπ k α )2. As the sinc2( x) function drops to

zero quite fast, the harmonics beyond 1/T w will be neglected. This means, a number of

(1/T w)/(1/T sw) = 1/α harmonics contribute to noise folding with an constant (very rough

approximation) amplitude of α 2, the rest is neglected. This crude approximation allows easy

calculation. The total noise power density in the base band is approximately

Φ2nn,mod ≈ α 2 N 0 ·min2 Bn

f sw

, 1α with α = T w

T sw

(C.3.5)

≈

α N 0 for 2 BnT w > 1 (a)

α 2 N 0 ·2 Bn/ f re f for 2 BnT w < 1 (b)

α 2 N 0 for Bn < f sw/2 (c)

The meaning of this is best seen with some extreme cases:

White Noise / Very Wide Noise Bandwidth (C.3.6a): When the input noise has very wide

input bandwidth, lots of noise is folded back into the baseband (fig. C.2). 1/α is smallerthan 2 Bn/ f sw or, regrouped, 2 BnT w > 1. The resulting noise power density is α N 0, as already

shown in (C.3.4).

Wide Pulses (Type 2 phase detector, C.3.6a): For wide pulses, 1/α usually also is smaller

than 2 Bn/ f sw and 2 BnT w > 1. When, for example, T w = 1/2T sw, α = 1/2 (fig. C.3), the

harmonics of M 2( f ) are attenuated quite strongly (p.ex. the harmonic at 2 f sw is completely

suppressed, the one at 3 f sw only has a magnitude of (0.21)2, i.e. there is not much folding

back of noise. For this reason, limiting the input noise bandwidth in this case has not much

effect on the total output noise power - the output noise density becomes α N 0.

Very Short Pulses (ABL pulses in locked state, C.3.6b): A Type II PLL (integrating loop

filter) in locked state produces only very short pulses (compared to T sw). This means, that

the frequency of the first zero of the sinc(x) function is at a very high frequency and the first

harmonics of M ( f ) have approximately constant magnitude α 2. The input noise bandwidth

directly influences the output noise spectrum - the wider Bn, the more copies of the input noise

are added on top of each other (fig. C.4) and the output noise density becomes α 2 N 0 ·2 Bn/ f sw.

Very Narrow Noise Bandwidth (C.3.6c): When the noise bandwidth is limited to less than

half the switching frequency (this could be realized in a system with a high reference fre-

quency, e.g. a Fractional-N Synthesizer), Bn < f sw/2, every spectral line folds a copy of the

noise around itself, but the resulting noise bands do not overlap (fig. C.5). The total baseband

noise density is simply the input noise density scaled with α 2, i.e. α 2 N 0. As a rule of the

thumb, the effect of downsampling can be ignored if Φnn ( f − f sw/2) Φnn ( f ) by at least

10 dB.

EXAMPLE 18: Charge Pump Noise





Using the same data as in the last examples, K φ = 0.5mA/ π rad, K vco = 40

MHz/V, N = 70, f sw = 13MHz. The noise current density is in,CP = 20pA/

√Hzinto a non-integrating loop filter with Rin = 8.2k Ω / into an integrating loop fil-

ter with C ∗1 = 13.5nF. In locked state, the PLL with non-integrating loop-filter

produces pulses at the output with a duty cycle of 50% (α = 0.5). The PLL

with integrating loop filter only produces very short anti-deadzone pulses with

T w = T ABL = 2ns (α = 0.02).

Assuming that the noise is wide bandwidth, the resulting output noise spectral

density is determined by the modulation duty cycle α . With the non-integrating

loop filter, the phase detector noise current density is

i2n,det ( f ) = α · i2

n,CP( f ) = 2.0 ·10−22A2/Hz

and for the integrating loop filter:

i2n,det ( f ) = α · i2

n,CP( f ) = 8.0 ·10−24A2/Hz

The resulting noise current at the phase detector v2n,det ( f ) has to be multiplied

with thenoise transfer function (10.2.11), giving an output noise spectrum within

the loop bandwidth of

∆φ 2O( f ) ≈ i2n,det ( f )

N

K φ 2

=

3.88 ·10−11rad2/Hz = −104dBc/Hz for n.i. LF

1.55·10

−12rad2/Hz =

−118dBc/Hz for int. LF

Outside the loop bandwidth, the output noise spectrum is:

∆φ 2O( f ) ≈ i2n,det ( f )

K VCO

jω F ( jω )

2

=

xxxrad2/Hz = − xxxdBc/Hz for n.i. LF

xxxrad2/Hz = − xxxdBc/Hz for int. LF

The single-sideband phase noise L ( f ) has half the magnitude, i.e. 3dB have to

be subtracted from the values above.

C.4 Intermodulation of Two Frequencies

When a signal containing two frequencies is put through a non-linear stage, new frequency

components will be generated. This process is called intermodulation. Let’s assume a stage

with linear gain and square and cubic distortion terms:

F ( x) = a1 · x + a2 · x2 + a3 · x3

A signal containing the two frequencies f 1 and f 2 is processed by this stage:

x = A1 cos(ω 1t ) + A2 cos(ω 2t )

The output signal will show many new frequency components:




C.5 Clipped Signals 159

F ( x) = a1 ( A1 cosω 1t + A2 cosω 2t ) linear gain

+ a2 ( A1 cosω 1t + A2 cosω 2t )2 quadratic distortion

+

a3 ( A1 cosω 1t + A2 cosω 2t )3 cubic distortion

= a1 A1 cosω 1t + a1 A2 cosω 2t +

a2

A2

1 cos2ω 1t + A22 cos2ω 2t + 2 A1 A2 cosω 1t cosω 2t

+

a3

A3

1 cos3ω 1t + A32 cos3ω 2t + 3 A1 A2

cos2ω 1t cosω 2t + cosω 1t cos2ω 2t

= a1 A1 cosω 1t + a1 A2 cosω 2t +

a2

2 A2

1 (1 + cos2ω 1t ) + A22 (1 + cos2ω 2t ) + 2 A1 A2 (cos(ω 1 −ω 2) t + cos(ω 1 +ω 2) t )

+

a3

4 A31 (3cosω 1t + cos3ω 1t ) + A32 (3cosω 2t + cos3ω 2t )+

3

2a3 A1 A2 [(1 + cos2ω 1t )cosω 2t + cosω 1t (1 + cos2ω 2t )]

=

a1 A1 +

3

2a3 A1 A2 +

3a3

8A3

1

cosω 1t +

a1 A2 +

3

2a3 A1 A2 +

3a3

8A3

1

cosω 2t

original f requencies

+

a2

2

A2

1 + A22

DC

+a2

2

A2

1 cos2ω 1t + A22 cos2ω 2t

second harmonic

+a3

4

A3

1 cos3ω 1t + A32 cos3ω 2t

third harmonic

+

a2 A1 A2 cos(ω 1 ±ω 2) t

1st order mix products

+3a3

4A1 A2 [cos(2ω 1 ±ω 2) t + cos(2ω 2 ±ω 1) t ]

2nd order mix products

(C.4.1)

Even in this simple example the output signal contains new components at DC, 2ω 1 and 2ω 2,

3ω 1 and 3ω 2, mixed components at ω 1 ±ω 2, 2ω 1 ±ω 2 and ω 1 ± 2ω 2.

C.5 Clipped Signals

Signal clipping can occur as an unwanted effect when the maximum output swing of a linear

stage is exceeded. On the other hand, analog signals often are limited deliberately to elimi-

nate amplitude noise for circuitry that only uses the timing / phase information. Limiting can

be approximated by putting the signal through a strongly non-linear function with limiting

behaviour like arctan( x) (

−π /2 . . .π /2) or tanh( x) (

−1 . . .1).

Inspite of clipping, an amplitude disturbance will create some phase or timing error. How

large that error is depends on the slew rate of the signal and the amplitude of the disturbance:

When a sum of two signals passes through a non-linear stage, there will be intermodulation,

i.e. the generation of new frequency components. Clipping is just a special form of a non-

linear stage, therefore the results from the last section can be used:




Appendix D

FM / PM Signals

Any sufficiently advanced

technology is indistinguishable from

magic.

Arthur C. Clarke

- — General BlaBla —

D.1 Sinusoidal Modulation Signals

A sinusoidal signal of amplitude A and frequency ω 0 that is phase modulated by another

sinusoidal signal of frequency ω 1 and amplitude µ can be expanded into an infinite sum of

cosine signals, each weighted with a Bessel function (see G.2) [Luk85, p. 232-235]. The

parameter µ = ∆ f / f 1 is called modulation index:

sFM (t ) = A cos(ω 0t +µ sin(ω 1t +φ 1))

= A∞

∑n=−∞

J n(µ )cos(ω 0t + n (ω 1t +φ 1)) (D.1.1)

This signal has a spectrum that is symmetrical around the carrier with frequency f 0 and am-

plitude J 0(µ ) (fig. D.1). The spurious sidebands have relative amplitudes of J n(µ ) at offsetsfrom the carrier of ±n f 1. This means, a modulating signal with a single frequency produces

lots of spurious sidebands due to the non-linearity of frequency modulation.

(D.1.1) has a magnitude spectrum of

|SFM ( f )| = A∞

∑n=−∞

| J n(µ )|δ ( f − f 0 − n f 1) (D.1.2)

For small modulation signals µ 1, the higher order Bessel terms decrease rapidly; the first

terms can be approximated by: J 0(µ ) ≈ 1, J ±1(µ ) ≈ ±µ /2, J ±2(µ ) ≈ µ 2/8. Often, it is

sufficient to look at the zero and 1st order terms, i.e. carrier and first sidebands, and (D.1.1)

can be rewritten as

sFM (t ) ≈ A−µ

2cos(ω 0t −ω 1t −φ 1) + cosω 0t +

µ

2cos(ω 0t +ω 1t +φ 1)

(D.1.3)

161



162 FM / PM Signals

In the frequency domain, this corresponds to

|SFM ( f )| = Aµ

2δ ( f − f 0 + f 1) +δ ( f − f 0) + µ

2δ ( f − f 0 − f 1)

(D.1.4)

This case is called Narrow Band FM Approximation1 or Low Modulation Index Approxima-

tion.

fc

1/f m2 1/f m1

S (f)FM

m1+f+fm2

+fm2m1+f

0f + f∆

0 1f + f∆

0f + f∆3

0f + f∆2

f0

f0

f0

f (t)FM

1/f m1+2f

m1m1+f

ft

t fa)

b)

Figure D.1: Instant Frequency and Spectra of FM Modulated Signals

Fig. D.1 shows momentary frequency and spectra of signals that have been FM modulated by

sinusoids. The upper figure shows what happens when the amplitude of a modulation signal

with frequency f m is increased: the instant frequency deviation ∆ f is increased by the same

amount. For a small modulation amplitude (= low modulation index), the modulation will

produce only two sidebands in the spectrum around the carrier at an offset of ± f m. Their

level will increase proportionally with the modulation amplitude. At higher modulation am-

plitudes this relationship becomes non-linear and higher order sidebands at ±k f m will appear

as predicted by (D.1.1).

The lower part of the figure shows the effect of varying the modulation frequency: doubling

the modulation frequency at the same modulation amplitude decreases the modulation index:

in the spectrum, the sidebands appear at twice the offset with half the level.

D.2 Periodic Modulation Signals

Due to the non-linearities of phase / frequency modulation,

Let’s first look at two sinusoids interfering with the tune voltage ve(t ) = m1 cosω 1t +m2 cosω 2t .

At the VCO output they create an phase error of

∆φ e(t ) = 2π K vco

t

−∞m1 cosω 1τ + m2 cosω 2τ d τ

=m1K vco

f 1sinω 1t +

m2K vco

f 2sinω 2t +φ 0

= µ 1 sinω 1t +µ 2 sinω 2t +φ 0 where µ i = miK vco/ f i (D.2.1)1No excess bandwidth compared to amplitude modulation is needed as in the case of high modulation indices




D.2 Periodic Modulation Signals 163

We see that the integrating behavior of the VCO attenuates the signal with the higher fre-

quency and also creates a phase shift of 90 deg. but there are no distortions. In the frequency

domain, things are different: applying a power series approximation, neglecting terms of 3rd

order and higher and using some trignometric identities gives the following results

svco(t ) = A cos(ω 0t + ∆φ e(t ))

= A cos(ω 0t +µ 1 sinω 1t +µ 2 sinω 2t )

= A cos(ω 0t )cos(µ 1 sinω 1t +µ 2 sinω 2t )

− A sin(ω 0t )sin(µ 1 sinω 1t +µ 2 sinω 2t )

≈ A cos(ω 0t )

1− 1

2(µ 1 sinω 1t +µ 2 sinω 2t )2

− A sin(ω 0t )µ 1 sinω 1t +µ 2 sinω 2t −1

6 (µ 1 sinω 1t +µ 2 sinω 2t )3

≈ A cos(ω 0t )

1− 1

2

µ 21 sin2ω 1t +µ 22 sin2ω 2t + 2µ 1µ 2 sinω 1t sinω 2t

− A sin(ω 0t ) (µ 1 sinω 1t +µ 2 sinω 2t )

= Acos(ω 0t ) +

µ 12

cos(ω 0t ±ω 1t ) +µ 22

cos(ω 0t ±ω 2t )

−cos(ω 0t )

µ 214

(1− cos2ω 1t ) +µ 224

(1− cos2ω 2t ) +µ 1µ 2

4cos(ω 1t ±ω 2t )

= A

cos(ω 0t )

1− µ 21 +µ 22

4

+

µ 12

cos(ω 0t ±ω 1t ) +µ 22

cos(ω 0t ±ω 2t )

+µ 2

18

cos(ω 0t ±2ω 1t ) + µ 2

28

cos(ω 0t ± 2ω 2t ) + µ 1µ 28

cos(ω 0t ±ω 1t ±ω 2t )(D.2.2)

The result shows a whole bunch of sidebands - the ones at offsets of ±ω 1 and ±ω 2 are the

linear terms, additionally the second harmonic of the modulation tones appears at ±2ω 1 resp.

±2ω 2 and there is intermodulation as well, giving sidebands at ±(ω 1 ±ω 2). Higher order

terms do not appear

A periodic signal ve(t ) with a fundamental frequency f 1 can be decomposed into an infinite

Fourier series:

ve(t ) = c0 +∞

∑k =1


where ck is the amplitude of the k-th harmonic and φ k is its phase. It has been assumed, thatve(t ) is DC-free (see page 11), i.e. c0 = 0. ve(t ) creates a phase modulation of

∆φ e(t ) = 2π K vco

t

−∞ve(τ ) d τ = 2π K vco

t

−∞

∞

∑k =1

ck cos(k ω 1τ +φ k ) d τ

= 2π K vco

∞

∑k =1

ck

k ω 1sin(k ω 1t +φ k ) +C k

=∞

∑k =1

K vcock

k f 1sin(k ω 1t +φ k )

=∞

∑k =1

µ k sin(k ω 1t +φ k ) where µ k =K vcock

k f 1(D.2.3)

The integration constants ∑C k have been dropped (see G.5) - they only cause static phase /

frequency changes which are compensated by the locked loop. µ k is the modulation index for




164 FM / PM Signals

the k-th harmonic of the modulation signal. For small periodic modulating signals (µ < 0.01),

narrowband FM approximation (6.2.2) can be used. This allows superposing the modulating

effect of each harmonic2:

svco(t ) = A cos(ω 0t + ∆φ e(t ))

= A cos

ω 0t +

∞

∑k =1

µ k sin(k ω 1t +φ k )

≈ A

cosω 0t +

∞

∑k =1

µ k

2(cos(ω 0t + (k ω 1t +φ k )) − cos(ω 0t − (k ω 1t +φ k )))

(D.2.4)

i.e. each harmonic of the modulating signal is upconverted around the carrier and attentuated

by 1/k f 1 due to the integrating behaviour of the VCO. This signal has a magnitude spectrum

density of:

|SFM ( f )| ≈ A

δ ( f − f 0) +

∞

∑k =1

µ k

2(δ ( f − f 0 + k f 1)) +δ ( f − f 0 − k f 1))

(D.2.5)

D.3 Phase / Frequency Shift Keying

Phase / Frequency Shift Keying are special cases of periodical modulation signals - the signal

phase resp. frequency are modulated with a rectangular signal. The instant phase / frequency

is calculated easily but cannot be measured. The measurement process always takes some

kind of averaging and filtering which must be specified in order to interpret the results.

D.4 Statistical Modulation Signals

Similiar to the last section D.2, the modulation with a non-periodic signal vn(t ) (e.g. noise)

can be analysed in the frequency domain. vn(t ) creates a phase modulation of:

φ n(t ) = 2π K vco

t

−∞vn(τ ) d τ

The effect of this phase modulation can be calculated with the help of its Fourier integral:

Φnn(t ) = F

2π K vco

t

−∞vn(τ ) d τ

= 2π K vco

V nn( f )

j2π f = K vco

V nn( f )

j f (D.4.1)

It has been assumed, that vn(t ) is DC-free, i.e. V nn( f ) = 0. The resulting VCO output signalis calculated using the inverse Fourier transforms (A.2.1) and (A.2.3):

svco(t ) = A cos(ω 0t +φ n(t ))

= A cosω 0t +F−1 Φnn( f )

= A cos

ω 0t + K vco F

−1

V nn( f )

j f

= A cos

ω 0t + K vco

∞

−∞

V nn( f )

j f

e j2π f t d f

= A cosω 0t + 2π K vco ∞

−∞ReF

t

−∞

vn(τ ) d τ cos2π ft d f (D.4.2)

2In general, it would not be possible to use this approach - frequency modulation is a non-linear operation,

therefore the superposition principle is not valid.




D.4 Statistical Modulation Signals 165

See also [Gar79, pp. 25-31, 100-105].




166 FM / PM Signals




Appendix E

Signal Energy and Power

E.1 The Basics: Energy

A signal s can be described in the time or in the frequency domain, but the energy of the

signal must be the same in both domains:

E =

∞

−∞s2(t )dt = φ E

SS(0) =

∞

0|S E ( f )|2d f (E.1.1)

(Parseval’s Theorem) where φ E SS(0) is the impulse or energy auto correlation function (ACF):

φ E SS(τ )

.=

∞

−∞

s(t )s(t +τ ) dt (E.1.2)

The Fourier transform of φ E SS(τ ) is the energy density spectrum |S E ( f )|2 [Luk85, p. 82]:

φ E SS(τ ) = s(−τ ) ∗ s(τ ) −• = S∗( f ) · S( f ) = |S E ( f )|2 (E.1.3)

This equation is the Wiener-Khinchine Theorem for energy signals. It shows that the ACF of

a signal can be calculated from the magnitude spectrum of its Fourier transform alone, the

phase spectrum is not needed. This is especially important for random processes where the

phase spectrum is difficult or impossible to determine (spectrum analyzers only measure the

magnitude spectrum) - see next section.

E.2 The Basics: Power

Signals with infinite energy (periodic signals or infinite statistical processes) must be charac-

terized by their power (squared time average or energy per time) instead of their energy:

P = s2(t ) = limT →∞

1

2T

T

−T s2(t )dt (E.2.1)

Here, “power” is used with the definition of system theory, i.e. the square of a signal. Usually,

a real physical power can be obtained by multiplying or dividing this value with a constant.

When the signal is e.g. a voltage, divide by the impedance to get the power.

The direct Fourier transform of statistical processes is not defined - but it is possible to cal-

culate the Fourier transform of the process’ ACF (E.2.2)

φ SS(τ ) = s(t )s(t +τ ) = limT →∞

1

2T

T

−T s(t )s(t +τ )dt (E.2.2)

167



168 Signal Energy and Power

φ SS(τ ) is the power auto correlation function (ACF) which is defined per time. Note that the

ACF of energy (E.1.2) and power signals (E.2.2) are defined differently [Luk85, p. 131]. The

Fourier transform of φ SS(τ ) reveals the spectral properties of the process:

φ SS(τ ) −• ΦSS( f ) =S2( f )

(E.2.3)

ΦSS( f ) is the power spectral density of the signal/process with the unit power per frequency,

it can be measured using e.g. a spectrum analyzer. (E.2.3) is the actual Wiener-Khinchine

Theorem, it is very important for calculating / measuring the power of statistical processes.

Similiar to Parseval’s Theorem (E.1.1), signal power can be calculated in the time domain

(E.2.1) or in the frequency domain via its ACF (E.2.4), whatever comes more handy:

P = φ SS(0) = ∞

−∞

ΦSS( f )d f (E.2.4)

For T 1-periodical signals or T 1-cyclostationary processes, (E.2.1) and (E.2.2) can be simpli-

fied:

P =1

T 1

T 1

0s2(t )dt (E.2.5)

φ SS(τ ) =1

T 1

T 1

0s(t )s(t +τ )dt with 0 ≤ τ ≤ T 1 (E.2.6)

E.3 Power of a Periodic Signal

The two ways for calculating signal power will be demonstrated once more:

E.3.1 Calculation of Signal Power in the Time Domain

The power of a sinusoidal signal s(t ) = Acosω 1t is calculated using (E.2.5):

P =A2

T 1

T 1

0cos2(ω 1t )dt

=A2

T 1

t

2+

1

4ω 1sin2ω 1t

T 1

0

=A2

T 1· T 1

2=

A2

2

as expected. A phase shift in the signal doesn’t change the power, therefore this result can be

applied to any sinusoidal signal.

The power of a general periodic signal with period T 1 can be calculated by expanding the

signal into a Fourier series s(t ) = c0 + ∑∞k =1 ck cos(k ω 1t +φ k ) using (E.2.5) and (A.4.12):

P =1

T 1

T 1

0

c0 +

∞

∑k =1


2

dt

=1

T 1

T 1

0c2

0 +∞

∑k =1

c2k cos2 (k ω 1t ) dt

= c20 +

∞

∑k =1

c2k

2

(E.3.1)

because the cosine terms in the Fourier series are orthogonal, i.e. for k , l = 0,1,2, . . .




E.4 Power of Statistical Processes 169

1

T 1 T 1

0cos(k ω 1t +φ k )cos(lω 1t +φ l ) dt = 0 for

|k

| =

|l

|12

for |k | = |l| (E.3.2)

When the signal is a pure sinusoid, all Fourier coefficients are zero except for c1 = A. In this

case, (E.3.1) again gives a power of A2/2.

E.3.2 Calculation of Signal Power from the Auto-Correlation Function

The power spectral density of a periodic signal is calculated via its ACF (E.2.6):

φ SS(τ ) =1

T 1 T 1

0s(t )s(t +τ ) dt with 0 ≤ τ ≤ T 1

=1

T 1

T 1

0

c0 +

∞

∑k =1


c0 +

∞

∑l=1

cl cos(lω 1t + lω 1τ +φ l)

dt

=1

T 1

T 1

0

c2

0 +∞

∑k =1

c2k cos(k ω 1t +φ k )cos(k ω 1t + k ω 1τ +φ k )

dt

= c20 +

1

T 1

∞

∑k =1

c2k

2

T 1

0cos(k ω 1τ )

...=cos(...)·t

+cos(2k ω 1t + 2φ k +τ ) ...=0

dt

= c20 +

∞

∑k =1

c2k

2·cos(k ω 1τ ) (E.3.3)

Again, the product of the sum of cosine terms was simplified by using the orthogonality of

the cosine functions (E.3.2). The remaining sum of products was further simplified by using

the trignonometric theorem (G.3.8). The total power of the signal is easily calculated from

its ACF (E.3.3):

P = φ SS(0) = c20 +

∞

∑k =1

c2k

2(E.3.4)

which is identical to (E.3.1).

E.3.3 Calculation of Signal Power in the Frequency Domain

Taking the Fourier transform of the ACF (E.3.3) gives the power spectral density:

S2( f ) = ΦSS( f ) = F(φ SS(τ )) = c2

0δ (0) +∞

∑k =1

c2k

2δ ( f − k f 1) with f ≥ 0 (E.3.5)

Using Parseval’s theorem (E.1.1) with (E.3.5) allows the calculation of the signal power in

the frequency domain by integratingS2( f )

over the whole frequency range. The result is

again identical to (E.3.1).

E.4 Power of Statistical Processes

A statistical process n(t ) can be described by its statistical properties (average, standard de-

viation etc.) or by the power spectral density Φnn( f ) of its autocorrelation function φ nn(τ ).

The power can be calculated both ways:





Equation (E.2.1) allows calculating the signal power of a statistical process with gaussian

amplitude distribution:

Pn = n2(t ) = limT →∞

1

2T

T

−T n2(t )dt = m2 +σ 2n = m2 + var (n(t )) (E.4.1)

where m is the average (DC), σ n the standard deviation and var the variance of n(t ).

For the case of time-discrete processes, the formula looks very similiar:

Pn = s2(n) =1

N − 1

N

∑n=1

s2(n) = m2 +σ 2n = m2 + var (n(t )) (E.4.2)

In the frequency domain, the power spectral density of the auto correlation function, Φnn( f ),

is used to calculate the power:

Pn =

∞

−∞Φnn( f )d f (E.4.3)

If the power spectral density of white noise really was constant, Φnn( f ) = N 0, its total noise

power would be infinite. In reality, all processes have a limited bandwidth, even the thermal

noise itself is low-pass limited by the atomic motion to ca. 1013Hz.

Note: Another measure is phase noise L ( f ): The concept of phase noise is used for systems

with a fixed frequency and little amplitude noise contribution, i.e. nearly all the noise power

is caused by random phase modulation ∆φ (t ), i.e. Pn = Pn, A + Pn,φ ≈ Pn,φ . Examples for

this are oscillators (amplitude noise is suppressed by regulating or limiting the amplitude) or

digital signals (clipped amplitude):

s(t ) = A cos(ω 0t + ∆φ (t ))

E.5 Power of FM / PM Modulated Signals

The total power of a FM / PM modulated signal can be calculated easily: it is independent

of the modulation because the amplitude stays constant. FM / PM modulation “smears” the

power over a broader frequency range or several discrete frequency lines. Usually, one is

interested in the spectral power density of this modulation spectrum (wanted or unwanted).

The power spectral density of a frequency modulated signal can be calculated like that of a

“normal” periodic signal (E.3.5) for two special cases: for sinusoidal modulation (D.1.1) orfor low modulation indices (narrowband case) (D.2.4) when the non-linear frequency modu-

lation can be linearized.

Sinusoidal Modulation

When a sinusoidal signal with amplitude m and frequency f 1 modulates a VCO with gain

K vco, the resulting FM signal has a modulation index of µ = K vcom/ f 1 and can be written as

(D.1.1):

sFM (t ) = A∞

∑k =−∞

J k (µ )cos(ω 0t + k (ω 1t +φ 1))

with a power spectral density of




E.5 Power of FM / PM Modulated Signals 171

S2FM ( f )=

A2

2

∞

∑k =−∞ J

2k (µ ) (δ ( f − f 0 − k f 1) +δ ( f + f 0 + k f 1)) (E.5.1)

This can be shown by calculating the ACF as in (E.3.3). Again, the cosine functions are

orthogonal when integrating over a period of T 1. The total power of this signal is

P =A2

2J 20 (µ )

carrier

+ A2∞

∑k =1

J 2k (µ ) modulation

≈ A2

2+

A2

4µ 2 (E.5.2)

Obviously, this approximation is not quite true: A2/2 is the power of the unmodulated carrier,

some of its power must be shifted to the modulation. Still, the term A2/4 · µ 2 is a useful

approximation for the modulation power.

Harmonic Signal Modulation with a Low Modulation Index

The low-modulation index case looks similiar: when a periodical signal with Fourier co-

efficients ck and base frequency f 1 modulates a VCO, the resulting FM signal (with low-

modulation indices µ k ) can be written as (D.2.4)

sFM (t ) ≈ A

cosω 0t +

∞

∑k =1

µ k

2(cos(ω 0t + (k ω 1t +φ k )) − cos(ω 0t − (k ω 1t +φ k )))

where µ k =K vcock

k f 1

and has a PSD of

S2FM ( f )

=A2

2

δ ( f − f 0) +

∞

∑k =1

µ 2k

2(δ ( f − f 0 − k f 1) +δ ( f + f 0 + k f 1))

(E.5.3)

The total power of this signal is:

P ≈ A2

2 carrier

+A2

2

∞

∑k =1

µ 2k modulation

=A2

2+

1

2

AK vco

f 1

2 ∞

∑k =1

c2k

k 2(E.5.4)

Modulation by Noise

Carrier and noise power of a carrier with weak phase modulation can be calculated with theapproximations sin(∆φ (t )) ≈ ∆φ (t ) and cos(∆φ (t )) ≈ 1 (where ∆φ is given in rad):

s(t ) = Acos(ω 0t + ∆φ (t ))

= Acosω 0t cos(∆φ (t )) − Asinω 0t sin(∆φ (t ))

≈ A (cosω 0t − sin(ω 0t ) ·∆φ (t )) (E.5.5)

The power of this signal is:

P =A2

T 0

T 0

0cos2ω 0t

T 0/2

−2cosω 0t sinω 0t ∆φ (t )

=0

+sin2ω 0t ∆φ 2(t ) dt

=A2

2

1 +

1

T 0

T 0

0∆φ 2(t ) dt

= PC + P N (E.5.6)





where PC = A2/2 is the power of the carrier and P N is the noise power. The noise to signal

ratio is equal to the RMS phase error:

P N

PC

=1

T 0

T 0

0∆φ 2(t ) dt = φ 2rms (E.5.7)

In the frequency domain, phase noise L ( f ) is defined as the relative (i.e. referred to the

carrier) spectral power per sideband at an offset f from the carrier, assuming that there is no

noise power due to amplitude modulation. In this case, phase noise is defined simply as

L ( f ) =1

2

Φnn( f )

PC

(E.5.8)

where PC is the carrier power and the factor 1/2 comes from using only one sideband.




Appendix F

Second Order (PT2)

Approximation

Suche das einfachste Gesetz, das mit

den Fakten harmoniert.

Ludwig Wittgenstein

F.1 Basic PT2 SystemMany real world control system can be approximated by second order systems, i.e. systems

whose transfer function contains two poles. The idea is to ignore the higher poles: As a rule-

of-thumb, the response of a third-order system can be approximated by the dominant roots of

the second-order system as long as the real part of the dominant roots is less than 110

of the

real part of the third root [Dor92, p. 166]. Put into simpler words: the higher order poles have

to be so far up in frequency that they do not have significant influence on the phase margin

etc. The advantage of second order systems is that they can be treated analytically without

too much hassle, important characteristics like bandwidth, settling time, amount of peaking

etc. can be easily extracted [Dor92, pp. 45 - 52, 161 - 168, 313 - 316]. Therefore, it’s worth

looking at second order systems in greater detail. A general description for a second order

system is given by:

C (s) =ω 2n

s2 + 2ζω ns +ω 2n=

1

s2/ω 2n + 2 (ζ /ω n) s + 1(F.1.1)

=ω 2n

s +ζω n + ζ 2 −1 ω n

s +ζω n −

ζ 2 −1 ω n

(F.1.2)

= −ω n

2√

ζ 2−1

s +ζω n + ζ 2 − 1 ω n

+

ω n

2√

ζ 2−1

s +ζω n − ζ 2 −1 ω n

(F.1.3)

(F.1.1) is the s-plane representation of the closed-loop transfer function of a second-order

system (two poles, no zero). ω n (unit: rad/s) is the natural frequency and ζ (dimensionless)

is called damping ratio. The meaning of these terms will become clear when looking at the

173



174 Second Order (PT2) Approximation

ωn

j

ωj

ζ = 1

ζ > 1

ζ < 1

ζ = 0

0

ζ = 0

σ

ζ > 1

Figure F.1: Root locus plot of C (s) as ζ varies with constant ω n

transient step response of the system (F.1.4). The characteristic equation (i.e. the denominator

of C (s)) is factored (F.1.2) to find its two roots which are the poles of the system. Applying

partial fraction expansion (F.1.3) makes it easier to find the transient response of the system

by applying inverse Laplace transform.

c(t ) =

ω n sin(ω nt ) for ζ = 0

ω ne−ζω nt 1−ζ 2

sin

1−ζ 2 ω nt

for 0 < ζ < 1

ω ne−ω nt for ζ = 1

ω n

2 ζ 2 −1

e−ω n

ζ −

√ζ 2−1

t − e

−ω n

ζ +

√ζ 2−1

t

for ζ > 1

(F.1.4)

where θ .

= arccosζ . The transient behaviour (F.1.4) depends strongly on the damping ratio ζ :

Undamped oscillation: ζ = 0

The two poles of C (s), s1,2 =

± jω n, sit on the imaginary axis (fig. F.1) and the system oscil-

lates without damping at the frequency ω n.

Underdamped system: 0 < ζ < 1

Increasing the damping ratio ζ gives an underdamped system with conjugate complex poles

s1,2 = −ζ nω n ± jω n

1−ζ 2 for 0 < ζ < 1

Increasing ζ lets the poles wander towards the negative real axis on an arc. In the time do-

main, this corresponds to an increasingly exponentially damped sinusoidal signal response

with a ringing frequency of ω n

1−ζ 2 (fig. 2.8).

Critically damped system: ζ = 1

For ζ = 1 the two poles meet on the real axis; the impulse response is an exponential decay

with one time constant.




F.2 PT2 System with a Zero 175

Overcritically damped system: ζ > 1

ζ > 1 gives two real poles,

s1,2 = −ω n

ζ ±

ζ 2 −1

for ζ ≥ 1

the system is overdamped ; its impulse response is an exponential decay (no ringing) with two

time constants.

Integrating the impulse response (F.1.4) gives the step response cε (t ) (F.1.5). Alternatively,

C (s) (F.1.1) can be multiplied by 1/s before calculating the inverse Laplace transform.

cε (t ) =

1− sin(ω nt ) for ζ = 0

1− e−ζω nt 1−ζ 2

sin

1− ζ 2 ω nt +θ

for 0 < ζ < 1

ω n

2 ζ 2 −1

e−ω n

ζ −

√ζ 2−1

t − e

−ω n

ζ +

√ζ 2−1

t

for ζ ≥ 1

(F.1.5)

[Lee98, p.413 f] collects some useful approximations for second order systems with 0 < ζ <1.

F.2 PT2 System with a Zero




176 Second Order (PT2) Approximation




Appendix G

Bits and Pieces

G.1 Normal Distribution and Error Function

−200 0 200 400 600 800 10001

2

3

4

5

6

7

8

9

m = 5, σ = 1

−3σ

+3σ

A m p

l i t u d e

[ V ]

time (s)

Signal with normal distribution and its PDF

1

2

3

4

5

6

7

8

9

P r o

b a

b i l i t y D e n s

i t y ( B i n )

Figure G.1: PDF of random process with Gaussian distribution

Many naturally occurring random processes (resistor noise, antenna noise etc.) can be de-

scribed by a Gaussian amplitude distribution (fig. G.1. The Gaussian Distribution or Normal

Distribution ps,G( x) describes the probability density function of such a random process s:

ps,G( x) =1√

2πσ 2e

−( x−m)2

2σ 2 (G.1.1)

It is completely defined by its mean value m and its standard deviation σ (see Fig. G.2).

177



178 Bits and Pieces

−10 −8 −6 −4 −2 0 2 4 6 8 100

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

x

p s , G

( x )

σ = 3

σ = 1

m = 2

Figure G.2: Gaussian Distribution for m=2 and σ = 1 / σ = 3

The total area under the Gaussian distribution is always 1. Due to symmetry reasons, the

area between −∞ and m is 1/2. Taking the integral Ps,G( x) of the probability density function

ps,G( z) from −∞ to x gives the probability that the process s is below the limit x:

Ps,G( x) =

x

−∞ ps,G( z) dz =

1√2πσ 2

x

−∞e

−( z−m)2

2σ 2 dz (G.1.2)

=1

2+

1√2πσ 2

x

me

−( z−m)2

2σ 2 dz (G.1.3)

This integral cannot be solved in closed form, but the integral of the normalized and centered

Gaussian distribution p0,g( x) (m = 0, σ = 1), the so-called Gaussian Error Integral P0,G( x)can be found in mathematical tables [BS81, pp. 18ff]:

P0,G( x) = x

−∞

p0,G( z) dz

=1√2π

x

−∞e

− z2

2 dz =1

2+

1√2π

x

0e

− z2

2 dz (G.1.4)

=1

2+

1

2erf

x√2

Alternatively, the so-called Error Function, erf(x), is found in books. The Error Function is

twice the Gaussian integral with m = 0 and σ = 1/√

2 (see Fig. G.3):

erf ( x) =2√π

x

0e− z2

dz (G.1.5)

= 2P0,G√

2 x−1

=2√π

x − x3

3 ·1!+

x5

5 ·2!− x7

7 ·3!· · ·




G.1 Normal Distribution and Error Function 179

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

x

e r f ( x

)

Figure G.3: Error Function erf(x)

The Complementary Error Function, erfc(x), is quite commonly used to describe the proba-

bility of a process to be above or outside a limit x:

erfc( x) = 2√π ∞

xe− z

2

dz = 1− erf ( x) (G.1.6)

Using the definitions of (G.1.4) and (G.1.5), (G.1.2) can be reformulated:

Ps,G( x) = P0,G

x − m

σ

(G.1.7)

=1

2erfc

x − m√

2σ

=

1

2+

1

2erf

x − m√

2σ

EXAMPLE 19: Thermal noise at the input of a comparator

A thermal noise voltage with a mean (DC) voltage of m = 450mV and a standard

deviation of σ = 10mV is applied to a comparator. What is the probability for

the noise voltage to exceed the comparator threshold of 500mV?

Ps,G(500mV ) =1

2+

1

2erf

500mV −450mV √

2 ·10mV

= 1− 2.9 ·10−7

gives the probability for the noise voltage being below the comparator threshold.

It can be seen easily that the amplitude of the noise needs to have a value of 5σ or

more to exceed the threshold of the comparator. This happens with a probability

of 2.9 ·10−7 (Table G.1), i.e. it exceeds the threshold for less than a second per

month.




180 Bits and Pieces

In theory, a random process with Gaussian amplitude distribution will reach any amplitude

value once in a while - but you may have to wait very, very long to see that happen ... There-

fore, in practical applications, it is often assumed that the amplitude of such a process stays

within ±3σ . This limit is exceeded with a probability of 0.135 % (Table G.1).

x σ 2σ 3σ 4σ 5σ 6σ

1− Ps,G( x) 0.159 0.0228 1.35 ·10−3 3.17 ·10−5 2.87 ·10−7 9.87 ·10−10

erf(x)

Table G.1: Function Values of Error Integral (m = 0)

G.2 Bessel Functions

Bessel functions are useful for expanding terms like cos(ω 0t +α sinω 1t ) which occur fre-

quently in FM / PM calculations. Bessel functions of the first kind with order ν are defined

by [BS81, pp. 7ff,440ff]:

J ν ( x) =∞

∑n=0

(−1)n xν +2n

2ν +2n n!Γ (ν + n + 1)(G.2.1)

For integer values of ν , the Gamma function [BS81, pp. 6, 103] is defined by Γ (n + 1) = n!,

allowing an easier power series expansion:

J ν ( x) =∞

∑n=0

(−1)n xν +2n

2ν +2nn!(ν + n)!≈ 1

ν !

x

2

ν for | x| 1 (G.2.2)

e.g.

J 0( x) =∞

∑n=0

(−1)n x2n

22n(n!)2= 1− x2

4+

x4

64− x6

2304+ . . .

J 1( x) =∞

∑n=0

(−1)n x2n+1

22n+1n!(n + 1)!=

x

2− x3

16+

x5

384− . . .

J 2( x) =∞

∑n=0

(−1)n x2n+2

22n+2n!(n + 2)!=

x2

8+

x4

96− x6

3072+ . . .

· · ·The power series expansions for the Bessel functions of order 0 and 1 (and the functions

themselves) look quite similiar to the sine and cosine functions (G.3.20) and (G.3.21).

Some theorems for Bessel functions:

J −n( x) = (−1)n J n( x) (G.2.3)∞

∑n=−∞

J n( x) = J 0( x) + 2∞

∑n=1

J 2n( x) (G.2.4)

J n−1( x) + J n+1( x) =2n

xJ n( x) (G.2.5)

sin(α sinω t ) =∞∑

n=−∞ J n(α )sin(nω t ) (G.2.6)




G.3 Trigonometric Theorems and Identities 181

−10 −8 −6 −4 −2 0 2 4 6 8 10

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

x

J ( x )

i=0

i=1

i=2

i=3

i

Figure G.4: Bessel Functions 0th to 3rd order

= 2∞

∑n=1

J 2n−1(α )sin((2n −1)ω t ) (G.2.7)

cos(α sinω t ) =∞

∑n=−∞

J n(α )cos(nω t ) (G.2.8)

= J 0(α ) + 2∞

∑n=1

J 2n(α )cos(2nω t ) (G.2.9)

cos(ω 0t +α sinω 1t ) =∞

∑n=

−∞

J n(α )cos(ω 0t + nω 1t ) (G.2.10)

cos(ω 0t +α sin(ω 1t +φ 1)) =∞

∑n=−∞

J n(α )cos(ω 0t + n(ω 1t +φ 1)) (G.2.11)

sin(ω 0t +α sinω 1t ) =∞

∑n=−∞

J n(α )sin(ω 0t + nω 1t ) (G.2.12)

(G.2.6) and (G.2.8) are the “textbook” equations from which (G.2.10) and (G.2.12) have been

derived using (G.3.12). In (G.2.11) the modulating signal has been phase shifted.

G.3 Trigonometric Theorems and Identities

Sine Function

sinα = cos(α − π

2) (G.3.1)




182 Bits and Pieces

sinα · sinβ =1

2[cos(α −β ) − cos(α +β )] (G.3.2)

sin2α =1

2(1− cos2α ) (G.3.3)

sin3α =1

4(3sinα − sin3α ) (G.3.4)

sinnα = (G.3.5)

sin(α ±β ) = sinα cosβ ± cosα sinβ (G.3.6)

Cosine Function

cos(α ) = sin(α +π

2) (G.3.7)

cosα ·cosβ =1

2[cos(α −β ) + cos(α +β )] (G.3.8)

cos2α = 12

(1 + cos2α ) (G.3.9)

cos3α =1

4(3cosα cos3α ) (G.3.10)

cosnα = (G.3.11)

cos(α ±β ) = cosα cosβ sinα sinβ (G.3.12)

1 + 2∞

∑n=1

cos(2π nt ) =∞

∑n=−∞

δ (t − n) (G.3.13)

arccos(α ) = arctan

√1−α 2

α (G.3.14)

Mixed Sine and Cosine Function

sinα · cosβ = 12

[sin(α −β ) + sin(α +β )] (G.3.15)

sinα · cosα =1

2sin2α (G.3.16)

Euler Identity

cosα + j sinα = e jα (G.3.17)

cosα =e jα + e− jα

2(G.3.18)

sinα =e jα − e− jα

2 j(G.3.19)

Power Series Expansion for Sine and Cosine Functions

sin( x) =∞

∑n=0

(−1)n x2n+1

(2n + 1)!= x − x3

6+

x5

120− . . . ≈ x for | x| 1 (G.3.20)

cos( x) =∞

∑n=0

(−1)n x2n

(2n)!= 1− x2

2+

x4

24− . . . ≈ 1 for | x| 1; (G.3.21)

1− cos( x) =x2

2− x4

24+ . . . ≈ x2

2for | x| 1 (G.3.22)

G.4 Quadratic Equation

The equation ax2 + bx + c = 0 has two solutions - real or complex -

x1,2 =−b ±√b2 −4ac

2a(G.4.1)




G.5 Differentials and Integrals 183

G.5 Differentials and Integrals

See [BS81, pp. 35ff].

d

dt sinω t = ω cosω t

sinω t dt = − 1

ω cosω t +C (G.5.1)

d

dt cosω t = −ω sinω t

cosω t dt =

1

ω sinω t +C (G.5.2)

d

dt sin2ω t = 2ω sinω t cosω t = ω sin2ω t (G.5.3)

sin2ω t dt =t

2− 1

4ω sin2ω t +C (G.5.4)

cos2ω t dt =t

2+

1

4ω sin2ω t +C (G.5.5)

dxa2 + x2

= 1a

arctan xa

+C (G.5.6) dx

x2 (a2 + x2)= − 1

a2 x− 1

a3arctan

x

a+C (G.5.7)

Integration of the Sine Function

Strictly spoken, the integral

φ (t ) =

t

−∞cosω 1τ d τ

= 0

−∞

cosω 1τ d τ + t

0

cosω 1τ d τ

= C +1

ω 1sinω 1t where C =

0

−∞cosω 1τ d τ (G.5.8)

does not converge. However, the integral from −∞ to zero represents a constant phase C that

is bounded between

− 1

ω 1≤ C ≤ 1

ω 1(G.5.9)

and can be set to zero for most applications [Luk85, p. 234].




184 Bits and Pieces




Appendix H

Variable and Acronym Definitions

Variable Meaning Definition Unit

A Amplitude - V or A

A0 Carrier Amplitude - V or A

C (s) Output (control theory) C (s) = T (s) R(s) -

D Fixed division ratio between VCO and

synthesizer output

f out = f vco/ D 1

F Fractional part of division ratio N , written

as N .F

F = frac( N )

= N F F mod

1

F mod Number of reference cycles per modulus

cycle

F mod = T mod T re f

1

F (s) Transfer function of loop filter - (→ K F )

G(s) Forward transfer function of process or

plant, here, usually the PLL forward path

G(s) = K O/s 1

H (s) Transfer function of feedback path, here,

usually the divider transfer function

- 1

K F Loop filter gain constant, unit depends on

type of loop filter and PD - can be Ω, 1 or

Ω−1

- ←

K O Open loop gain factor K O = K ΦK F K VCO 1

K VCO VCO gain factor - Hz / V

K Φ PD gain, unit depends on PD type - can

be A / rad or V / rad

- ←

N Main division ratio N = N I + N F 1 N F Number of cycles with N (t ) = N + 1 per

modulus cycle

- 1

N I Integer part of division ratio N N I = int( N ) 1

N 0 Noise power density - W/Hz

P Power - W

R Division ratio of reference divider f re f = f sys/ R 1

R Resistance - Ω R(s) Input, stimulus - -

T Period or time duration (also look under

f xxx instead T xxx)

T = 1/ f s

T (s) Closed-loop transfer functionT (s) = C (s)

R(s)

= G(s)1+G(s) H (s)

1

185



186 Variable and Acronym Definitions

Variable Meaning Definition Unit

T ABL

Minimum duration of PD / CP - pulses

(Anti-BackLash)

- s

T mod Modulus period T mod = F mod T re f s

T w Pulse width - s

f Frequency - Hz

f 0 Carrier or VCO frequency - Hz

f 3dB Frequency where the closed loop gain has

dropped by 3dB (3dB bandwidth)

|T ( f 3dB)| = |T (0)|/√

2 Hz/s

f B (Signal) bandwidth - Hz

f FR Free running VCO frequency (V ctrl = 0) - Hz

f S Sampling frequency - Hz

f c Frequency where the open loop gain be-

comes 1 (crosses the 0 dB line)

|GH ( f c)| = 1 Hz/s

f div Divided VCO frequency at the PD f div = f O/ N Hz f m Modulation frequency - Hz

f out Output frequency of synthesizer f out = f vco/ D Hz

f re f Reference frequency at the PD / CP f re f = f sys/ R Hz

f s Frequency of spurious sideband - Hz

f vco VCO frequency - Hz

∆ f s Distance of spurious sideband from car-

rier

- Hz

f sys System frequency (crystal frequency

from which f re f is derived)

f sys = R f re f Hz

w Weight (area) of a single pulse w = +∞−∞ s(t )dt Vs or As

s Complex frequency s = σ + jω -

s(t ) Generalized signal - e.g. V or AS( f ) Power spectral density of s(t ) Fs(t ) W/Hz

t Time as a variable - s

α Duty cycle α = T w/T 1

µ Modulation indexµ = ∆ f / f m

= K vco f m/m1

φ Phase - here, ”phase” usually means ”ex-

cess phase”, i.e. without the part ω t that

increases in a linear fashion over time.

- rad

φ 0 VCO or carrier phase - rad

φ div Divided VCO (excess) phase (at PD) φ div = φ 0/ N rad

φ e Excess or error phase: the difference of

input phases at the PD

φ e = φ re f −φ div rad

φ m Phase margin of the loop - rad

φ re f Reference (excess) phase (at PD) - rad

Φ(s) Phase in the frequency domain - rad

ω Circular frequency (also look under f xxx

instead ω xxx)

ω = 2π f rad / s

ω n Eigenfrequency of second order system

(closed loop) - ω n has no relation with the

input or output frequency of the PLL! It is

rather a sort of gain-bandwidth product of

the PLL. For a second order system with

→ ζ = 0.707, ω n = ω c = ω 3dB

- rad/s

σ Standard deviation - 1

σ Real part of complex frequency σ = Res 1ζ Damping factor of a second order system - 1




187

Telecommunication business is notorious for its TLAs (Three Letter Acronyms) - this book

also uses quite a few:

Acronym Meaning

ABL Anti BackLash (pulses)

ACF Auto Correlation Function

AWGN Added White Gaussian Noise

CMOS Complementary Metal Oxide Semiconductor

CP Charge Pump

DMD Dual Modulus Divider

GSM Global System for Mobile communication, originally Global

Systeme Mondial

LF Low Frequency

LTI Linear Time-Invariant (system)

MMD Multi Modulus DividerOSR Oversampling Ratio

PD Phase Detector, also used for Phase Frequency Detector

PFD Phase Frequency Detector

PSD Power Spectral Density

PLL Phase Locked Loop

RF Radio Frequency

VCO Voltage Controlled Oscillator




188 Variable and Acronym Definitions




Bibliography

[Bes98] Roland Best. Theorie und Anwendungen des Phase-Locked Loop. AT Verlag,

Aarau / Stuttgart, 1998. German PLL Bible, no CP PLLs.

[BS81] Bronstein and Semendjajew. Taschenbuch der Mathematik . Verlag Harri Deutsch,Thun, 21st edition, 1981.

[CS98] Jan Craninckx and Michel S. J. Steyaert. A fully integrated cmos dcs-1800 fre-

quency synthesizer. Journal of Solid-State Circuits, 33:2054–2065, Dez. 1998.

Dual Path Loop Filter, Loop Filter Calculations, Prescaler.

[Dor92] Richard C. Dorf. Modern Control Theory. Addison-Wesley Publishing, Reading,

Mass., 6. edition, 1992. General control theory.

[Gar79] Floyd M. Gardener. Phaselock Techniques. John Wiley and Sons, New York,

1979. The PLL bible, but no CP’s.

[GM84] Paul R. Grey and Robert G. Meyer. Analog Integrated Circuits. John Wiley and

Sons, New York, 2nd edition, 1984. Thermal Noise, Noise Bandwidth.[GT86] Roubik Gregorian and Gabor C. Temes. Analog MOS Integrated Circuits for

Signal Processing. John Wiley and Sons, New York, 1986. Switched Circuits,

Noise of SC-Filters / S & H Circuits.

[Kun98] Ken Kundert. Modeling and simulation of jitter in pll frequency synthesizers.

http://www.designers-guide.com, 1998.

[LB92] Thomas H. Lee and John F. Bulzacchelli. A 155 mhz clock recovery delay- and

phase locked loop. IEEE J. Solid-State Circuits, 27:1736–1746, Dez. 1992. Good

introduction into clock and data recovery and DLLs, describes Hogge’s, Triwave

and Modified Triwave Phase Detector in detail.

[Lee98] Thomas H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits.

Cambridge University Press, Cambridge, UK, 1998.

[LR00] Christopher Lam and Behzad Razavi. A 2.6-ghz/5.2-ghz frequency synthesizer in

0,4µ m cmos technology. Journal of Solid-State Circuits, 35:788–794, Mai 2000.

Loop filter noise, prescaler and PLL building blocks.

[Luk85] Hans-Dieter Luke. Signal¨ ubertragung. Springer Verlag, Berlin, 3rd edition, 1985.

General Communication Theory, Fourier Transformation, PM / FM modulation.

[NSE97] S.R. Norsworthy, R. Schreier, and G.C. Temes (Eds.). Delta-Sigma Data Con-

verter: Theory, Design, and Simulation. IEEE Press, New York, USA, 1997.

[Per97] Micheal Henderson Perrott. Techniques for High Data Rate Modulation and Low

Power Operation of Fractional-N Frequency Synthesizers. PhD thesis, Massa-

chusetts Institute of Technology, 1997. two-point modulator, dual path loop filter,

XOR+ PFD.

189



190 BIBLIOGRAPHY

[PK04] Joel Phillips and Ken Kundert. Noise in mixers, oscillators, samplers & logic an

introduction to cyclostationary noise. http://www.designers-guide.com, 2004.

[PM96] John G. Proakis and Dimitris G. Manolakis. Digital signal processing (3rd ed.):

principles, algorithms, and applications. Prentice-Hall, Inc., 1996.

[RCK93] Tom A.D. Riley, Miles A. Copeland, and Tad A. Kwasniewski. Delta-Sigma

Modulation in Fractional- N Frequency Synthesis. IEEE J. Solid-State Circuits,

28(5):553–559, Mai 1993.

[Roh97] Ulrich L. Rohde. Microwave and Wireless Synthesizers. John Wiley and Sons,

New York, 1997. Loop Dynamics, Noise in the Loop.

[Smi99] Steven W. Smith. The Scientist and Engineer’s Guide to Digital Signal Process-

ing. California Technical Publishing, San Diego, USA, 2nd edition, 1999.

http://www.DSPguide.com.

[VFL+00] Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs

Voegeli, and Zhenhua Wangothers. A family of low-power truly modular pro-

grammable dividers in standard 0.35-µ m cmos technology. Journal of Solid-State

Circuits, 35:1039–1045, Jul. 2000. Dual- and Multi-Modulus Divider Concepts.




List of Figures

1.1 Phase noise and spurious sidebands on the VCO output . . . . . . . . . . . . 11

2.1 PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2 PLL block diagram - control theory point of view . . . . . . . . . . . . . . . 16

2.3 Closed loop gain |T ( jω )| and noise bandwidth Bn . . . . . . . . . . . . . . . 18

2.4 Bode plot for open loop gain of type I, 2nd / 3rd order PLLs . . . . . . . . . . 19

2.5 Averaging loop filters of 1st / 2nd order (no zero) . . . . . . . . . . . . . . . 20

2.6 Root locus diagram for typ I, first order PLL . . . . . . . . . . . . . . . . . . 21

2.7 Step response parameters: Overshoot, settling and steady-state error . . . . . 23

2.8 Step Response and Frequency Response of Type I, 2nd Order PLL . . . . . . 24

2.9 Averaging Loop Filters of 1st / 2nd order (one zero) . . . . . . . . . . . . . . 25

2.10 Bode Plot for Open Loop Gain GH ( jω ) of Type I, 2nd / 3rd order PLLs (one zero) 26

2.11 Bode Plot for Open Loop Gain GH ( jω ) of type II, 3rd / 4th order PLL . . . . 27

2.12 Integrating Loop Filters of 1st / 2nd / 3rd order (one zero) . . . . . . . . . . . 27

2.13 Root locus diagram for typ II, second order PLL . . . . . . . . . . . . . . . . 28

2.14 Step Response and Frequency Response of Type II, 2nd Order PLL . . . . . . 29

2.15 Dual Path Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.16 Impedance of Averaging Loop Filter (1 pole, no zero) . . . . . . . . . . . . . 32

2.17 Input Impedance of Averaging Loop Filter (1 pole and 1 zero) . . . . . . . . 33

2.18 Loop Filter Impedance / Effective Capacitance of Integrating Loop Filter . . . 34

2.19 Spectra of Pulses for (Non) Integrating Loop Filter . . . . . . . . . . . . . . 35

3.1 Multiplier symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2 Average multiplier output signal ud as function of phase error φ e . . . . . . . 39

3.3 Average multiplier output signal ud as function of frequency error f e . . . . . 39

3.4 Timing diagram for EXOR PD with identical frequency at its inputs . . . . . 40

3.5 Timing diagram for EXOR PD with different frequencies at its inputs . . . . 40

3.6 EXOR schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.7 EXOR average output signal ud as function of phase error φ e . . . . . . . . . 41

3.8 Average EXOR output signal ud as function of frequency error f e . . . . . . . 41

3.9 EXOR+FD schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.10 Average EXOR+FD output signal ud as function of phase error φ e . . . . . . 42

3.11 Average EXOR+FD output signal ud as function of frequency error f e . . . . 43

3.12 Signals in the EXOR+ PD when f re f > f div . . . . . . . . . . . . . . . . . . 43

3.13 Signals in the EXOR+ PD when f re f = f div (φ div < φ re f . . . . . . . . . . . . 44

3.14 JK Flip-flop schematic (neg. edge triggered) . . . . . . . . . . . . . . . . . . 44

3.15 Average JK Flip-flop output signal ud as function of phase error φ e . . . . . . 45

3.16 Average JK Flip-flop output signal ud as function of frequency error f e . . . . 45

3.17 Tristate PFD schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.18 Average Tristate PFD output signal id as function of phase error φ e . . . . . . 46

3.19 Average Tristate PFD output signal ud as function of frequency error f e . . . 47

3.20 EXOR with bidirectional charge pump and integrating loop filter . . . . . . . 47

191



192 LIST OF FIGURES

3.21 EXOR with unidirectional charge pump and integrating loop filter . . . . . . 48

3.22 Basic 2/3 divider cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.23 Signals in a 2 / 3 divider cell . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24 An 8/9 dual modulus prescaler . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.25 Dual-modulus divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.26 Signals in a dual-modulus divider . . . . . . . . . . . . . . . . . . . . . . . 50

3.27 Multi-modulus divider made from a Chain of 2/3 divider cells . . . . . . . . 50

3.28 Improved 2/3 divider cell with modulus enable . . . . . . . . . . . . . . . . 51

3.29 D-Flip-Flop in current mode logic . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 Frequency synthesizer using fractional-n techniques . . . . . . . . . . . . . . 54

4.2 Timing diagram of 1st order fractional-N PLL . . . . . . . . . . . . . . . . . 55

4.3 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4 Spectral density of quantization noise . . . . . . . . . . . . . . . . . . . . . 57

4.5 Spectral density of quantization noise with oversampling . . . . . . . . . . . 574.6 Delta modulation and demodulation . . . . . . . . . . . . . . . . . . . . . . 59

4.7 Delta modulation signal forms . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.8 Analog-to-Digital Converter using sigma-delta modulation . . . . . . . . . . 60

4.9 Digital delta-sigma modulation . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.10 Digital integrator (one sample delay) . . . . . . . . . . . . . . . . . . . . . . 61

4.11 Digital integrator (no delay) . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.12 Digital delta-sigma modulation - equivalent represenation for quantization noise 62

4.13 Second order digital sigma-delta modulator . . . . . . . . . . . . . . . . . . 63

4.14 Second order digital sigma-delta modulator . . . . . . . . . . . . . . . . . . 63

5.1 Non-Integrating Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.2 Realization of an IIR filter in direct form I . . . . . . . . . . . . . . . . . . . 675.3 Realization of an IIR filter in direct form II . . . . . . . . . . . . . . . . . . 67

5.4 IIR implementation of 1st order RC low pass . . . . . . . . . . . . . . . . . 68

5.5 Integrating Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.1 Spurious generation due to reference frequency leakage . . . . . . . . . . . . 84

6.2 Block schematic of a PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3 Comparison of single and double sided notation . . . . . . . . . . . . . . . . 86

6.4 Periodic Disturbance of Control Voltage . . . . . . . . . . . . . . . . . . . . 87

6.5 Disturbance Caused by DC Leakage Current I L . . . . . . . . . . . . . . . . 88

6.6 Spectra of Single Short Pulses v p(t ) . . . . . . . . . . . . . . . . . . . . . . 91

6.7 Spectra of Periodic Short Pulses ve(t ) . . . . . . . . . . . . . . . . . . . . . 91

6.8 Mismatch of Charge Pump Currents . . . . . . . . . . . . . . . . . . . . . . 94

6.9 Instant Frequency and Spectra of Divided, FM Modulated Signals . . . . . . 95

7.1 Characteristic behaviour of alpha spurs . . . . . . . . . . . . . . . . . . . . . 98

7.2 Spurious generation due to downsampling of RF components . . . . . . . . . 99

7.3 Example for downsampling the TX output into the reference path . . . . . . . 100

7.4 Characteristic behaviour of beta spurs for D = 4 . . . . . . . . . . . . . . . . 101

7.5 Spurious generation due to system frequency harmonics . . . . . . . . . . . . 102

7.6 Characteristic behaviour of Gamma-spurs . . . . . . . . . . . . . . . . . . . 104

7.7 Spurious generation due to reference frequency leakage . . . . . . . . . . . . 105

7.8 Spurious generation due to system frequency leakage . . . . . . . . . . . . . 106

7.9 Reference / system frequency modulating the VCO . . . . . . . . . . . . . . 106

7.10 Spurious generation due to modulation of LO buffer and divider . . . . . . . 107

7.11 LF injection into the system frequency path . . . . . . . . . . . . . . . . . . 108

10.1 Upconversion of Noise Around the Carrier f 0 . . . . . . . . . . . . . . . . . 124




LIST OF FIGURES 193

10.2 PLL Block Diagram Showing Various Noise Sources . . . . . . . . . . . . . 124

10.3 Noise Transfer Function for Reference Clock, Divider and PD / CP . . . . . . 125

10.4 Noise Transfer Function for VCO . . . . . . . . . . . . . . . . . . . . . . . 125

10.5 Open loop VCO phase noise at an offset of f m from the carrier . . . . . . . . 132

B.1 Equivalent Circuit for Noise of RC Lowpass . . . . . . . . . . . . . . . . . . 151

B.2 Noise transfer function and equivalent noise bandwidth . . . . . . . . . . . . 152

C.1 Switched Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

C.2 Switched white noise, narrow pulses . . . . . . . . . . . . . . . . . . . . . . 154

C.3 Switched white noise, wide pulses . . . . . . . . . . . . . . . . . . . . . . . 155

C.4 Switched bandlimited noise, narrow pulses α 1 . . . . . . . . . . . . . . . 156

C.5 Switched bandlimited noise, wide pulses . . . . . . . . . . . . . . . . . . . . 156

D.1 Instant Frequency and Spectra of FM Modulated Signals . . . . . . . . . . . 162

F.1 Root locus plot of C (s) as ζ varies with constant ω n . . . . . . . . . . . . . . 174

G.1 PDF of random process with Gaussian distribution . . . . . . . . . . . . . . 177

G.2 Gaussian Distribution for m=2 and σ = 1 / σ = 3 . . . . . . . . . . . . . . . 178

G.3 Error Function erf(x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

G.4 Bessel Functions 0th to 3rd order . . . . . . . . . . . . . . . . . . . . . . . . 181




194 LIST OF FIGURES




List of Tables

2.1 Attenuation of RC Lowpass Filter . . . . . . . . . . . . . . . . . . . . . . . 35

3.1 Overview of Phase Detector Types Suitable for Frequency Synthesis . . . . . 37

4.1 Operation of Phase Accumulator (F mod = 5) . . . . . . . . . . . . . . . . . . 56

8.1 Operation of Phase Accumulator (F mod = 5) . . . . . . . . . . . . . . . . . . 111

G.1 Function Values of Error Integral (m = 0) . . . . . . . . . . . . . . . . . . . 180

2005-ifx-muenker-spurious sidebands phase noise basics 20051220

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