Doctoral Thesis Multilevel Converters: Topologies, Modelling, Space Vector Modulation Techniques and Optimisations University of Seville Electronic Engineering Department Power Electronics Group Author: Jos Ignacio Len Galvn Advisor: Prof. Leopoldo Garca Franquelo

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To my family

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CONTENTS: 1. Introduction and objectives 1.1. Introduction 1.2. Objectives 2. Multilevel Converter Topologies 2.1. Introduction 2.2. Multilevel Converter Topologies 2.2.1. Diode-Clamped Converter (DCC) 2.2.1.1. Advantages and disadvantages of DCC topology 2.2.2. Flying Capacitor Converter (FCC) 2.2.2.1. Flying capacitor voltage ratios 2.2.2.2. Advantages and disadvantages of FCC topology 2.2.3. Cascaded Converter 2.2.3.1. Different DC voltage source ratios in multilevel cascaded converters 2.2.3.2. Advantages and disadvantages of Cascaded topology 2.3. Converter Connecting Configurations 2.3.1. Three-Leg Four-Wire Topologies 2.3.2. Three-Leg Four-Wire Topologies 2.3.3. Four-Leg Four-Wire Topologies 3. Multilevel Converter Models 3.1. Introduction 3.2. Diode-Clamped Converter Model 3.2.1. Three-Leg Three-Wire Diode-Clamped Converter Model 3.2.2. Three-Leg Four-Wire Diode-Clamped Converter Model 3.2.3. Four-Leg Four-Wire Diode-Clamped Converter Model 3.3. Flying Capacitor Converter Model

3.3.1. Three-Leg Three-Wire Flying Capacitor Converter Model 3.3.2. Three-Leg Four-Wire Flying Capacitor Converter Model 3.3.3. Four-Leg Four-Wire Flying Capacitor Converter Model 4. Modulation Techniques for Multilevel Converters 4.1. Introduction 4.2. Classic PWM modulations 4.3. Space Vector PWM Modulation 4.3.1. Three-Leg Three-Wire Topologies 4.3.2. Three-Leg Four-Wire Topologies 4.3.3. Four-Leg Four-Wire Topologies 5. Solving the balancing of the DC-Link capacitors in Multilevel Converters 5.1. Introduction 5.2. Quasi-solution of the balancing problem 5.3. Balancing problem depending on the converter topology 5.3.1. Diode-Clamped Converter Topology 5.3.1.1. N-level Three-Leg Three-Wire Diode-Clamped Converter Topology 5.3.1.2. N-level Four-Leg Four-Wire Diode-Clamped Converter Topology 5.3.1.3. N-level Three-Leg Four-Wire Diode-Clamped Converter Topology 5.3.2. Flying Capacitor Converter Topology 5.4. Controllability limits 6. Contributions and General Conclusions 7. Future works 8. Publications derived from the thesis work 9. References 10. Acknowledgments

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Chapter 1 Introduction and Objectives 1.1 Introduction The Electronic Engineering Department at University of Seville has been involved in multilevel converter topics during last 10 years. The research has been focused on the development of new modulation strategies and new control strategies [1]-[4]. The performance of this thesis has been the pinnacle of this research and it would be the base for future multilevel converters research in o ur department.

1.2 Objectives The objectives in this thesis have been focused on improvements on multilevel converter features. The first objective is centered on minimizing the computational cost of the modulation strategy. In this thesis, the design of sim ple and fast Space Vector Modulation (SVPWM) techniques reducing the computational cost for different multilevel converter topologies is the first ai m. On the other hand, multilevel converters present problems to achieve the balance of DC capacitors. The second objective of this thesis is the development of simple and low-cost control strategies to get voltage balance based on the use o f redundant vectors using proposed SVPWM strategies. These control algorithms should be completely generalized and they could be applied to different multilevel converter topologies and for any number of levels.

Chapter 2 Multilevel Converter Topologies 2.1 Introduction This thesis is focused on the development of different modulation techniques and several optimisations to improve some specific characteristics of multilevel converters. But, in order to make the text understandable, it is necessary to ma ke a brief overview of the most common multilevel converter topologies introducing the used nomenclature and the operation basis of this type of converters. So, th is chapter is dedicated to introduce the way of switching for multilevel converters and to show the possible output voltages that can be achieved depending on the choosing converter topology. Multilevel converters present great advantages compared with typical and very well known two-level converters [5][6]. These advantages are fundamentally

focused on improvements in the output signals quality and a nominal power increase in the converter. These properties make multilevel converters very attractive to the industry and nowadays, researchers all over the world are spending great efforts trying to improve multilevel converters performance as th e control simplification and the performance of different optimisation algorithms in order to enhance the Total Harmonic Distortion (THD) of the output signals, the balancing of the DC capacitors voltage, the ripple of the load currents, , etc. For instance, nowadays researchers are centered on the harmonic elimination using pre-calculated switching functions [7]-[11], the development of new multilevel converter topologies (hybrids or new ones) and the development of new control strategies. This thesis is not focused on the harmonic elimination topic and the control strategies for the complete system are not discussed. New topologies are not presented in this thesis but using common multilevel converte r topologies, new voltage strategies are proposed. 2.2 Multilevel Converter Topologies In order to facilitate the understanding of the text, it is going to be presente d the state-of-art of the different multilevel converter topologies. Although there ar e a large number of multilevel converter topologies in the literature, in this chapt er the most common topologies will be presented. The most typical multilevel converter topologies are: Diode-Clamped Converter (DCC), Flying Capacitor Converter (FCC), and Cascaded Converter. Several surveys of multilevel converters have been published to present these topologies [12]-[19].

2.2.1 Diode-Clamped Converter (DCC) In 1980s, power electronics concerns were focused on the converters power increase (increasing voltage or current). In fact, Current Source Inverters were the main focus for researchers in order to increase the current. However, other authors began to work on the idea of increasing the voltage instead the current. In order to achieve this objective, authors were developing new converter topologies. In 1981, A. Nabae, I. Takahashi and H. Akagi presented a new neutral-point-clamped PWM inverter (NPC-PWM) [20]. This converter was based on a modification of the classic two-level converter topology. In conventional two-level case (see Figure 2.1), each transistor must have at the most a voltage stress equal to VDC and they should be dimensioned to tolerate this voltage. Figure 2.1. Two-level conventional converter The proposed modification to get the three-level converter added two new transistors per phase (see Figure 2.2). Using this new topology, each transistor tolerates at the most a voltage equal to VDC/2. So, if these new transistors hav e

the same characteristics than the transistors in two-level case, the DC-Link voltage can be doubled achieving a value equal to 2VDC. But, this converter topology still has a problem. If transistors S1 and S2 are switched on and transistors S3 and S4 are switched off, VDC voltage should be equally shared between transistors S3 and S4. But, there is not any mechanism that assures it. The solution of this problem appears thanks to use the clamping diodes . In each phase, two diodes clamp each transistor voltage. Finally, in Figure 2.2, a three-level Diode Clamped Converter (DCC) is shown. In this converter topology, the DC-Link voltage is equally shared between capacitors C1 and C2. Figure 2.2. Three-level Diode-Clamped Converter It can be explained why this converter is named three-level converter. In order to show it, possible switching configurations of this converter topology can be presented. There are only three possible switching configurations in the threelevel DCC. Other switching possibilities are not allowed because they create

short-circuit in some DC-Link capacitor or they let the output opened. For instance, if S1, S2 and S3 are switched on, a short-circuit is created in capaci tor C2. Besides, the voltage in transistor S4 is VDC being its maximum admissible voltage equal to VDC/2. The possible switching configurations are shown in TABLE 2.I. Only three possible output phase voltages with respect to 0 (middle point of the DC-Link) appear using this converter and this is the reason to name this converter as a three-level converter.

S1 S2 S3 S4 Phase-0 voltage ON ON OFF OFF VDC/2 OFF ON ON OFF 0 OFF OFF ON ON -VDC/2 TABLE 2.I. Possible switching configurations in a three-level DCC After introducing the three-level DCC topology, it can be extended trying to achieve more levels in the output phase voltages with respect to 0 [21]. In orde r to show it, a phase of a five-level DCC is represented in Figure 2.3. Now, using this configuration there are more possible switching configurations and they can be seen in TABLE 2.II. S1 S2 S3 S4 S5 S6 S7 S8 Phase-0 voltage ON ON ON ON OFF OFF OFF OFF VDC/2 OFF ON ON ON ON OFF OFF OFF VDC/4 OFF OFF ON ON ON ON OFF OFF 0 OFF OFF OFF ON ON ON ON OFF -VDC/4 OFF OFF OFF OFF ON ON ON ON -VDC/2 TABLE 2.II. Possible switching configurations in a five-level DCC

Figure 2.3. Single phase Five-level Diode-Clamped Converter In general, for N-level DCC topology all the possible switching configurations have N-1 adjacent transistors switched on in each phase and the possible output phase voltages with respect to 0 take N discrete values in equally spaced out in the voltage range {-VDC/2, VDC/2}.

2.2.1.1 Advantages and disadvantages of FCC topology The main advantages of the DCC topology are: The number of capacitors is low compared with other topologies as the flying capacitor converter. This fact is very important due to the cost of these reactive devices. This topology does not require any transformer There is only one DC-Link bus The change between adjacent states is done changing only the state of two transistors. The main drawbacks of DCC topology are: The possibilities to control the balance of the DC-Link capacitors voltage are limited. In fact, other topologies as the Flying Capacitor topology present more possibilities to achieve the balance. This type of converter is still not a final product of companies as ABB, Semikron, , etc. Therefore, all the actual converters are homemade custom design prototypes. DCC topology has become very popular between researchers all over the world and other hybrid topologies have been developed trying to improve the converter features [22]-[24]. 2.2.2 Flying Capacitor Converter (FCC) Multilevel Flying Capacitor Converter (FCC) topology has been recently introduced and it present advantages and disadvantages compared with other multilevel topologies [25][26]. FCC topology uses several floating capacitors in each phase that connect several points in the converter to achieve different voltage levels in the output signals. This topology presents the floating capaci tors instead the clamped diodes of DCC topology. In Figure 2.4, a conventional threephase three-level FCC is shown.

Figure 2.4. Conventional three-phase three-level Flying Capacitor Converter Figu re 2.4. Conventional three-phase three-level Flying Capacitor Converter The topology can be extended trying to achieve more levels in the output phase voltages with respect to 0. In order to show it, a phase of an extended FCC is represented in Figure 2.5. All the switching configurations in FCC can be studie d using a systematic method. There is not a complete freedom in the transistors switching in each phase. In fact, each transistor can be associated with other transistor in the same phase forming different couples and only one of the transistors in each couple can be switched on at the same time. Each transistors couple forms one basic cell of the converter. If both transistors were switched on at the same instant, a short-circuit would be created in the flying capacitor of the basic cell. Multilevel FCC topology can be represented in a different way showing that the converter can be built connecting several basic cells in series . An M-cell single-phase FCC is achieved thanks to M basic cells connected in series [26]. A FCC basic cell and the M-cell single phase FCC topology are shown in Figure 2.6 and Figure 2.7 respectively.

Figure 2.5. Phase of an extended Flying Capacitor Converter

Figure 2.6. Basic flying capacitor cell Figure 2.7. M-cell Flying Capacitor Converter Topology The switching configurations study can be done defining each transistor couple state in a basic cell as a binary value specifying if the couple state is low (t he lowest transistor of the basic cell is switched on) or high (the highest transis tor of the basic cell is switched on). So, for a single phase x M-cell FCC, binary fact ors Hxi can be defined as follows:

0, S = OFF xi Hxi = xi with i = 1,..., M (2.1) 1, S = ON 2M-1 So, in general, for M-cell FCC case, there are possible switching configurations where Hxi with i=1, , M marks the state of each transistors couple in the basic cell i in the single phase x [27]. 2.2.2.1 Flying capacitor voltage ratios In general, for multilevel FCC, several flying capacitor voltages Vx1:Vx2:Vx3:..:Vx(M-1) can be considered [27]. The first presented FCC topology had floating capacitors voltage ratios equal to M-1:..:2:1 (named in this work OFBCS voltage ratio). A four-cell single phase FCC using OFBCS voltage ratio is shown in Figure 2.8 in order to show the ratio performance. Figure 2.8. Four-cell single phase FCC using OFBCS voltage ratio

Using this voltages ratio, there are only four possible switching configurations in each phase for two-cell single phase FCC and they are shown in TABLE 2.III using basic cells binary values Hxi. Other possibilities are not allowed because they create short-circuit in some capacitor or they let the output opened. It is important to say that two different switching configurations achieve the same output phase voltage with respect to 0. This is very important because this type of converter has redundant switching configurations. It will be shown later that th is property can be used to improve the floating capacitors voltage control. From TABLE 2.III it can be concluded that two-cell single phase FCC is a three-level single phase FCC with one redundant switching configuration. The state of each phase is denoted by an integer number where 0 means that the output Vxo voltage is the minimum voltage possible. SX1 SX2 HX1 HX2 Phasex-0 voltage Phasex State ON ON 1 1 VDC/2 2 ON OFF 1 0 0 1 OFF ON 0 1 0 1 OFF OFF 0 0 -VDC/2 0 Redundant switching configurations TABLE 2.III. Possible switching configurations in two-cell single phase FCC using OFBCS voltages ratio The same calculations can be done using the four-cell single phase FCC topology with OFBCS voltages ratio. In this case, there are more possible switching configurations and they are shown in TABLE 2.IV. The calculation results show that this topology achieves five different output voltage levels presenting seve ral redundant switching configurations. Using OFBCS voltages ratio, the number of

output levels (N) is the number of basic cells (M) plus one. In general, there i s an easy way to calculate the output phase voltage with respect to 0 thanks to the couples binary values using OFBCS voltages ratio. M Phase x _ State =Hxi i=1 (2.2) VV DC DC V = Phase _ State out x M 2 HX1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 HX2 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 HX3 HX4 Phasex-0 voltage Phasex_State -VDC/2 0 -VDC/4 1 -VDC/4 1 0 2 -VDC/4 1 0 2 0 2 VDC/4 3 -VDC/4 1 0 2 0 2 VDC/4 3 0 2 VDC/4 3 VDC/4 3 VDC/2 4

TABLE 2.IV. Possible switching configurations in four-cell single phase FCC using OFBCS voltages ratio

It can be seen from TABLE 2.III and TABLE 2.IV that increasing the number of cells of the converter, the switching configurations redundancy increases. This redundancy implies that the same output phase voltage can be achieved thanks to different switching configurations. This property does not appear in DCC and in chapter 5 it will be shown that it introduces some control advantages. However, it should not be forgotten that the control complexity increases with the number of FCC cells because there will be more redundant switching configurations. In [27] new flying capacitors voltage ratios were presented in order to achieve more output voltage levels with the same number of power devices. In [27][28], the comparison between these voltage ratios was presented using the Full Binary Combination Schema (FBCS) concept demonstrating that, with the same number of power devices, the number of levels in the output voltages changes depending on the voltage ratios used in FCC. Several voltage ratios generate higher number of levels compared with OFBCS. Therefore, at first sight, they improve the behaviour of the converter because they achieve better output signals quality wi th the same cost. However, all these possible configurations achieve phase to middle point of the DC-Link output voltage signals in the range {-VDC/2,VDC/2}. These voltage ratios consider that the flying capacitors voltages have the same polarity. All the flying capacitors are charged with the desired voltage in the same sense. A new voltage ratio is presented considering OFBCS voltage ratios but doing that flying capacitors voltages can be positive or negative. In the proposed voltage ratio, the sign of flying capacitor voltages (Vxi) is alternati vely positive and negative considering positive the DC-Link voltage. This proposed voltage ratio is named New FBCS (NFBCS). In Figure 2.9, a FCC performed with four basic cells using NFBCS is shown.

Figure 2.9. Four-cell single phase FCC using NFBCS voltages ratio Using this voltage configuration, the output phase to middle point of DC-Link voltage (Vx0) can be calculated. In TABLE 2.V, the results using OFBCS and NFBCS voltage ratios are shown. It can be seen that with the same number of devices (only with 4 basic cells), OFBCS achieves five output levels and NFBCS achieves 15 levels. So, it is clear that using this new voltages ratio, with the same number of power devices, the number of output voltage levels increases. Other important result can be concluded from TABLE 2.V. Using OFBCS, output Vx0 voltages are located in the range {-VDC/2, VDC/2} where VDC is the DC-Link voltage. However, using NFBCS voltages ratio the output voltages are in the range {-2VDC, 2VDC} with the same DC-Link voltage. Therefore, two clear advantages appear using NFBCS voltage ratio. In general, for a M-cell FCC using OFBCS voltages ratio, the number of output levels is N=M+1. However, using NFBCS the number of levels increases exponentially. In Figure 2.10, the number of output levels achieved by both voltage ratios is represented in order to show the increase of levels using NFBC S voltages ratio.

Switching Configuration HX1HX2HX3HX4 Output Phasex-middle point of DC-Link Voltage/VDC OFBCS NFBCS 0000 -1/2 -1/2 0001 -1/4 -3/4 0010 0011 -1/4 0 1/4 0 0100 -1/4 -7/4 0101 0 -2 0110 0 -1 0111 1/4 -5/4 1000 -1/4 5/4 1001 0 1 1010 0 2 1011 1/4 7/4 1100 0 0 1101 1/4 -1/4 1110 1/4 3/4 1111 1/4 1/2 TABLE 2.V. Output voltages for four-cell FCC using OFBCS and NFBCS voltages ratios

Figure 2.10. Number of levels achieved by OFBCS and NFBCS voltages ratios depending of the number of FCC basic cells Output voltages Vx0 range also depends on the chosen voltages ratio. Using OFBCS, Vx0 is always in the range {-VDC/2, +VDC/2} and this range does not depend on the number of basic cells in FCC. However, using NFBCS the output voltage range increases. In Figure 2.11, the output voltage range depending on the used voltages ratios is represented showing the increase depending on the number of basic cells in the FCC. Previously, the advantages using NFBCS in FCC have been shown. However, some possible drawbacks appear using this new voltages ratio. Changing the sign of flying capacitor voltages, the power semiconductors of the converter should b e chosen very carefully. Using OFBCS, each power device must support a maximum voltage equal to VDC/M where M is the number of basic cells in the FCC. But using NFBCS voltage ratio, each power device must support higher voltages and due to this fact, the specifications of each power device must be chosen in order to support this voltage. For an M-cell FCC using NFBCS, the maximum voltage that each power device must support is (2M-1)VDC/M. This problem also appears using other previously published voltage ratios [28].

Figure 2.11. Maximum output voltage obtained by OFBCS and NFBCS voltage ratios depending of the number of FCC basic cells On the other hand, the topology of power devices using NFBCS voltages ratio must be different because they must be bidirectional. Actually these bidirection al power devices are used in other converter topologies as matrix converters and they can be found easily in the market [29]. These bidirectional power devices use to be diode bridges or back-to-back switches. The diagram of a back-to-back switch is shown in Figure 2.12 and it is built using a module of two reverse blocking IGBTs. This module controls the current flow within each switch. These power devices are actually well extended and for instance, bidirectional power devices are performed by Dynex Semiconductors, Semelab or EUPEC.

Figure 2.12. Back-to-back bidirectional switch As it was shown before, using NFBCS voltages ratio it is achieved a higher number of output voltage levels (see TABLE 2.V). However, these output voltage levels are not equally spaced out. This can lead to an increase in the ripple in the output voltage signals due to the fact that there are different vo ltage steps between the possible output voltage levels. In order to minimize this problem, other voltage ratios can be taken into account. It can be considered a new voltages ratio similar to NFBCS but doing all the flying capacitors voltages equal to VDC/M where M is the number of basic cells of the FCC. This new ratio is named NEFBCS. In Figure 2.13, a four-cell FCC using NEFBCS voltages ratio is shown. All possible output Vx0 voltages can be easily determined and they are shown in TABLE 2.VI. From TABLE 2.VI, it can be seen that output voltage levels are equally spaced out and all the voltage steps are equal to VDC/M. However, NEFBCS ratio makes smaller the output voltage range. In general, for a M-Cell FCC the output voltag e range is {(-3/2+1/M)VDC,(-3/2+1/M)VDC}. So, it can be seen that increasing the number of basic cells, the maximum output voltage using NEFBCS is smaller than the obtained using NFBCS. Besides, the number of output voltage levels depends on the chosen voltages ratio. Figure 2.14 and Figure 2.15 show a comparison between OFBCS, NFBCS and NEFBCS voltages ratios.

Switching Configuration Sx1Sx2Sx3Sx4 Output Phase-middle point of DC-Link Voltage/VDC NFBCS NEFBCS 0000 -1/2 -1/2 0001 -3/4 -3/4 0010 1/4 0 0011 0 -1/4 0100 -7/4 -1 0101 -2 -5/4 0110 -1 -1/2 0111 -5/4 -3/4 1000 5/4 3/4 1001 1 1/2 1010 2 5/4 1011 7/4 1 1100 0 1/4 1101 -1/4 0 1110 3/4 3/4 1111 1/2 1/2 TABLE 2.VI. Output voltages VX0 in four-cell FCC using NFBCS and NEFBCS voltages ratios

Figure 2.13. Four-cell single phase FCC using NEFBCS voltages ratio Figure 2.14. Maximum output voltage depending on the number of basic cells in FCC using different flying capacitor voltage ratios

Figure 2.15. Number of output voltage levels depending on the number of basic cells in the FCC using different flying capacitor voltage ratios As conclusions, new flying capacitor voltages ratios using the Full Binary Combination Schema (FBCS) have been studied in order to improve the output signals features for multilevel FCC. These voltage ratios use positive and negative flying capacitor voltages. The results show that an increase in the out put voltages range and an increase in the number of levels of the converter is achieved with the same number of power devices and with the same DC-Link capacitors voltage. Therefore, to obtain the same maximum output voltage, the DC-Link capacitors voltage can be reduced and the power devices can have lower voltage requirements. Besides, discussions about the physical implementation and possible drawbacks of these voltage ratios have been introduced.

2.2.2.2 Advantages and disadvantages of FCC topology Finally, the main advantages of the FCC topology are: This topology presents more possibilities to control the DC-Link capacitors voltage compared with other multilevel topologies using the redundant switching configurations. This topology does not require any transformer The main drawbacks of FCC topology are: The number of capacitors is high compared with other topologies as the diode clamped converter. This fact is very important due to the cost of these reactive devices. The change between adjacent states is done changing the states of one several transistors. This fact increases the number of commutations in the transistors and the power losses in the converter. The clamping capacitors must be set up with the required voltage levels. So, there is necessary an initialization of the converter. This type of converter is still not a final product of companies as ABB, Semikron, , etc. Therefore, all the actual converters are homemade custom design prototypes. 2.2.3 Cascaded Converter The cascaded converter or full-bridge converter is formed by two single-phase inverters with independent voltage sources [30]. In Figure 2.16, a phase of a three-level cascaded converter is shown.

Figure 2.16. Phase of the three-level cascaded converter Considering the three-level basic cell, it is clear that only one transistor of each leg (S1-S1 , S2-S2 ) can be switched on at the same time. In order to facilitate the notation of the possible switching configurations, for each basic cell in phase x, binary factors Hxi can be defined as follows: 0, S = ON and S = OFF xi ' xi H = xi (2.3) 1, S = OFF and S = ON xi ' xi So, using this binary notation, the possible switching configurations of the thr eelevel basic cell are shown in TABLE 2.VII.

HX1 0 0 0 1 1 0 1 1

HX2 VAB 0 -VDC VDC 0

TABLE 2.VII. Possible switching configurations in a three-level cascaded converter using the binary notation This three-level converter is the basic cell that is used to build multilevel cascaded converters. A multilevel cascaded converter is easily built connecting basic three-level cells in series. For instance, the two basic cells cascaded converter is shown in Figure 2.17. It is important to notice that each basic cel l needs an independent voltage source and this is one of the most important drawbacks of this multilevel converter topology. Figure 2.17. Two basic cells cascaded converter

2.2.3.1 Different DC voltage source ratios in multilevel cascaded converters The cascaded converter topology has the same property than FCC topology. Different DC voltage source ratios can be applied in order to achieve different voltage levels in the output signals [31]. The classic cascaded converter assume s that all the DC voltage sources have exactly the same value. Assuming conventional voltage sources ratio and considering the two basic cells cascaded converter, the possible switching configurations are shown in TABLE 2.VIII. The phase state can be defined as the voltage level achieved by the converter where 0 means the lowest voltage level. This converter achieves five possible output voltages and, therefore it is a five-level converter. Analytically, it is easy to know the output phase-to-neutral voltage and the pha se state defining the FCxi parameter for M-cell cascaded converter as: 0, H = H xi xi( +1) FC = -1, H = 0 and H = 1 with i = 1,..., M xi xi xi( +1) (2.4) 1, Hxi = 1 andH xi( +1) = 0 And finally, the phase state and the output phase-to-neutral voltages can be determined using the FCxi parameter as follows:

M Phase x _ State =M -FCxi i=1 M (2.5) Vxn =VDC Phase x _ State -MV DC =-VDC FCxi i=1 Cell 1 Cell 2 Vxn voltage Phasex_State HX1 HX2 HX3 HX4 0 0 0 0 0 2 0 0 0 1 VDC 3 0 0 1 0 -VDC 1 0 0 1 1 0 2 0 1 0 0 VDC 3 0 1 0 1 2VDC 4 0 1 1 0 0 2 0 1 1 1 VDC 3 1 0 0 0 -VDC 1 1 0 0 1 0 2 1 0 1 0 -2VDC 0 1 0 1 1 -VDC 1 1 1 0 0 0 2 1 1 0 1 VDC 3 1 1 1 0 -VDC 1 1 1 1 1 0 2 TABLE 2.VIII. Output voltages for a two basic cells cascaded converter using classic voltage ratio (all DC voltage sources have the same value)

Using classic voltage sources ratio, a diagram of the necessary basic cells to obtain multilevel cascaded converters is shown in Figure 2.18. The number of three-level basic cells to build a N-level cascaded converter is (N-1)/2 with N odd. Figure 2.18. Diagram of the necessary basic three-level cells to obtain differen t multilevel single-phase cascaded converters

Other study is case, re shown

DC voltage sources ratios can be taken into account [31]. A generalized can be done for the two basic cells single phase cascaded converter. In th the possible output phase-to-neutral voltages can be calculated and they a in TABLE 2.IX.

Cell 1 Cell 2 Vxn voltage HX1 HX2 HX3 HX4 0 0 0 0 0 0 0 0 1 VDC2 0 0 1 0 -VDC2 0 0 1 1 0 0 1 0 0 VDC1 0 1 0 1 VDC1+ VDC2 0 1 1 0 VDC1- VDC2 0 1 1 1 VDC1 1 0 0 0 -VDC1 1 0 0 1 VDC2- VDC1 1 0 1 0 -VDC1 -VDC2 1 0 1 1 -VDC1 1 1 0 0 0 1 1 0 1 VDC2 1 1 1 0 -VDC2 1 1 1 1 0 TABLE 2.IX. Generalized output phase-to-neutral voltages for a two basic cells single phase cascaded converter

So, depending on the DC voltage sources values, different number of levels can be obtained in the output voltages. For instance, if VDC2 is three times VDC1, n ine different levels appear in the output voltages. It can be seen in TABLE 2.X. Cell 1 Cell 2 Vxn voltage Phasex_State HX1 HX2 HX3 HX4 0 0 0 0 0 4 0 0 0 1 3VDC1 7 0 0 1 0 -3VDC1 1 0 0 1 1 0 4 0 1 0 0 VDC1 5 0 1 0 1 4VDC1 8 0 1 1 0 -2VDC1 2 0 1 1 1 VDC1 5 1 0 0 0 -VDC1 3 1 0 0 1 2VDC1 6 1 0 1 0 -4VDC1 0 1 0 1 1 -VDC1 3 1 1 0 0 0 4 1 1 0 1 3VDC1 7 1 1 1 0 -3VDC1 1 1 1 1 1 0 4 TABLE 2.X. Output phase-to-neutral voltages for a two basic cells single phase cascaded converter considering VDC2=3VDC1

It is important to notice that depending on the chosen DC voltage sources ratio, the number of output voltage levels change. Besides, the switching configurations redundancy also depends on the DC voltage sources ratio. So, the cascaded converter topology behavior is similar to FCC topology because both converter topologies can apply different voltage ratios depending on the needed industrial application. 2.2.3.2 Advantages and disadvantages of cascaded converter topology The main advantages of the Cascaded Converter topology are: This topology is based on basic cells (full-bridge converters) connected each other. So, its modularity is important and the controller can be distributed. This makes for a simpler controller structure than for either of the two previously discussed topologies. This type of converters is a final product of companies as ABB, Semikron, , etc. Therefore, the cost of using this type of converters is lower because other topologies are completely custom made. The main drawback of Cascaded Converter topology is: This topology has not been applied at low power levels to date because of the need to provide separate isolated DC supplies for each full-bridge converter element.

2.3 Converter Connecting Configurations 2.3.1 Three-Leg Three-Wire Topologies In previous points of this chapter, the most common multilevel converter topologies have been presented showing all possible switching configurations in each converter phase. In the same way, Three-phase systems can be developed thanks to use three single phase converters. Three-leg three-wire (3L3W) converter topologies are defined as three-phase converters connected to a threephase load with the neutral point of the load unconnected. For instance, a 3L3W three-level diode-clamped converter is shown in Figure 2.19. Figure 2.19. 3L3W three-level Diode-clamped converter

2.3.2 Three-Leg Four-Wire Topologies A new topology appears if the neutral point of the load is connected to the midd le point of the DC-Link bus. This connection changes the operation conditions due to the fact that in this case the sum of the phase currents would not be zero. These converters are named Three-Leg Four-Wire (3L4W) Converters. As an example, a 3L4W three-level diode-clamped converter is shown in Figure 2.20. Figure 2.20. 3L4W three-level DCC

2.3.3 Four-Leg Four-Wire Topologies A new topology can be developed connecting the neutral point of the load to a new phase of the converter (the fourth leg). These converters are named FourLeg Four-Wire (4L4W) Converters. In this case, as in 3L4W case, it is clear that the sum of the phase currents would not be zero. But now, there are several possibilities to connect the neutral point of the load depending on the switchin g configuration of the fourth leg. As an example, a 4L4W two-level conventional converter is shown in Figure 2.21. Figure 2.21. Four-Leg Four-Wire two-level conventional converter

Chapter 3 Multilevel Converter Models 3.1 Introduction It is very important to develop mathematical models for multilevel converters to carry out simulations to find out the system response to different control strategies. In fact, the first step of the implementation of a control algorithm is to simulate it and to see if the simulation results are satisfactory. In this thesi s, several multilevel converters analytical models have been developed. These models are built thanks to commutation models and the definition of the switching functions that will be presented in this chapter. The simulation model s were developed using MatLab/Simulink software helping to the performance of the control algorithms presented in this thesis. All mathematical models are based on the determination of state equations for dynamical variables introduced in [1]. These models are conspicuous by their extreme simplicity in front of oth er previous analytical models presented in the literature [32]-[36].

In order to introduce the commutation model of a multilevel converter, a phase o f the very well known conventional two-level converter is shown in Figure 3.1. Figure 3.1. Phase of the conventional two-level converter In this converter, only one of the transistors can be switched on at the same ti me. If S1 transistor is switched on, the output phase voltage with respect to the reference (see figure 3.1) is VDC/2 and if S2 transistor is switched on, the out put phase voltage with respect to the reference is -VDC/2. In order to simplify the circuit, it is possible to replace the phase using an ideal switch that connects the output to the possible voltage connection points of the system. The switching functions are defined as Sij where i is the phase and j is the point where the p hase i output is connected (it is supposed that 0 is the lowest voltage connection value). The switching function Sij is equal to 1 if the phase i is connected to th e voltage connection point j and 0 if the phase i is connected to other voltage connection point. The simplification of the two level single phase converter can be seen in Figure 3.2.

Figure 3.2. Phase of the conventional two-level converter using an ideal switch This type of commutation model using switching functions simplifies the graphical display of multilevel converters and is completely generalized because any type of transistors can be considered in the system. In this way, the study of multilevel converters is completely generalized obtaining the simulation results using ideal switches. Some transistors real effects as the turn-on time, turn-of f time, internal resistance, internal losses, , etc, are neglected. However, the main advantage of this type of commutation model is its simplicity and its easy implementation in simulation softwares in order to study complex systems as multilevel converters. The implemented analytical models need the state equations for the DC capacitors voltages and the phase currents. This chapter is focused on the determination of these state equations depending on the multilevel converter topology. Using matrix notation, the state equations can be described as follows . dWJx1 = AW + BV (3.1) JxJ Jx 1 Jx 1 DC dt

3.2 Diode-Clamped Converter (DCC) Model 3.2.1 Three-Leg Three-Wire Diode-Clamped Converter (3L3W-DCC) Model Figure 3.3 shows the commutation model of a three-phase 3L3W three-level DCC. As a three level converter, it can be seen that each phase can be connected to level 0, 1 or 2. The mathematical model uses the switching functions Sij for i . {a,b,c} and j . {0,1,2}. Figure 3.3. Commutation model of three-level Diode-Clamped Converter 3L3W Three-level DCC can be easily extended increasing the number of levels. The commutation model of the 3L3W N-level DCC is shown in Figure 3.4. In the N-level case, the mathematical model uses switching functions Sij where i . {a,b,c} and j . {0,1, , N-1}.

Figure 3.4. Commutation model of N-level Diode-Clamped Converter All developed mathematical models are calculated assuming that multilevel converters are connected to three-phase RL loads. The N-level DCC connected to this load is represented in Figure 3.5.

Figure 3.5. Commutation model of a three-level 3L3W Diode-Clamped Converter connected to a RL load In general for N-level DCC, the currents that flow through the DC-Link capacitors can be determined using the switching functions. dVC1 N-2 N-3 N-41 321 -- F i =C =- F - F - F -- ... F ... F - F 11 123 N-1 N-4 N-3 N-2 dt N-1 N-1 N-1 22 N-1 N-1 N-1 dV 1 N-3 N-41 321 i =CC2 = F - F - F ... F -- F - F -- ... F 22 123 N-1 N-4 N-3 N-2 dt N-1 N-1 N-1 22 N-1 N-1 N-1 dVC31 2 N -41 321 i -- ... =C = F + F - F ... F -- F - F - F 33 123 N-1 N-4 N-3 N-2 dt N-1 N-1 N-12 N-1 N-1 N-1 2 (3.2) dVC41231 321 i =C = F + F + F ... F -- F - F -- ... F 44 123 N-1 N-4 N-3 N-2 dt N-1 N-1 N-1 22 N-1 N-1 N-1 ..... dV (2 CN-1)123 1 N-4 N-3 Ni =C = F + F + F ... F ++ F + F ++ ... FN N-1 N-1 123 N-1 N-4 N-3 -2 dt N-1 N-1 N-1 22 N-1 N-1 N-1

where F=Si Si +Si (3.3) i (ai a +bib cic) And finally, the state equations of the DC-Link capacitors voltages are presente d. dV 1 1 C1 =-fF -fF -fF ... F -- gF -gF -gF -- ... 11 22 33 N-13 N-42 N-31 N-2 dt C 2 1 2 . dVC21 1 . = gF -fF -fF -- ... F ... gF -- gF -gF 11 22 33 N-13 N-42 N-31 N-2 dt C 2 2 2 dVC31 1 = gF +gF -fF -- ... F ... gF -- gF -gF 11 2233 N-13 N-42 N-31 N-2 dt C 2 3 2 (3.4) dV 1 1 C4 = gF +gF +gF -- ... F ... gF -- gF -gF 1122 33 N-13 N-42 N-31 N-2 dt C 2 4 2

..... dVCN( -1) 1 1 = gF +gF +gF ++ ... F ... fF + ++ fF -fF 1122 33 N-13 N-42 N-31 N-2 dt C 2 N-1 2 where N--1 i fi = N-1 (3.5) i g = iN-1 In order to determine the state equations for the phase currents, the output pha se voltages with respect to 0 (lowest point of the DC-Link) are calculated as follows.

V ) ++) ++ V =SV +S (V +V ) +S (V +V + ... a0 a1 C1 a2 C1 C2 a3 C1 C2 C 3 Sa N (V +V VCN ) +SaN L + ( V V +

-2) C1 C2 ++ ... ( -2) ( -1)VDC -didta ) ++ =SV +S (V +V ) +S (V +V ...

b0 b1 C1 b2 C1 C2 b3 C1 C2 C3 dib ++ SV -L +S ( -2) (VC1 +VC2 ... V ( -2) ) +( -1) DC bN CN bN dt (3.6) ( V ) ++ V =SV +SV +V ) +S (V +V + ... c0 c1 C1 c2 C1 C2 c3 C1 C2 C3 dic S ++ SV -L +( -2) (VC1 +VC2 ... V ( -2) ) +( -1) DC cN CN cN dt 3L3W topology fulfils that the voltage of the neutral point of the load with respect to 0 is determined as follows. V +V +V a0 b0 c0 VN0 = 3 (3.7) The phase voltages with respect to the neutral point of the load are determined.

V =V -V =Ri aN a0 N0 aa (3.8) V =V -V =Ri bN b0 N 0 bb V =V -V =Ri cN c0 N0 cc And finally, the phase currents state equations are presented.

di RV a aC1 =a+2( S1 ++ ... aN ( --S1 ... bN ( - )( -S1 ++ cN i aS 2) ) ( b ++ S 2) c ... S( -2))+ . dt L 3L V C2 Sa2 ++ S( - )( b2 ++ S( - )( -Sc2 ++ ScN-2)) + 2( ... aN 2) -S ... bN 2) ... ( + 3L V +C3 2( ++ S 2) ) ( ++ SbN )( ++S() S ... -S ... -S ... + a3 aN ( - b3( -2) c3 cN-2) 3L ++ ... V CN( -2)+ (2 SaN ( --S( -2) -ScN()+ 2) bN -2) 3L V +DC(2 SaN ( --S( --ScN() 1) bN 1) -1) 3L di RV b bC1

- i+ -Sa1 ... S( - )+2( b1 ++ S( -2) -Sc ++ ScN 2)) =b ( ++ aN 2) S ... bN )( 1... ( - + dt L 3L VC2 + -( a ... S( -2) )+2( b2 ... S( -) -Sc2 ... S( -2)) + S ++ S ++ )( ++ 2 aN bN 2 cN 3L VC3 -S ... SaN )+2( ... SbN -S ++ S( 2)) + 3L( a3 ++ ( -2) Sb3 ++ ( -2) ) ( c3 ... cN-+ (3.9) ++ ... V CN( -2) + (-SaN ( -+2S( --ScN()+ 2) bN 2) -2) 3L VDC + 3L(-SaN ( -+2S( --ScN( -1)) 1) bN 1) di RV c cC1 S ... )( ... bN S ... ) + =ic+ -( a1 ++SaN( -2) -Sb1 ++ S( -2) )+2( c1 ++ ScN( -2) dt

L 3L VC2 -Sa2 ++ ( -2) ) ( b2 ... S( -+ Sc2 ++ ScN- )+ + ( ... SaN -S ++ bN 2) )2( ... ( 2) . 3L VC3 -Sa3 ... S( -2) -Sb3 ... S( - )+2( c3 ++ ScN- ) + ( ++ aN )( ++ bN 2) S ... (2) + 3L ++ ... V CN( -2)+ 3L (-SaN( -2) -SbN ( -2) +2ScN( -2))+ +VDC(-SaN ( --S( -+2ScN( -1)) 1) bN 1) 3L

3.2.2 Three-Leg Four-Wire Diode-Clamped Converter (3L4W-DCC) Model The mathematical model of this topology is very similar to 3L3W-DCC model. In fact, the only difference is that, in this topology, VN0 voltage is constant and equal to VDC/2. The commutation model for this topology is shown in Figure 3.6. Figure 3.6. Commutation model for N-level 3L4W Diode-Clamped Converter connected to a RL load

So, the expressions presented for the 3L3W topology are valid but imposing that VN0 is equal to the middle DC-Link voltage. Hence, state equations for the DCLink capacitors voltage for 3L4W DCC are (3.4). Nevertheless, the phase currents state equations change due to the presence of the fourth wire connectin g the neutral point of the load with the middle point of the DC-Link. So, using 3L4W-DCC topology, the phase voltages with respect to the neutral point of the load can be determined. VDC V = V -= Ri aN a0 aa 2 V DC (3.10) V = V -= Ri bN b0 bb 2 VDC VcN = Vc0 -= Ricc 2 And finally, the phase currents state equations are presented. di RV 1 a aDC =- i- + 1( a1 +... +S( -2) ) + C2( a2 +... +S( -2)) + VS VS a C aN aN dt L 2LL VS + ( -2) ( -2) + D( -1) ...+VCN SaN CaN dib Rb VDC 1 =- i- + 1( 1 +... +S( - )+ C2( b2 +... +S( - )+ VS VS b Cb bN 2) bN 2)

dt L 2LL (3.11) +...+VS +VS ( bN CbN CN -2) ( -2) D( 1) di RV 1 c cDC =- i- + C (1 +... +ScN )+ ( c2 +... + VS ( - C2 S( -2) c 1 c 2) VS cN )+ dt L 2LL +...+VS +VS ( cN CcN CN -2) ( -2) D( 1)

3.2.3 Four-Leg Four-Wire Diode-Clamped Converter (4L4W-DCC) Model The commutation model of the 4L4W N-level DCC is shown in Figure 3.7. The commutation model has been validated connecting the converter to a R-L load. This system is going to be described in detail. Figure 3.7. Commutation model for N-level 4L4W Diode-Clamped Converter connected to a RL load It can be seen that the DC-Link capacitors voltages state equations can be determined using (3.4) where fi and gi were defined in (3.5) but assuming that F i functions can be determined as follows.

=+ iS+ i=( - ) +( - ) +( - (3.12) iS+ i=( - ) +( - ) +( - (3.12) FSi S+ iSSSi SSi SSi ) i aia bib cic diN ai dia bi dib ci dic On the other hand, the voltage of the neutral point of the load with respect to 0 (lowest point of the DC-Link) can be determined. + ( ++ ... V =SV +S (VV )+SVV V )++ N 0 d1 C1 d 2 C1 C2 d 3 C1 C2 C3 (3.13) +S ( -2) (VC1 ++ ... V ( - )+Sd N ( V dN CN 2) -1) DC The phase voltages with respect to 0 are calculated thanks to expression (3.6) a nd finally, using (3.8), the phase currents state equations are presented.

di RV a aC1 - i+S ++ S( -2) ) ( -Sd1 ++ S( -2)) =a ( a1 ... aN ... dN + dtL L VC2 ( ++ S( -2) ) ( Sd2 ++ ... S( -2)) + + S ... a2 aN dN L VC3 +a ... )( S ++ dN (S aN - ) ... L 3 ++ S( -2) d3 ... S( -2) ++ ( -2) VCN +S -S + ( dN aN -2) ( -2) L VDC +S -S aN ( -1) dN( -1) L dib Rb VC1 - i+S ++ S( -2) ) ( -Sd1 ++ S( - ) =b ( b1 ... bN ... dN 2) + dtL L VC2 ( ++ S( -2) ) ( Sd2 ++ ... S( - )+ + S ... b2 bN dN 2)

L VC3 (S ++ S( -2) ) ( d3 ++ S( -2))++ + ... -S ... ... b3 bN dN L (3.14) ( -2) VCN+ SbN ( -2) -S( -2) + L dN + VLDC SbN -1) -SdN-1) (( di RV c cC1 - i+S ++ S( -2) ) ( -S1 ++ S( -2)) =c ( c1 ... cN d ... dN + dtL L V ( ++ S( -2) ) ( Sd2 ++ ... S( -2)) + +C2 S ... c2 cN dN L V (S ++ S( -2) ) ( d3 ++ S( -2)) ++ +C3 ... -S ... ... c3 cN dN L V CN( -2) +S -S + ( dN cN -2) ( -2) L

V +DC S -S cN( - ( 1) dN-1) L

3.3 Flying Capacitor Converter Model 3.3.1 Three-Leg Three-Wire Flying Capacitor Converter (3L3W-FCC) Model All developed FCC models assume that the converter is connected to an RL load. Each multilevel single phase FCC can is represented in Figure 3.8. In order to build the commutation model of the flying capacitor converter, it is necessary t o use FCxi factor definition using each basic cell binary values Hxi defined in (2 .1) for M-cell single phase x FCC. Figure 3.8. Single phase FCC. In the three-phase model, each phase is connected to an RL load.

0, H = H xi xi( +1) (3.15) FC =-1, H = 0 and H = 1 with i = 1,..., M-1 xi xi xi( +1) 1, H = 1 andH = 0 xi xi( +1) Using this definition, the state equations for multilevel FCC can be easily determined. In general, for M-cell FCC it can be determined currents that flow through the floating capacitors in phase x. dVCx1 iCx = Cp1 = FCi 1 xx1 dt dVCx2 i = C = FCi Cx2 x2 xx dt 2 (3.16) ..... dV C( xM 1) i = C = FC i C( -1) xM ( - xM -1) x xM 1) ( dt And the state equations of the floating capacitor voltages can be determined. dV FCi

C= xx x11 dt Cx1 dV FCi C= xx x22 dt Cx2 (3.17) ..... dV FCi xM -1) ( - x C( xM 1) = dt C xM( -1) These expressions are valid for every flying capacitor voltage ratio only taking into account that depending on the chosen flying capacitor voltage ratio (OFBCS, NFBCS or NEFBCS), the flying capacitor voltages (VCxi) magnitude and sign change.

In order to determine the state equations for the phase currents, only the two-c ell FCC case is shown because increasing the number of cells, expressions are not easily extended. Anyway, expressions for a large number of cells can be calculated following the same steps presented in this thesis. The output phase voltages with respect to 0 (lowest point of the DC-Link) are calculated as follows using two-cell OFBCS ratio. VV di DC DC a Va0 = Sa1[ + FC a1( - VCa 1)] + a2 DC - L SV 22 dt VV di DC DC b V = S [ + FC ( - V )] + SV - L b0 b1 b1 Cb 1 b2 DC 22 dt (3.18) VV di DC DC c Vc0 = Sc1[ + FC c1( - VCc 1)] + c2 DC - L SV 22 dt For two-cell NFBCS and NEFBCS ratios, dia V =- SV + SV + S (V + V ) - L a0 a0 Ca 1 a2 DC a3 DC Ca1 dt dib V =- SV + SV + S (V + V ) - L b0 b0 Cb 1 b2 DC b3 DC Cb1 dt (3.19) dic V =- SV + SV + S (V + V ) - L c0 c0 Ca 1 c2 DC c3 DC Cc1

dt 3L3W topology fulfils that the voltage of the neutral point of the load with respect to 0 is determined using (3.7) and the phase voltages with respect to th e neutral point of the load are determined using (3.8). Finally, the phase current s state equations for two-cell FCC using OFBCS ratio are presented.

di a Ra 211 =- i - S FC V + S FC V + S FCV + aa1 a1 Ca 1 b1 b1 Cb 1 c1 c1 Cc1 dt L 3L 3L 3L 1 1 +V { [S (1 +FC )+2S ]- [S (1 +FC )+S (1 +FC )+2( S +S )]} DC a1 a1 a2 b1 b1 c1 c1 b2 c2 3L 6L di b Rb 211 S FC V b Cb + S FC V 1 a SFCV + =- ib 1 b11 a 1 Ca 1 + c1 c1 Cc1 dt L 3L 3L 3L 11 +V { [S (1 +FC )+2S ]- [S (1 +FC )+S (1 +FC )+2( S +S )]} (3.20) DC b1 b1 b2 a1 a1 c1 c1 a2 c2 3L 6L di c Rc 211 =- i - S FC V + S FC V + S FCV + cc1 c1 Cc 1 a1 a1 Ca 1 b1 b1 Cb1 dt L 3L 3L 3L +VDC [Sc1(1 +FC c1)+2Sc2]- [Sa1(1 +FC a1)+Sb1(1 +FC b1)+2( Sa2 +Sb2)] {31 L 61 L } The phase currents state equations for two-cell FCC using NFBCS and NEFBCS ratios are presented. di a Ra 1 =- i + [2 V (-S +S )-V (-S +S )-V (-S +S )+ a Ca 1 a0 a3 Cb 1 b0 b3 Cc 1 c0 c3

dt L 3 L -V (2 S +2S -S -S -S -S )] DC a2 a3 b2 b3 c2 c3 di R 1 b =- ai + [-V (-S +S )+2V (-S +S )-V (-S +S )+ b Ca 1 a0 a3 Cb 1 b0 b3 Cc 1 c0 c3 dt L 3L (3.21) -V (-S -S +2S +2S -S -S )] DC a2 a3 b2 b3 c2 c3 di c Rc 1 =- ic + [-VCa 1(-Sa0 +Sa3)-VCb 1(-Sb0 +Sb3)+2VCc 1(-Sc0 +Sc3)+ dt L 3L -VDC (-Sa2 -Sa3 -Sb2 -Sb3 +2Sc2 +2Sc3)]

3.3.2 Three-Leg Four-Wire Flying Capacitor Converter (3L4W-FCC) Model The state equations of 3L4W FCC can be determined. In general, for N-cell converter the floating capacitor voltages state equations are exactly the same t hat equations presented for 3L3W DCC in (3.17). The state equations of 3L4W FCC can be easily determined applying expressions (3.10), (3.18) and (3.19). For two-cell OFBCS ratio, di RV S aaDC a1 SS 1] =- i + [ (1 -FC ) +2 -+V FC aa1 a1 a2 Ca 1 a1 dt L 2LL di RV S bbDC b1 SS 1] =- i + [ (1 -FC ) +2 -+V FC bb1 b1 b2 Cb 1 b1 dt L 2LL (3.22) di RV S ccDC c1 =- i + [ (1 -FC ) +2S -+ S 1] V FC cc1 c1 c2 Cc 1 c1 dt L 2LL And for two-cell NFBCS and NEFBCS ratios, di RV V 1 a aCa 1 DC =- i + ( -S ) + ( +S SS ) aa3 a0 a2 a3 dt LL L 2 di RV V 1

b bCb 1 DC =- i + ( -S ) + ( +S SS ) bb3 b0 b2 b3 dt LL L 2 (3.23) di RV V 1 c cCc 1 DC =- i + ( -S ) + ( +S SS ) cc3 c0 c2 c3 dt LL L 2

3.3.3 Four-Leg Four-Wire Flying Capacitor Converter (4L4W-FCC) Model The state equations of 4L4W FCC can be determined. In general, for N-cell converter the floating capacitor voltages state equations are exactly the same t hat equations presented for 3L3W DCC in (3.17). The flying capacitor current state equations of 4L4W FCC can be determined applying (3.8). In 4L4W FCC, VN0 voltage is calculated depending on the chosen voltage ratio. For two-cell OFBCS, VDC VDC V N0 = Sd1[FC d (VCd 1 - ) + ]+ SVDC 1 d2 22 (3.24) And for two-cell NFBCS and NEFBCS, SV VN 0 = (Sd2 + Sd3)VDC + (Sd3 - d0) Cd1 (3.25) Finally, using (3.18) and (3.19), the flying capacitor current state equations a re presented. For two-cell OFBCS ratio,

di V a = DC [S (1 - FC ) + 2( S - S ) - S (1 - FC )] + a1 a1 a2 d2 d1 d1 dt 2L VV R Ca 1 Cd 1 a + S FC - S FC - i a1 a1 d1 d1 a L LL di b VDC = [S (1 - FC ) + 2( S - S ) - S (1 - FC )] + b1 b1 b2 d2 d1 d1 dt 2L VCb 1 VCd 1 Rb (3.26) + S FC - S FC - i b1 b1 d1 d1 b L LL di c VDC = [S (1 - FC ) + 2( S - S ) - S (1 - FCd )] + c1 c1 c2 d2 d11 dt 2L VV R Cc 1 Cd 1 c + S FC - S FC - i c1 c1 d1 d1 c L LL And for two-cell NFBCS and NEFBCS ratios, di RVV V a aCa 1 Cd 1 DC =- i + (S -S ) - (S -S ) + (S +S -S -S ) aa3 a0 d3 d0 a2 a3 d2 d3 dt LLL L

di RVV V b bCb 1 Cd 1 DC =- i + (S -S ) - (S -S ) + (S +S -S -S ) bb3 b0 d3 d0 b2 b3 d2 d3 dt LLL L (3.27) di RVV V c cCc 1 Cd 1 DC =- i + (S -S ) - (S -S ) + (S +S -S -S ) cc3 a0 d3 d0 c2 c3 d2 d3 dt LLL L

Two-cell 3L3W FCC state equations using OFBCS voltage ratio R 21 1 dia - a 00 - SFC SFC SFC a1 a1 b1 b1 c1 c1 L 3L 3L 3L 1 dt Rb 1 21 S (1 2 FC - S [2 S (1 +FC )+4 -S +FC )- S -S (1 + )2] di a1 a1 a2 b1 b1 b2 c1 c1 c2 b 0 - 0 S FC - SFC SFC a1 a1 b1 b1 c1 c16L L 3L 3L 3L ia dt Rc 11 2 i 1 [2 S (1 +FC )+4S -S (1 +FC )-2S -S (1 +FC )-2] dic 00 - SFC SFC - S FC b b1 b1 b2 a1 a1 a2 c1 c1 Sc2 a1 a1 b1 b1 c1 c16L L 3L 3L 3L dt ic = + 1 VDC FCa1 [2 S (1 +FC )+4S -S (1 +FC )-2S -S (1 +FC )2] - S dV Vc1 c1 c2 a1 a1 a2 b1 b1 b2 Ca1 000 0 0 Ca1 6L dt Ca1 V Cb10 dV FC Cb1 0 b100 0 0 VCc1 0

dt C b1 0 dVCc1 FC 00 c10 0 0 dt C c1

Two-cell 3L3W FCC state equations using NFBCS or NEFBCS voltages ratio R 2 11 di -a 00 ( Sa0 Sa3) ( Sb0 Sb3) ( Sc0 Sc3)a -+ --+ --+ L 3L 3L 3L 1 --- didt 0 -Rb 0 1( Sa0 Sa3) 2( Sb0 Sb3) 1( Sc0 Sc3) 3L[2 Sa2 +2Sa3 Sb2 Sb3 Sc2 Sc3] b --+ -+ --+ L 3L 3L 3L ia 1 dt Rc 1 12 i [ SS 2S 2SSS ]---+ + -dic --+ --+ ( S ) b a2 a3 b2 b3 c2 c3 00 - ( SS )( SS ) -+S a0 a3 b0 b3 c0 c33L L 3L 3L 3L dt ic = + 1 V FCa1 - -- SSS S +2] [ S --+ 2 S DC dV Va2 a3 b2 b3 c2 c3 Ca1 3L Ca1 - 000 00 dt V Ca1 Cb10 dV FC

Cb1 b1 V 0 - 00 00 . dt C . Cc1 0 b1 0 dVCc1 FC 00 -c10 00 dt C c1

Two-cell 3L4W FCC state equations using OFBCS voltage ratio R 1 a 00 S FC 00 di - aa1 a1 LL 1 dt Rb 1[S (1 -FC )+2S -1] dib 0 - 00 S FC 0 a1 a1 a2 b1 b12L LL ia dt 1 di Rc 1 ib [Sb1(1 -FC b1)+2Sb2 -1] c 00 - 00 S FC c1 c12L LL dt ic = + 1 V dV FCa1 V [Sc1(1 -FC c1)+2Sc2 -1] DC Ca1 000 00 Ca1 2L Ca1 dt VCb10 dV FC Cb1 0 b100 00 VCc1 0 dt Cb1 0

dV FC Cc1 c1 00 000 dt C c1

Two-cell 3L4W FCC state equations using NFBCS or NEFBCS voltages ratio R 1 dia - a 0 0(S -S )0 0 a3 a0 LL dt 11 Rb 1(S +S - ) dib 0 - 0 0(Sb3 -Sb0) 0 La2 a32 LL ia dt 11 R 1 i dic 00 - c 0 0(Sc3 -Sc0) b L (Sb2 +Sb3 2) LL dt ic = + 11 V dV FCa1 V (Sc2 +Sc3 - ) DC Ca1 - 000 00 Ca1 L 2 Ca1 dt VCb10 dV FC Cb1 0 - b100 00 VCc1 0 dt Cb1 0 dV FC Cc1 c1 00 - 000

dt Cc1

Two-cell 4L4W FCC state equations using OFBCS voltage ratio Ra 11 dia - 00 S FC 00 - S FC a1 a1 d1 d1 LL L dt R 11 b 1 b 0 - 00 S FC 0 - S FC di b1 b1 d1 d1 [Sa1(1 -FC a1)+2( Sa2 -Sd 2)-Sd1(1 -FCd1)] LL L 2L dt ia R 11 c 1 dic 00 - 00 S FC - SFC i c1 c1 d1 d1[S (1 -FC )+2( S -S )-S (1 -FC )] bb1 b1 b2 d 2 d1 d1 L LL 2L dt ic FCa11 dVCa1 = 00000 0 V + Sc1(1 -FCc1 + (Sc2 -Sd 2)-Sd1(1 - d1 V [ )2 FC )] C Ca1 DC a1 2L dt

VCb1 dV FCb10 Cb1 0 0000 0 V C Cc1 0 dt b1 V dV FCc1 Cd1 0 Cc1 00 0000 dt C 0 c1 dV Cd1 FC d1 000 000 dt C d1

Two-cell 4L4W FCC state equations using NFBCS or NEFBCS voltages ratio Ra 11 - 0 0(Sa3 -Sa0)0 0 - (Sd3 -Sd0). LL L dia R 1 11 b dt 0 - 0 0(Sb3 -Sb0) 0 - (Sd3 -Sd0) (S +S -S -S ) a2 a3 d 2 d3 LL L L di b ia R 11 dt 00 - c 0 0(Sc3 -Sc0) - (Sd3 -Sd0) i 1(S +S -S -S ) bb2 b3 d 2 d3 L LL L di c ic a11 dt = - FC 00000 0 V + (Sc2 +Sc3 -Sd 2 -Sd3)V C Ca1 DC a1 L dVCa1 VCb1 FCb10 dt 0 - 0000 0 V C Cc1 0

dVCb1 b1 V FC Cd1 0 dt c1 00 - 000 0 dV C 0 Cc1 c1 dt FC d1 000 - 00 0 C d1

Chapter 4 Modulation Techniques for Multilevel Converters 4.1 Introduction In previous chapters, several multilevel converter topologies have been presented. Each topology has different switching configurations in order to achieve the desired output signals. The converter switching must be controlled t o follow a control reference and modulation strategies are in charge to define the switching control in the converter. The primary objective of the modulation algorithm is to synthesize a control reference obtaining a pulse train with the same averaged value. Several modulation strategies have been proposed in the literature. Pulse Width Modulation (PWM) and Space Vector PWM (SVPWM) techniques are typical modulation strategies and they are explained in the next points.

4.2 Classic PWM Modulations Pulse Width Modulation (PWM) strategy is carried out obtaining a pulse train where the pulse s width has the modulation information [37]. The simplest PWM technique implementation can be done using a triangular carrier signal with frequency fc trying to modulate a reference signal with lower frequency fs. In Figure 4.1, a sinusoidal reference signal is modulated using a triangular carrie r obtaining a high frequency PWM pulse train [37]. Multilevel PWM can be obtained using more than one triangular carrier. For an N-level converter, N-1 carriers are arranged in contiguous bands across the full linear modulation range of the multilevel converter. All the carriers have the same frequency and amplitude and the reference waveform is placed in the middle of the carrier bands [38][39]. As an example, a five-level PWM schema is shown in Figure 4.2. Different possibilities appear because several relative carrier phases can be us ed. In the first case (Figure 4.2), all the carriers were in phase and this PWM is named Phase Disposition PWM or PD-PWM. Other possibility lies in to use a 180 phase shifts between positive and negative carriers. This possibility is named Phase Opposition Disposition PWM or POD-PWM and it can be seen in Figure 4.3. Other possible PWM can be carry out doing that each carrier is alternately out of phase with its neighbour. This possibility is named Alternati ve Phase Opposition Disposition PWM or APOD-PWM and it can be seen in Figure 4.4 [40].

Figure 4.1. Conventional two-level PWM. The low frequency reference signal is modulated using a triangular carrier with higher frequency. Figure 4.2. Five-level PWM schema using four triangular carriers disposed to carry out PD-PWM.

Figure 4.3. Five-level PWM schema using four triangular carriers disposed to carry out POD-PWM. Figure 4.4. Five-level PWM schema using four triangular carriers disposed to carry out APOD-PWM.

Some authors have compared the different PWM strategies showing the spectral analysis produced by the modulation processes [41]. These studies say that PDPWM is harmonically superior across the bulk of the modulation region because is the only technique which places harmonic energy into a common mode carrier harmonic which cancels in the line to line voltage. In order to show the modulation quality of the presented PWM schemes, the total harmonic distortion (THD) using PD-PWM, POD-PWM and APOD-PWM are shown in Figure 4.5, Figure 4.6 and Figure 4.7 respectively and several PWM comparisons are present in the literature [42]-[44]. Finally, it must be noticed that many more strategi es have been proposed in order to improve some characteristics of the converter operation [45]-[50]. Figure 4.5. Total Harmonic Distortion (% of fundamental) for a five-level converter using PD-PWM

Figure 4.6. Total Harmonic Distortion (% of fundamental) for a five-level converter using POD-PWM Figure 4.7. Total Harmonic Distortion (% of fundamental) for a five-level converter using APOD-PWM

4.3 Space Vector PWM Modulation An alternative PWM method is the Space Vector Modulation (SVPWM) [51]. This modulation method presents important advantages compared with PWM modulation [43][44]. As it was seen before, PWM modulation calculates the multilevel converter switching configurations automatically. In fact, it is an automatic method that completely marks the switching of the converter and there is no ANY freedom degree and the control algorithm has not the possibility of changing for instance the order of the switching configurations in the switching sequence. So, there is no freedom in order to improve some characteristics of th e converter as balancing of DC-link capacitors, harmonic content, load currents ripple, ,etc [52]. In front of this fact, SVPWM modulation calculates the switching configurations and chooses their order into the switching sequence [51]. Besides, SVPWM modulation introduces the concept of the redundant vectors and their important contribution to the converter control [53]. First of all, the State Vectors Spac e of a converter is going to be introduced to present this modulation method. Several converter configurations presented in chapter 2 are considered: three-leg threewire converters, three-leg four-wire converters and four-leg four-wire converter s. 4.3.1 Three-leg three-wire converters (3L3W) Three-phase converters without connecting the neutral point of the load are named three-leg three-wire systems (3L3W systems) and they were presented in chapter 2. A 3L3W two-level conventional converter is shown in Figure 4.8.

VDC 2 VDC 2 a S1 S2 C1 C2 S3 S4 S5 S6 b c load load load Figure 4.8. 3L3W two-level conventional converter Output phase-to-neutral voltages (VxN) for two-level conventional converter can be determined. VxN can be represented using abg coordinates resulting that VxN g coordinate is equal to zero and the state vectors can be placed on the ab plane. The state vectors space for two-level conventional converter is shown in Figure 4.9. Two possible states are placed in the same point in the plane. These state vectors are named redundant vectors and they are completely equal seen from the load. Each 3L3W state vector of the converter is defined as xyz where x is t he state of phase a, y is the state of phase b and z is the state of phase c. In tw o-level case, if the highest phase transistor is switched on, the associated parameter i s equal to 1 and if the lowest phase transistor is switched on, the associated parameter is equal to 0. So, for example, the state vector 100 means that transistors S1, S4 and S6 are switched on and S2, S3 and S5 are switched off.

Figure 4.9. State vectors space for two-level conventional converters SVPWM considers a complex voltage vector as the reference waveform to follow. This reference signal (uref ) is sampled with a constant frequency and t he converter generates it using a linear combination of possible state vectors. So, the modulation technique samples the reference signal and looks for the three neares t state vectors determining their three duty cycles respectively [51]. Hence, the output signal achieved by the converter is equal to the reference signal average d over a sampling period. In order to illustrate SVPWM method, in Figure 4.10 the reference voltage ( uref ) is generated thanks to carry out a linear combination of the three nearest vectors (100, 110 and 000 or 111).

Figure 4.10. Reference vector synthesis using the three nearest state vectors in the control region The state vectors space increasing the number of levels of the converter can be determined in the same way that two-level converter control region was calculated [53]. For instance, the state vectors space for a five-level DCC is shown in Figure 4.11. In this case, there are 27 possible different state vector s and they are also placed in the ab plane forming two concentric hexagons. Only 19 different positions in the ab plane cover the 27 different state vectors and therefore, there are 8 redundant vectors in five-level DCC state vectors space. Figure 4.11. State vectors space for five-level DCC

It is easy to determine the state vectors space for N-level DCC and it is shown in Figure 4.12. It is clear that increasing the number of levels, new and concentri c hexagons appear. Besides, the redundancy of the vectors increases if the state vectors are close to the origin. Increasing the number of levels in the DCC, the number of triangular sectors that compose the total control region increases and the search for the three nearest state vectors increases its difficulty. Several generalized modulation algorithms for multilevel converters have been recently proposed [53]-[63]. An effective approach that drastically reduces the computational load using a decision-making algorithm was presented in [64]. The proposed method was based on the decision-based pulse width modulation introduced in [65]. As it was said before, any modulation algorithm has to carry out two different tasks. The first one is to identify the three nearest state ve ctors to the reference vector. After that, the modulation algorithm has to calculate e ach state vector duty cycle. Figure 4.12. State vectors space for N-level DCC

One of the most important contributions of [64] is that the normalised reference voltage vector u* is transformed into uflat scaling u* imaginary part and multiplying it by 1 . The modulation algorithm input is the normalised 3 reference voltage vector. The normalisation depends on the number of levels of the multilevel converter and the voltage level value of the DC-link capacitors. Using the proposed transformation, multilevel converter state vectors space is flattened. The state vectors space after the transformation is a hexagon where a ll the sectors are separated by 45 lines. This property is very useful due to the fa ct that the modulation algorithm can easily find out the triangular sector where uf lat is pointing to by comparing their real and imaginary parts. This transformation drastically reduces the modulation algorithm computational cost doing it very fast and efficient. The state vectors space before and after the transformation is shown in Figure 4.13. Figure 4.13. The state vectors space is flattened multiplying by 1 the 3 imaginary part of the reference vector making the search for the nearest state vectors very simple and fast

In [64], the first problem is solved for the reference vector in the first sexta nt. However, this reference vector can be located in any of the six sectors of the regular hexagon which contain the switching state vectors. This problem was solved rotating the reference vector anti-clockwise by an angle (n-1)p/3, where n is the sextant number, n = 1, ,6. This rotation displaces any reference vector to the first sextant to be studied there. This algorithm clearly improves the resul ts of previous modulation algorithms due to the fact that its simplicity is very high. Nevertheless, there are several complex operations as the rotation to the first sextant and the inverse rotation to obtain the final switching sequence and the final on-state durations. In order to eliminate these complex operations, a new and faster modulation algorithm was proposed in [66]. On the same way, the state vectors space is flattened in order to achieve 45 lines but online calculations are reduced due to the fact that the modulation algorithm implies only very simple calculations. Th e modulation algorithm obtains the switching sequence and the duty cycles in the simplest way. This modulation algorithm based on geometrical considerations. One N-level state vectors space sector is shown in Figure 4.14. Each state vecto r is represented using the expression {x,y,z}. For example, if it is considered th e state vector {320}, that means that x=3 (phase a state is 3), y=2 (phase b state is 2) and z=0 (phase c state is 0). It can be easily determined x graphically. y can be calculated limiting vertical ly the region where the reference vector is pointing to. Thus, every reference vect or located in this state vectors space sector fulfils that z component is always ze ro. x = integer (uan+ubn) y=integer (2ubn) (4.1) z=0

u n=-u n+1 1 0.5 000 010 020 030 040 050 150 140 130 120 110 010 250 240 230 220 210 210 350 340 330 320 310 310 450 440 430 420 410 410 550 540 530 520 510 510 u n=-u n+2 u n=1 u n=0.5 u n=1.5 u n=2 u n u n Figure 4.14. N-level state vectors space sector Once x, y and z are determined, it is known that the reference voltage is pointi ng to a sub-region in this sector. Figure 4.15 shows a generic sub-region in zone 1 . This sub-region is divided in two different triangles. Figure 4.15. Sub-region of N-level state vectors space

It is necessary to know which is the triangle where the reference vector is foun d to determine the other states and the switching times. The condition that the reference vector should fulfill to be found in triangle number one is: u + y - x u - u < (yx) u < bn an bn an (4.2) It must be noticed that this modulation algorithm drastically reduces the online calculations due to the fact that the search for the nearest state vectors impli es only very simple calculations. The modulation algorithm obtains the switching sequence and the duty cycles in the simplest way. 4.3.2 Three-leg four-wire converters (3L4W) Three-phase converters connecting the neutral point of the load to the middle point of the DC-link bus are named three-leg four-wire systems (3L4W systems) and they were presented in chapter 2. A 3L4W two-level conventional converter is shown in Figure 4.16. Figure 4.16. Two-level 3L4W conventional converter

In 3L4W converters zero current can flow through the neutral wire and the phase currents could be not equilibrated. In this case, the g coordinate of the phasetoneutral voltages (VXN) could be not equal to zero and the state vectors space can not be represented only using the ab plane. Therefore, a three dimensional representation must be used in order to represent the state vectors space for 3L4W converters. Previous authors have represented the state vectors space for 3L4W converters using three dimensional abg coordinates [67]. It can be easily represented and f or instance, the state vectors space for two-level 3L4W conventional converters and five-level 3L4W DCC are shown in Figure 4.17 and Figure 4.18 respectively. Figure 4.17. State vectors space for two-level 3L4W conventional converters using abg coordinates

Figure 4.18. State vectors space for five-level 3L4W DCC In the three dimensional case, the reference voltage (uref ) must be generated carrying out a linear combination of the four nearest vectors. These nearest sta te vectors form a volume (a tetrahedron) and therefore 3D SVPWM algorithms have to find out the tetrahedron where the reference vector is pointing to. Afte r discovering the tetrahedron, the modulation algorithm knows the four nearest vectors (they are the vertexes of the tetrahedron) to carry out the linear combination of them in order to generate the reference vector averaged over a sampling period. An example of the reference vector generation in a five-level DCC is shown in Figure 4.19.

Figure 4.19. Reference vector generation using the four nearest vectors in a fiv elevel 3L4W DCC Using abg coordinates, the possible tetrahedrons that compose the state vectors space have different shapes and volumes. Several volume shapes appear and it is not easy to develop computationally efficient modulation algorithms to find out the tetrahedron where the reference vector is pointing to. In spite of it, some authors have developed 3D SVPWM algorithms using abg coordinates for 3L4W topologies [67]. But these algorithms are complex and their computational cost i s important. This is the fundamental drawback of this type of 3D SVPWM algorithms.

Therefore, it is necessary to change the representation way of the multilevel st ate vectors space. This is the reason because abc coordinates are used by other authors doing modulation algorithms more simple and more easily implemented [70]. In order to reduce the 3D SVPWM computational cost, 3L4W converters state vectors space can be represented using abc coordinates instead abg coordinates. The state vectors space for two-level 3L4W conventional converters is shown in Figure 4.20. Figure 4.20. State vectors space for two-level 3L4W conventional converters using abc coordinates It must be noticed that for 3L4W case, there are not redundant vectors because the state vectors are located in different positions. The 3L4W converter state vectors space increasing the number of levels can be done. For instance, the three-level 3L4W converter state vectors space is shown in Figure 4.21.

Figure 4.21. Three-level 3L4W converter state vectors space using abc coordinates Increasing the number of levels of the converter, the state vectors space for an Nlevel 3L4W converter forms a cube in the 3D-space. This cube is formed by a certain number of sub-cubes depending on the number of the levels of the converter. Only one sub-cube for two-level converters, eight sub-cubes for three level converters, twenty-seven sub-cubes for four-level converters. In general, (N-1)3 sub-cubes into the total cube, where N is the number of levels of the multilevel converter. Using abc coordinates, the modulation algorithm computational cost is lower than using abg coordinates. In fact, abc coordinates divide the volume control i n cubes doing easier and faster the search for the four nearest vectors to the reference vector. A fast and efficient generalized multilevel 3D SVPWM algorithm was presented in [70]. It is based on a generalization of 3D SVPWM

presented in [66] and it is the basis of other developed multilevel 3D SVPWM algorithms presented in this thesis. Besides, using [70] the number of switching commutations and the number of calculations to determine the switching sequence and the duty cycles are minimized. In this generalized modulation algorithm, the N-level generalization is done thanks to the reduction of the multilevel problem into a two levels one. This basic 3D SVPWM algorithm is based on several steps: Step 1: Calculate the coordinates of the sub-cube reference vertex where the reference vector is found. The multilevel control region is divided in several sub-cubes and the first step of the modulation algorithm is to find the sub-cube where the reference vector i s pointing to. Considering this sub-cube using abc coordinates and changing the origin coordinates to the nearest to (0,0,0) sub-cube vertex, the problem is reduced to a two level case because the two level control region is one sub-cube . For a certain reference vector in three-phase coordinates (uan, ubn, ucn), the i nteger part of each component (a,b,c) is calculated with uan, ubn, ucn {0,..., 2(N-1)}. a = integer (uan), b = integer (ubn), (4.3) c = integer (ucn), The coordinates (a,b,c) are the coordinates origin corresponding to the referenc e system of the sub-cube where the reference vector is pointing to. This sub-cube is exactly equal as the two-level state vectors space case. So, the multilevel case is reduced to a two levels case only calculating the factors a, b and c. This is sh own in Figure 4.22.

Figure 4.22. Sub-cube reference coordinates in generalized 3D SVPWM algorithms Step 2: Divide the sub-cube in several tetrahedrons. Once (a,b,c) coordinates are known, the algorithm calculates the four state vectors corresponding to the four vertices of the tetrahedron into the selected sub-cube where the reference vector is located. These vectors will generate the reference vector. The first option to divide the sub-cube was presented in [70]. Using this subcube division, the tetrahedron where the reference vector is located is easily found using comparisons with three 45 planes into the 3D space which define the six tetrahedrons inside the sub-cube. These tetrahedrons are shown in Figure 4.23. In [70], the diagram flow to find out the nearest four vectors is shown an d it is important to notice that they are calculated using a maximum of three

comparisons for calculating the suitable tetrahedron. The modulation algorithm i s so easy due to the 45 planes dividing the sub-cube. This space division is named SD45 in this work. But other sub-cube divisions can be considered. 3D SVPWM algorithms look for the best tetrahedron to generate the reference vector. The best solution is to use the tetrahedron where all the distances between the reference vector and the four state vectors are minimum. In fact, the ideal solution would be to increase infinitely the number of levels of the converter doing that the reference vector is always perfectly generated using only one state vector. So, minimizing the distances between the reference vector and the state vectors, the ripple of the resultant output signals will be minimized. Other planes can be used to divide each sub-cube and in this thesis, new division planes are presented. Four new planes are used to divide the sub-cube volume and resulting tetrahedrons are shown in Figure 4.24. In this case, five tetrahedrons compose the sub-cube volume where there is one central tetrahedron and four external ones. Five is the minimum number of tetrahedrons to compose the sub-cube. This fact is mathematically demonstrated in [1]. This new space division is named SD1.

Figure 4.23. Sub-cube division using 45 planes (named SD45 space division). Six tetrahedrons compose the total sub-cube volume

a c b 000 111 001 100 011 010 110 CASE 2 a c b 000 111 001 100 011 010 110 CASE 1 a c b 000 111 001 100 011 010 110 CASE 2 a c b 000 111 001 100 011 010 110 CASE 1 101 101 000 111b 000 111b CASE 4 CASE 3 010 010 110 011 110 011

100 a 100 a c 001 c 001 101 000 111001 101 b CASE 5 010 110 011 100 a c 101 Figure 4.24. Sub-cube division using new planes (named SD1). Five tetrahedrons compose the total sub-cube volume

Using the same notation described in [70], the flow diagram to find out the tetrahedron where the reference vector is pointing to using SD1 is shown in Figure 4.25. Once the tetrahedron is found, the state vectors to be used and the ir duty cycles can be determined using Table I. Normalized reference vector: (uan, ubn, ucn) a = integer (uan) b = integer (ubn) c = integer (ucn) r=u-a aan rb=ubn-b r=u-c ccn ra+rb-rc < 0 Yes No Yes Yes No No ra-rb+rc < 0 Case 4 ra+rb+rc > 2 Yes Nora-rb-rc > 0 Case 2 Case 5 Case 1 Case 3 Figure 4.25. Flow diagram to find out the tetrahedron where the reference vector is pointing to using space division SD1

More possible sub-cube divisions can be considered using SD1 but rotating them 90 over b axis. The obtained tetrahedrons (named space division SD2) are represented in Figure 4.26. In the same way that using previous 3D space divisions, other flow diagram can be defined to find out the tetrahedron where the reference vector is pointing to. The flow diagram for space division SD2 is shown in Figure 4.27. Step 3: Duty cycles calculation. The reference vector is generated by a linear combination of four state vectors determined in step 2. Sinj is the phase i state located in position j in the swi tching sequence and dj is the duty cycle j. The duty cycles calculation can be describe d using the following matrix expression. 111 SSS 1 an bn cn 222 San Sbn Scn 1 [ra rb rc 1] =[d1 d2 d3 d4] 333 SSS 1 an bn cn 4 44 SSS 1 an bn cn (4.4) R =DS D RS-1 i =i Using these equations, the modulation algorithm can determine the duty cycles. The final results using SD45, SD1 and SD2 are shown in TABLE 4.I, TABLE 4.II and TABLE 4.III respectively. These tables summarize the switching sequences and the duty cycles for all possible locations of the reference vector inside the two-level sub-cube.

a c b 000 111 001 100 011 010 110 CASE 9 a c b 000 111 101 001 100 011 010 110 CASE 6 a c b 000 111 101 001 100 011 010 110 CASE 7 a c b 000 111 001 100 011 010 110 CASE 8 a c b 000 111 001 100 011 010 110 CASE 9 a c b 000 111 101 001

100 011 010 110 CASE 6 a c b 000 111 101 001 100 011 010 110 CASE 7 a c b 000 111 001 100 011 010 110 CASE 8 101 101 a c b 000 111 001 100 011 010 110 CASE 10 101 Figure 4.26. Sub-cube division SD2. Five tetrahedrons compose the total subcube volume

Normalized reference vector: (uan, ubn, ucn) a = integer (uan) b = integer (ubn) c = integer (ucn) ra=uan-a rb=ubn-b rc=ucn-c Normalized reference vector: (uan, ubn, ucn) a = integer (uan) b = integer (ubn) c = integer (ucn) ra=uan-a rb=ubn-b rc=ucn-c Yes No Case 6 No Yes Yes No Case 7 r-rb-r< 0 ac Case 9 Yes No -ra+rb+rc > 1 r+rb-r> 1 ac r+rb+r> 2 ac Case 8 Case 10 Figure 4.27. Flow diagram to find the tetrahedron where the reference vector is pointing to using space division SD2

TABLE 4.I SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE TETRAHEDRON CASE USING SPACE DIVISION SD45 Tetrahedron State vectors sequence Duty cycles Case 1 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2 cn) = (a + 1, b, c) (S3 an, S3 bn, S3 cn) = (a + 1, b, c + 1) (S4 an, S4 bn, S4 cn) = (a + 1, b + 1, c + 1) d1= 1 -ra, d2= ra - rc, d3= -rb + rc, d4= - rb, Case 2 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2 cn) = (a, b + 1, c) (S3 an, S3 bn, S3 cn) = (a, b + 1, c + 1) (S4 an, S4 bn, S4 cn) = (a + 1, b + 1, c + 1) d1= 1 - rb, d2= rb - rc, d3= - ra + rc, d4= ra, Case 3 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2 cn) = (a, b, c + 1) (S3 an, S3

bn, S3 cn) = (a + 1, b, c + (S4 an, S4 bn, S4 cn) = (a + 1, b + 1, d1= 1 - rc, d2= - ra + rc, d3= ra - rb, d4= rb, Case 4 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2 cn) = (a, b + 1, c) (S3 an, S3 bn, S3 cn) = (a + 1, b + 1, (S4 an, S4 bn, S4 cn) = (a + 1, b + 1, d1= 1 - rb, d2= - ra + rb, d3= ra - rc, d4= rc, Case 5 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2 cn) = (a, b, c + 1) (S3 an, S3 bn, S3 cn) = (a, b + 1, c + (S4 an, S4 bn, S4 cn) = (a + 1, b + 1, d1= 1- rc, d2= - rb + rc, d3= - ra + rb, d4= ra, Case 6 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2

1)

c + 1)

c)

c + 1)

1)

c + 1)

cn) (S3 an, bn, cn) (S4 an, bn, cn) d1= d2= d3= d4=

= (a + 1, b, c) S3 S3 = (a + 1, b + 1, c) S4 S4 = (a + 1, b + 1, c + 1) 1- ra, ra - rb, rb rc, rc,

TABLE 4.II SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE TETRAHEDRON CASE USING SPACE DIVISION SD1 Tetrahedron State vectors sequence Duty cycles Case 1 (S1 an, S1 bn, S1 cn) = (a, b, c + 1) (S2 an, S2 bn, S2 cn) = (a + 1, b, c + 1) (S3 an, S3 bn, S3 cn) = (a, b + 1, c + 1) (S4 an, S4 bn, S4 cn) = (a, b, c) d1= -ra-rb+rc, d2=1-d1-d3-d4, d3= rb, d4= 1-rc, Case 2 (S1 an, S1 bn, S1 cn) = (a + 1, b, c) (S2 an, S2 bn, S2 cn) = (a + 1, b + 1, c) (S3 an, S3 bn, S3 cn) = (a + 1, b, c + 1) (S4 an, S4 bn, S4 cn) = (a, b, c) d1= ra-rb-rc, d2= 1-d1-d3-d4, d3= rc, d4= 1- ra, Case 3 (S1 an, S1 bn, S1 cn) = (a + 1, b + 1, c + 1) (S2 an, S2 bn, S2 cn) = (a + 1, b + 1, c) (S3 an, S3

bn, S3 cn) = (a + 1, b, c + (S4 an, S4 bn, S4 cn) = (a, b + 1, c + d1= ra+rb+rc-2, d2= 1-rc, d3= 1-d1-d2-d4, d4= 1-ra, Case 4 (S1 an, S1 bn, S1 cn) = (a, b + 1, c) (S2 an, S2 bn, S2 cn) = (a + 1, b + 1, (S3 an, S3 bn, S3 cn) = (a, b + 1, c + (S4 an, S4 bn, S4 cn) = (a, b, c) d1= -ra+rb-rc, d2= 1-d1-d3-d4, d3= rc, d4= 1-rb, Case 5 (S1 an, S1 bn, S1 cn) = (a + 1, b + 1, (S2 an, S2 bn, S2 cn) = (a + 1, b, c + (S3 an, S3 bn, S3 cn) = (a, b + 1, c + (S4 an, S4 bn, S4 cn) = (a, b, c) d1= 0.5 (ra+rb-rc), d2= 0.5 (ra-rb+rc), d3= 1-d1-d2-d4, d4=1-0.5 (ra+rb+rc),

1)

1)

c)

1)

c)

1)

1)

TABLE 4.III SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON THE TETRAHEDRON CASE USING SPACE DIVISION SD2 Tetrahedron State vectors sequence Duty cycles Case 6 (S1 an, S1 bn, S1 cn) = (a + 1, b, c + 1) (S2 an, S2 bn, S2 cn) = (a + 1, b + 1, c + 1) (S3 an, S3 bn, S3 cn) = (a, b, c + 1) (S4 an, S4 bn, S4 cn) = (a + 1, b, c) d1= ra-rb+rc-1, d2=1-d1-d3-d4, d3= 1-ra, d4= 1-rc, Case 7 (S1 an, S1 bn, S1 cn) = (a, b, c) (S2 an, S2 bn, S2 cn) = (a, b + 1, c) (S3 an, S3 bn, S3 cn) = (a, b, c + 1) (S4 an, S4 bn, S4 cn) = (a + 1, b, c) d1= 1-ra-rb-rc, d2= 1-d1-d3-d4, d3= rc, d4= ra, Case 8 (S1 an, S1 bn, S1 cn) = (a, b + 1, c + 1) (S2 an, S2 bn, S2 cn) = (a + 1, b + 1, c + 1) (S3 an, S3

bn, S3 cn) = (a, b + 1, c) (S4 an, S4 bn, S4 cn) = (a, b, c + 1) d1= -1-ra+rb+rc, d2= 1-d1-d3-d4, d3= 1-rc, d4= 1-rb, Case 9 (S1 an, S1 bn, S1 cn) = (a + 1, b + 1, c) (S2 an, S2 bn, S2 cn) = (a + 1, b + 1, c + 1) (S3 an, S3 bn, S3 cn) = (a, b + 1, c) (S4 an, S4 bn, S4 cn) = (a + 1, b, c) d1= -1+ra+rb-rc, d2= rc, d3= 1-ra, d4= 1-d1-d2-d3, Case 10 (S1 an, S1 bn, S1 cn) = (a + 1, b + 1, c + 1) (S2 an, S2 bn, S2 cn) = (a, b + 1, c) (S3 an, S3 bn, S3 cn) = (a, b, c + 1) (S4 an, S4 bn, S4 cn) = (a + 1, b, c) d1=0.5(-1+ra+rb+rc), d2=0.5(1-ra+rb-rc), d3=0.5(1-ra-rb+rc), d4=1-d1-d2-d3,

In order to compare SD45 and SD1 space divisions, the distances between the reference vector and the four state vectors that compose the tetrahedron where the reference vector is pointing to can be determined. These distances are named x1, x2, x3, and x4. In Figure 4.28, the distances xi using SD45 and SD1 are show n. Figure 4.28. Generation of the reference voltage using the four nearest state vectors using SD45 (a) and SD1 (b). The distances between the state vectors and the reference vector are different Depending on the used space division, the reference vector is generated using different state vectors. Mathematically, the reference vector is correctly generated using any space division but the distances xi change and consequently the ripple of the output signals also changes. The output current ripple is rela ted to the value of the distances xi. If these distances decrease, it means that the reference vector is generated with nearer state vectors and therefore the instantaneous error due to each state vector is lower. A merit figure can be defined in order to show xi distances in each case and what is the best solution depending on the reference vector location. This merit figure is defined as:

1111 F =+++ xx xx 1234 (4.5) 11 where if > 1000 = 1000 fori = 1...4 xx ii In order to pick out what is the best sub-cube division depending on the referen ce vector location inside the two-level sub-cube, F functions for both space divisions are calculated (FSD45 and FSD1). Finally, it is defined the function F T as the difference of FSD1 and FSD45. F = F - F (4.6) T SD 1 SD 45 FT can be determined for all possible locations of the reference vector in the s ubcube. In the control regions where FT is lower than zero, SD45 appears as the better solution. On the other hand, in the control regions where FT is greater t han zero, SD1 improves the ripple behaviour. In Figure 4.29, FT function is represented for several values of b coordinate in two-level sub-cube. It is clea r that inside the central tetrahedron defined by SD1, SD45 improves FT. However, in the outer parts of this central tetrahedron, SD1 improves the FT function. So , if the reference vector is located into the central tetrahedron, the best solution is to use SD45 space division and if the reference vector is outside central tetrahedr on, it is better to use SD1 space division.

Figure 4.29. Merit figure FT for several b coordinate values between 0 and 1. If FT is positive or negative, the distances between the reference vector and the state v ectors are smaller using SD1 or SD45 respectively Simulations have been carried out to show the SD1 performance. The simulated system is a four-leg four-wire three-level diode clamped converter connected to an RL load. The DC-Link voltage is equal to 1600 V, L=5 mH, R=22 O and the switching frequency is 5 kHz. The reference is a pure sinusoidal waveform with modulation index equal to 0.6875. Simulation results using SD45 and SD1 are shown in Figure 4.30 and Figure 4.31 respectively. It is clear that undesired an d unexpected ripple effects in the output phase currents using SD1 appear.

Figure 4.30. Output phase currents using SD45 for a three-level 4L4W DCC considering VDC=1600V, L=5mH, R=22 O and the modulation index m=0.6875. The reference voltage is a pure sinusoidal waveform and the switching frequency is 5 kHz Figure 4.31. Output phase currents using SD1 for a three-level 4L4W DCC considering VDC=1600V, L=5mH, R=22 O and the modulation index m=0.6875. The reference voltage is a pure sinusoidal waveform and the switching frequency is 5 kHz

Using SD1, the distortion in the output phase currents occur when the reference vector moves from a sub-cube (sub-cube 1) to an adjacent sub-cube (sub-cube 2). Adjacent tetrahedrons from both sub-cubes only have two common state vectors. In the transition between adjacent tetrahedrons, there is one not common state vector with non zero duty cycle that generates the reference vector. This is sho wn in Figure 4.32. In the figure, the not common state vector between adjacent tetrahedrons in adjacent sub-cubes is emphasized using a circle. The contributio n of this state vector to the output currents is completely different and undesire d ripple effects appear. Figure 4.32. Transition between adjacent sub-cubes using space division SD1. State vectors with non zero duty cycle create output current distortion

In order to avoid the presence of not common state vectors, adjacent sub-cubes i n the total control region are divided using SD1 and SD2 alternately. Using this configuration in the control region, adjacent tetrahedrons from adjacent subcubes have three common state vectors and in the transition instant, the fourth state vector has zero duty cycle. So, the movement between adjacent sub-cubes is done avoiding the presence of state vectors with non negligible duty cycles. Thi s space division is named SD12 and is represented in Figure 4.33. Figure 4.33. Adjacent sub-cubes in the total control region divided using SD1 and SD2 alternately (named SD12 space division) Considering the combination of the SD1 and SD2 control region division, the same simulations can be carried out. In Figure 4.34, simulation output phase currents results using SD12 space division are shown. It can be seen that the obtained results are very similar.

Figure 4.34. Output phase currents using SD12 space division generating a pure sinusoidal reference for a three level four-leg four-wire diode clamped converter considering VDC=1600V, L=5mH, R=22O and the modulation index m=0.6875. The reference voltage is a pure sinusoidal waveform and the switching frequency is 5 kHz As the obtained phase current results are similar at first sight, total harmonic distortion (THD) values are calculated using SD45 and SD12. THD using SD45 and SD12 space division are represented in Figure 4.35 and Figure 4.36 respectively showing that both space divisions achieve similar THD contents.

Figure 4.35. Obtained output phase current total harmonic distortion (% of fundamental) using SD45 space division Figure 4.36. Obtained output phase current total harmonic distortion (% of fundamental) using SD12 space division

Three dimensional generalized space vector modulation algorithms are discussed in this work. Two new space divisions and its related multilevel modulation algorithms are shown. Finally, the combination of two different sp