©2009 dj foreman cs552 operating systems z/390 basic assembler language programming
TRANSCRIPT
©2009 DJ Foreman
Architectures
• CISC Complex Instruction Set Computer
– Multiple operands per instruction– Multiple instruction formats– 64 bit architecture,
• Instr set is variable– 32-bit– 64-bit
• 32 bit instructions work on low-order• RISC – Reduced Instruction Set Computer– One (expressly written) operand per instruction– Accumulator is 2nd (implied) operand
Example 1: C=A+B;
• CISC (mainframe)
LOAD 5,A
ADD 5,B
ST 5,C
• RISC (PC)
LOAD A
ADD B
ST C
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RISC becomes MUCH more complicated if A, B & C are subscripted. CISC is easier, because CISC instructions can have subscript in an “index” register.
Example 2: A=B;A & B are strings 1<=length<=256
• MVCA(250),B Set -> A[0]
Set -> B[0]
Load index with max length of A
Load *A
Store *B
Increment pointers
Repeat 249 times
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Loop until max index
Elements of a machine -1• Registers
– Numbered hardware location (NOT memory)– Used for
• Addressing (like a pointer in C) • Arithmetic (just a simple accumulator)
– Number of registers varies with architecture– Size varies: 32, 64 or 128 bits– ALL registers may be accumulators
• Stack– A set of registers accessed in LIFO order
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Elements of a machine -2
• Memory– Linear set of addresses – Accessible to a program
• Devices– Mechanical objects – Accessible
• Directly by device number for assembler programs• Via special functions (e.g.; << and >> in C++)• Through a “device driver”
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What is Assembler Language?
• Short names for native machine codes
• Saves memorizing hexadecimal values
• One name generates one instruction
• E.g. for a pretend machine;– L x
• Loads the accumulator from memory “x”• “x” defined by programmer as a variable
– L 15,X• Loads register 15 from location “X”
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©2009 DJ Foreman
I/O & State
• Subchannels– Allow for variability of h/w path to device– Use a "control block" for access
• Program Status Word– Interruptability (on/off)– Privilege mode (on/off)– Wait state (on/off)– Next instruction
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Instruction Format Terms
• Op operation code (8 bits)• R1, etc. register number 0-F (8 bits)• B register used as address
base• X register used as an index• DDD 0-FFF 12-bit disp. from base• M,I 8-bit mask or immediate data• LL length of data (256 bytes
max)
Instruction formats• Following slides show each format 2 ways:
– Actual memory arrangement• As seen in a memory dump
– As written (with data names) in a program• L R1,mydata(R2)
• Known as: “Base-Displacement” notation
• BE CAREFUL, SYNTAX CAN BE CONFUSING!
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Op R1 R2 BDDD
Hexadecimal equivalent– As written (with code) in a program
• L R1,DDD(R2,B)• shown in some following slides
• Note that no actual data names are used in this version
• Same instruction example with real numbers– L 12,x’05e’(3,4)
• Add contents of reg’s 3 and 4 to displacement (5e) to get the actual address of data being loaded
• Note: no 0 in front of the x, quotes used instead©2009 DJ Foreman
Notation tricks• The assembler program (the “compiler”)
allows “substitutions” for numbers via an “EQU” instruction (really a “directive”)
• Examples:– R5 EQU 5– XYZ EQU X’5E’– DJ EQU 4095 (max value)
• Allows writing – L R5,XYZ(3,4) vs. L 5,X’4E’(3,4)– Just easier to write, no advantage in code
©2009 DJ Foreman
©2009 DJ Foreman
Base Register Specification• USING Tells assembler which register to use for names
– Register to use as Base– Generates NO code (takes no space in memory)
• Example:BALR 12,0 puts addr of "go“ into R12
USING *,12 go MVC Data1(5),Data2Data1 DC C'target location'Data2 DC C'Source'
• Data1 is 6 bytes from "go"– The * means: "starting here" and the MVC is 6 bytes long– Could have said: USING go,12
• If Reg 12 has address of "go", then data1 is 6 bytes from Reg 12• YOU must put the correct memory address into the Base Reg• DROP terminates use of a register for name addressability
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RR Format
• Example:AR 5,14
– Operation code is 1A– Adds the contents of Reg 14 to the contents of Reg 5– results in Reg 5– No memory references involved
• Note: examples show Regs as decimal values, but Assembler converts them to Hexadecimal
• In memory, this instruction looks like:1A5E
Op R1 R2
• Memory address is:– content of X– + content of B– + value DDD
• Example:– L Load – Operation code X'58'– L R,DDD(B,X)– L 4,mydata(12)
• Result replaces value in R– If "mydata" is at offset X'23' from Reg 5, which holds
X'0E00', then, in memory, this will look like:
584C5023– Mydata becomes a "starting point, and the content of Reg
12 is added to it as an "index" - nice for table accesses
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RX Format
Op R X BDDD
+
Arrows reverse for store operations
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RS Format
• Memory address:– content of B– + value DDD
• Example:– LM Load Multiple - Opcode X'98'– LM R1,R2,DDD(B)– LM 4,7,mydata
• Result: Loads all registers from R1 to R2, from data at "mydata"– If "mydata" is at offset X'23' from Reg 5, which
holds X'0E00', then, in memory, this will look like:
98475023– Note: "wrap-around" of register numbers is legal
• Ex: LM 14,12 loads regs 14, 15, 0,1,2,…,12 inclusive
Op R1 R2 BDDD
Arrows reverse for store operations
©2009 DJ Foreman
SI Format
• Performs "Op" using the instruction content itself (Imm) as data. That is, no additional memory reference is done.)
• Example:– N And Immediate - Opcode X'94'– N DDD(B),I– N mydata,X'0A'If "mydata" is at offset X'23' from Reg 5, which holds X'0E00',
then, in memory, this will look like:940A5023
Note: when writing the instruction, the memory ref comes 1st, FOLLOWED BY the Imm data!
Op Imm BDDD
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SS Format
• Memory address is:– + content of Bn
– + value DDDn
• Example:– MVC Move Characters - Opcode X'D2'
– MVC DDD1(B1,LL),DDD2(B2)
– MVC yourdata(23),mydata 23=X'17'
• Result replaces value in B1DDD1
– "mydata" is at offset X'02' from Reg 5 (X'0E00')– "yourdata" is at offset X'55' from Reg 8 (X'1F00')– then, in memory, this will look like:
– D21750028055
Op LL B1DDD1 B2DDD2
Additions
• A “word” is 32-bits, so a halfword is 16 bits
• Load and Store and math instructions can thus be used on 16-bit data, by appending the letter “H” to the opcode:– LH load halfword– STH store halfword– AH add halfword
• Results use low order half of register
• All registers are AT LEAST 32 bits©2009 DJ Foreman
©2009 DJ Foreman
Module Definitions
• CSECT - externally known module– Named or unnamed– Linkable object
• Could be a compilation result• Contains program code or data
• DSECT - externally known "dummy" module– Used to define offsets– Like a "C" 'struct‘, requires a pointer
• Both ended by another C/DSECT or END
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Storage Specification
• DC Define Constant– Hex, character, decimal formats– Contains the actual "constants"– Constants are NOT protected
• DS Define Storage– Allows for "reserving" an area– No pre-defined value, NOT zeroed out!!!
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Storage Specification 2• Op [m] {attrib1} [Ln] 'value1 ‘ note: quote signs• Op [m] {attrib2} [Ln] (value2) note: parentheses
– m is a repetition factor (0 is valid)– n is a length (per element)
• Attrib values– Attrib1 X, C, H, F, D ,B– Attrib2 A, S
• Value1 is any hex, integer or character data• Value2 is an address constant• Examples
DS 0CL5 uses no memory (so no quotes)
DC 3XL3'25' 000025000025000025
DC A(mydata) 4-byte, aligned, address
DC S(mydata) converts to base/disp notation
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Setting a Base Address
• Special instruction: BALR R1,R2
• At EXECUTION time, – R1 will receive the address of the NEXT inst
in memory following the BALR itself– A branch (jump) will be taken to the address
in R2 (call/return semantics)• IF R2 is register 0, no branch is taken!!!
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Naming• EQU "equates" a name to a location or value• Example:
– Data1 DC X'010203' length attr=1» Because no length was explicitly given
– Data2 DC XL3'010203' length attr=3– Hextwo EQU Data2+1– K5 EQU 5
– Hextwo now refers to the offset* of 02 inside Data2– BE CAREFUL: since the target of Hextwo is in a
string of length 3, hextwo has a length 'attribute' = 3– K5 has a numeric value of 5 - uses NO memory
– * from the current USING directive’s address
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Ending the Program Definition
• END – tells assembler "end of program"– Generates NO code. It is NOT a "return"
Comments• An * placed in column 1 of any line
– tells assembler "ignore this line"
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I/O
• Basic I/O instructions– SSCH Start Sub-Channel– TSCH Test " - clears pending
interrupts
• Operand (SSCH/TSCH) points to an ORB – Control block– Specifies additional info for I/O system
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ORB layout
Word# Usage
0 Interruption Parameter
1 Key SCMYFPIAU0HT LPM LD00000X
2 Channel-Program Address (address of 1st CCW in chain)
3 CSS Priority
Res CU priority
Res
4-7 Reserved
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I/O Programming
• Setup the ORB
• Setup the interrupt handler
• Setup address of NSI in PSW to be loaded
• Setup low memory – (I/O new & PGM new PSW's)
• SSCH
• Enable interrupts
• Wait for interrupt
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IBM Application ConventionsThese do NOT apply to kernel code
• All APPLICATION programs return to caller via Reg 14
• All programs save their caller's registers in an area pointed-to by Reg 13, STARTING WITH Reg 14
• Example:– STM 14,12,12(13)
• saves callers regs 14, 15, 0,1, 2…12 in an area addressed by Reg 13+12
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IBM Application conventions -2 Save Area Chaining
USING *,15 called via R15MYPG STM 14,12,12(13) save caller's regs
ST 13, mysave+4 my save ->caller’sLR 14,13 ptr to caller's areaLA 13,mysaveST 13,8(0,14) caller’s area-
>mineLA 12,MYPG change to R12USING MYPG,12 tell assembler L 13,MYSAVE+4 restore caller regsLM 14,12,12(13)BR 14 return to caller
MYSAVE DS 19F space for registersEND
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Macros
• Expand into actual inline code• Save writing and remembering• Allows for variable substitution• Allows for different expansion, based on
arguments– NOT a function call, – NOT a text substitution (as it is in C)
• It can generate DIFFERENT instructions oneach usage in a program
ExampleMACRO
&LBL SETCTL
&LBL STCTL C6,C6,SCRATCH
MVI SCRATCH+4,X'FF'
LCTL C6,C6,SCRATCH
MEND
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So XYZ SETCTLGenerates:XYZ STCTL C6,C6,SCRATCH
MVI SCRATCH,X’FFLCTL C6,C6,SCRATCH
Note: “SCRATCH” is 8 bytes
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Structure• Privileged
• No save-area chaining
• No "runtime" libraries
• Permitted access to ALL REAL memory
• Permitted access to REAL devices
• Two styles:– Monolithic - one complete linked file– Modular
• multiple files, • dynamically loaded files
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Reserved Memory
• Page 0 is Reserved storage for kernel
• Accessible only in privileged mode
• Uses base register 0 (in CISC machines)– reg 0 is "treated" by hardware as if = zero,
but CAN hold a number, which is ignored for addressing
• 4096 bytes (addresses 0-FFF)– Only needs 12 bits, no base register value
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Hex Address
Purpose(all PSW's: 8 bytes each)
0 Initial PSW
8 Initial CCW1
10 Initial CCW2
18-3F Old PSW's (Ext, SVC, Pgm, Mck, I/O)
58-7F New PSW's ( '' )
86-89 Interrupt codes (ext, svc, pgm) 2 bytes each
BC-BF I/O int parameter (4 bytes)
C0-FF Reserved
0100 1st possible byte of O/S or Program
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Boot Sequence• ROM forces an I/O read:
– 24 bytes from Cyl 0, Hd 0, Rec 0– Into loc 0, with chaining to loc 8 – These 24 bytes contain
• PSW 0 state vector w/Addr of 1st byte of pgm• CCW1 Read more data• CCW2 And more data
• CCW Chaining continues at loc 8• At end of data, PSW is loaded• Execution begins
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Program State Management
• LPSW - Load Program Status Word– Loads address of NSI– Sets privilege mode for NSI– Sets wait state on/off for NSI– Enables/disables interrupts for NSI– Sets memory protection mask for NSI
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VM Simulation
• Boot minidisk formatted as a CMS disk– Not a free-standing drive– Temp disk is usable
• O/S module created in CMS• O/S file copied to boot disk• Stand-Alone Program Loader (SAPL) installed
on boot using SAPIPL• When drive is booted, SAPL loads the O/S• O/S may then use any volumes (but must either
create a file system or use CMS file system
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What is VM?
• A virtual environment– Minidisks– Virtual devices (some are true simulations)– Spool management (prt, con)– Real-system resource mgr– Privilege-mode emulator for virtual machines– Allows a user to
• Invoke ALL real hw instructions in a program• Boot an O/S - existing or roll-your-own
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What is VM? - 2
• Two components– CP the Control Program or Hypervisor
• Does all real I/O, paging, scheduling• Manages virtual devices (disks, consoles, etc)
– CMS the "shell" that comes with VM• File system• Program management
– No multi-threading – No multi-programming
• Extensive s/w development & file mgmt commands
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Program creation
• Xedit text mode editor– Command line for issuing commands
• HLASM translates assembler source– Hlasm myos
• LOAD collects compiled files– Load myos (RLDSAVE– RLDSAVE keeps relocation dictionary in file for SAPL
• GENMOD link-edits the LOADed files– Gen myos
• Scripting language: REXX
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Booting your own system
• Define T3390 as vaddr cyl n• Format vaddr modeletter • Format vaddr modeletter n-1 (recomp• Salipl vaddr (origin xxxx mod myos• #CP IPL vaddr
– Need the #CP to avoid terminal type problems• Returning to the CMS shell
– #CP IPL CMS• Modeletter:
– A-Z, same as a PC– Defines path for files AND writeability of drive