©2009 – james r. morrison – ieee case 2009 – august 25, 2009 regular flow line models for...

©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009

Regular Flow Line Models for Semiconductor Cluster Tools:

James R. Morrison Assistant Professor - KAIST

Industrial & Systems Engineering

A Case of Lot Dependent Process Times

©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 2

Presentation Outline

• Motivation

• System description: Clustered photolithography tools & flow line model

• Recursions for wafer delay & extensions

• Computation

• Application to a clustered photolithography tool

• Concluding remarks


Motivation (1)

• Fab simulation is very commonly used in semiconductor mfg– Assess implications of changes to equipment & operations– Trade-offs between model fidelity/data collection and computation

• Existing fab-level simulation models– Simplified equipment representation is good for computation– Generally of adequate fidelity for most purposes– Detailed wafer robot models NOT used

• Industry trends: Render existing simulation models obsolete– Cluster tools have become increasingly more common– Anticipated 450 mm wafer era and/or many products

Image source: http://www.semiconductor-design.com/uploads/images/wafer.jpg


Motivation (2)

• Current equipment models do NOT well address – Internal wafers buffers & state dependent setups– These are common in photolithography clusters!

• Need expressive yet computationally tractable equipment models of semiconductor manufacturing equipment

• Goals– Develop models for cluster tools (clustered photolithography)– Expressive: Incorporate internal wafer buffers & setups, transient– Tractable: Ignore wafer transport robot & appeal to system structure– Practical: High fidelity when describing actual tool behavior

Image source: http://www.fabtech.org/


System Description: Clustered Photolithography

• Conceptual diagram of a clustered photolithography tool

• Internal wafer buffer may be present before/after the scanner• Setups are of two types

– Pre-scan track: Can start only after all of its modules are empty– Scanner: Setup starts once the first wafer arrives

ScannerP6

Pre-scan track

Post-scan track

Buffer

Buffer

Wafers

Enter

Wafers Exit

Wafer handling robots

P1

P1

P2

P2

P2

P3P4

P4P5

P7

P8

P8

P8

P9

P9P10

P11

P11

P11

Bottleneck

processProcess 2:

3 modules


System Description: Flow Line Model (1)

• Modeling relaxations– Ignore wafer transport robot except for addition to process time– Process 2 is modeled as 3 modules each with 1/3 original process time– Each buffer space modeled as a server with zero process time

• Process times are deterministic, but wafer class dependent– tj

k, for module j an d wafer class k (there are K classes)

• To enable the analysis, we make further assumptions– Restrictive, but as we will see, they still allow for high fidelity

…

Pre-scan track Buffer Scanner Post-scan track

Wafers

Enter

Wafers

Exit



• Let xj(w) := start time of wafer w in module mj

• Let aw := arrival time of wafer w to the queue • Assume wafers are served in a FIFO manner (this can be

relaxed easily)• There are M modules in the system

• Wafer advancement in the flow line obeys the elementary evolution equations

)()(

11

1)(11

21

)1(,)(max)(

)1(,)(max)(

)1(,max)(

wcMM

wcMMM

jwc

jjj

w

twxtwxwx

wxtwxwx

wxawx

FS: FullSimulation



• Assumption A1: Service times between wafer class

m1

tj1

m2 m3 m4

…mM-3 mM-2 mM-1 mM

m1

tjk

m2 m3 m4


tjk = k tj

1 , 0 < k < 1



• Definition: Dominating Modules. For each wafer, the modules that have strictly greater process time than all preceding modules

• Note: They are the same for all wafers by Assumption A1

• Definition: Channel. The modules including and between any two adjacent dominating modules

m1

tj1

m2 m3 m4




• Assumption A2: Service times in the channels decay geometrically in each channel at constant rate = 1*…*K

• This assumption guarantees that wafers will not experience contention unless all downstream modules are full

m1

tj1

m2 m3 m4


= 1/2


Recursions for Wafer Delay (1)

• Terminology:• dj(w) := delay wafer w experiences in module mj

• Y(w) := total delay wafer w experiences in channel-• S(w) := max delay wafer w can experience in channel-• xj(w) := start time of wafer w in module mj

• Key Result 1: Under Assumptions A1 and A2,

• where Y(0) = 0, a0 = -∞, d0(0) = 0, d1(0) = 0. Further,


Recursions for Wafer Delay (2)

• The following features can be incorporated:– Wafers arrive in batches called lots (batch arrivals – wafer lots)– Track setups – Setups at the bottleneck module (scanner)

• Key Result 2: The equations for each channel can be strung together to give recursions for the wafer delay in the entire flow line

• Features of the results– Don’t have to conduct full simulation (FS)

– Simply keep track of the state of each channel


Computational Complexity

• Key Result 3: Allow setups and batch arrivals of wafers – Let G be the number of lots, each with W wafers– Let B be the number of modules– Let K be the number of classes

– Computations for initialization

– Computations for recursions

Method # of Add # of MultFS 0 0

Result 1 K(K-1)(B-1) 0

Method # of Add # of MaxFS GWB-1 GWB-B

Result 1 27G+9G(W-2) 8G+2G(W-2)


Application to a Clustered Photolithography Tool (1)

• Let K = 20 classes of lots• W = 12 wafers/lot• B = 40 modules (about right for a clustered scanner with buffer)• Want to simulate the system for G wafer lots

• FS requires approximately 960G/145G = 6.6 times more computation

Method # of Add # of MultFS 0 0

Result 1 10898 0

Method # of Add # of MaxFS 480G-1 480G-40

Result 1 117G 28G

Computation for initialization Computation for recursion


Application to a Clustered Photolithography Tool (2)

• How good is the model when compared against data from a real tool?

• Throughput accurate to within 1%

• Cycle time accurate to within 4%

• Quite acceptable for use in fab level simulation


Concluding Remarks

• Semiconductor manufacturing environment & needs

– Increase in setups, product diversity & transient behavior

– Simulation is the tool of choice to assess changes at the fab level

– Simulation models do not well address such features in key tools

• Developed a flow line model for cluster tools

• Computationally, the method can be more efficient than full simulation for typical clustered scanners

• Future work

– Simplified models: Can we improve computation with minimal loss of fidelity?

©2009 – james r. morrison – ieee case 2009 – august 25, 2009 regular flow line models for...

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