2016-04-11 flyer high-q si-embedded 3d inductors...si-embedded-spiral-inductor solenoidal-inductor...
TRANSCRIPT
F R A U N H O F E R I N S T I T U T E F O R I N T E G R AT E D S Y S T E M S A N D D E V I C E T E C H N O L O G Y
HIGH-Q SI-EMBEDDED 3D INDUCTORSAir coils for power electronics
General description
A CMOS-compatible Si-embedded integra-
ted inductor concept with high-Q factor is
available to realize monolithic integration
of power converters for portable electro-
nics applications. The buried inductor is
fully insulated from the Si-substrate by an
oxide layer and can be manufactured with
electroplated Cu. The Si-embedded spiral
design suggests the highest Q-factor and
integration density.
Features
• Fully CMOS-compatible
• Monolithic integration along with active
electronics or silicon capacitors or as
stand-alone bare die
• Easy design of inductance and Q-factor
• Core less design suitable for operation
above 1MHz (fRes ≥ 300MHz*)
• Low parasitic capacitance, e.g. as low as
208fF*
1 D i ce d p lanar- s p i r a l
in du c t or s w i t h a i r co r e an d
A l w in d ing on S i - sub s t r at e
Fraunhofer Institute forIntegrated Systems andDevice Technology IISB
Schottkystraße 10
91058 Erlangen
Germany
Contact: PD Dr.-Ing. Tobias Erlbacher
Phone: +49 9131 761 319
Fax: +49 9131 761 360
www.iisb.fraunhofer.de
11
Advantages
• Considerably smaller footprint compared
to conventional inductors
• Higher Q-factor (Q > 200*) compared to
the planar RF inductors (Q = 7*)
• Lower power consumption of integrated
circuits (DF = 0.0045*)
• No polarization losses allow for faster
switching under high currents compared
to ferrite-based inductors
Benefits
• High-profit due to an innovative product
• Increased market volume from expanded
product options
• Reduced assembly effort by monolithic
integration
* for a 1µH inductor
1
Tech
nolog
yM
ater
ialCor
e
Area [
mm
2 ]Vo
lume [
mm
3 ]Ind
ucta
nce [
µH]
Induc
tanc
e den
sity [
nH/m
m3 ]
Serie
s res
istan
ce [Ω
]
Para
sitic
capa
citan
ce [f
F]
Reso
nanc
e fre
quen
cy [M
Hz]
Quality
facto
r at 5
MHz
Dissipa
tion
facto
r at 5
MHz
CU Air core
Planar-spiral on Si-surface
1.28 0.64 1.0 1562 0.20 10142 50 157 0.006
Multi-layer inductor
19.2 3.92 1.04 264 4.23 174 375 7.61 0.13
CU Ferrite core
24.2 5.19 1.10 212 0.16 208 333 221 0.005
Si-embedded spiral
CU Air core
1.28 0.64 0.06 8.75 0.20 181 5000 0.88 1.14CU Air core
Fig. 1 displays inductance density in terms of
quality factor for solenoidal-, toroidal- and
spiral-inductors.
Spiral-inductors are given in planar and
Si-embedded models. Number of turns in all
architectures is set to be 24.
2 D et a i l e d image of a h igh - Q p lanar-
s p i r a l in du c t or on a s i l i con sub s t r at e
Performance Characteristics
0 20 40 60 80 100 120 140
Quality factor
50
100
150
200
250
300
Inte
grat
ion
dens
ity (n
H/m
m3 )
Planar-Spiral-Inductor
Si-Embedded-Spiral-Inductor
Solenoidal-Inductor
Toroidal-Inductor
Soolenoidal Indu
Table 1 indicates key geometrical, technological and electrical parameters
of different inductor technologies
2 2