PAG. 25

Registration Information

Everything you need to know about registering

for the 2019 IEEE S3S Conference

PAG. 19

Educational Opportunities

Join us for our 25th Annual Short Course: FDSOI

Design and the Tuesday Tutorial RF Design

PAG. 4

Technical Program 2019 Selected and Invited Papers covering

a wide range of topics in the areas of SOI, 3D

Integration and low-voltage devices, circuits

and architectures

IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFEREN C E

45

2019

IEEE S3S Conference

ADVANCE PROGRAM

TABLE OF CONTENTS

General Chair’s Message

Short Course and Tutorial

Technical Program

Additional Agenda Items

Satellite Function

Hotel Information

Travel Information

Conference Registration

2019 Committee

SPONSORED BY

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OCIETY®

LECTRON

EVICES

IEEE S3S CONFERENCE 6930 De Celis Place, #36, Van Nuys, CA 91046

Telephone: (818) 795-3768 manager@s3sconference.org

Conference at a Glance 3

General Chair’s Message

The organizing committee and I are pleased to invite you to attend this year’s S3S conference and celebrate its 45th anniversary with a very rich technical program.

On its 45th anniversary, the S3S con-ference continues to grow and attract more attention from the industrial and academic arenas. This year, the 2019 IEEE SOI–3DI– Subthreshold (S3S) Microelectronics Technology Unified Conference is to be held October 14-17 at the Double-Tree by Hilton in San Jose, CA.

The race to develop the right tech-nology for the 5G and IoT markets is revolutionizing the semiconductor industry. With more than 20 billion smart connected devices expected by 2021, the demand on ultra-low power operation, 3D integration, mil-limeter-wave connectivity, computa-tional efficiency and design flexibility is going to unprecedented edges. These aspects of technology have been covered by the S3S conference for years, and this year is no excep-tion.

The organizing committee and I are pleased to invite you to attend this year’s S3S conference and celebrate its 45th anniversary with a very rich technical program. This year, we can see major players from the different stages of the value chain coming to present their state-of-the-art technol-ogies and solutions besides the most recent academic achievements in a highly dynamic domain. Connectivity is the main theme of the conference focusing on 5G and IoT, but also on technologies allowing this to happen, like AI, neural networks, 3D integra-tion, etc. This year’s conference features one plenary session and two keynote sessions, in order to accommodate 9 great speakers from the 4 corners of the semiconductor industry.

The opening plenary session on Monday morning features three must-attend talks:

Vida Ilderem Vice President, Intel Labs

Hans Stork, Senior Vice President and CTO, ON semi-

conductor

Yoon-Jong Lee, Senior Vice President and CTO, DB HiTek

Subramani Kengeri CTO and Vice President,

Worldwide Client Solutions, GLOBALFOUNDRIES

On Tuesday morning, we have the keynote session featuring:

Jon Cheek Executive Director, SOI Industry

Consortium

Tomasz Brozek PDF Fellow at PDF Solutions

And the third keynote session taking place on Wednesday morning where we have three inspiring talks by:

Andreia Cathelin Fellow at STMicroelectronics

Massimo Alioto Associate Professor,

National University of Singapore

Rob Cosaro Fellow, NXP Semiconductors

Along with these rich three keynote sessions, we have more than 80 invited and contributed presentations through two parallel tracks and not to forget the poster session on Monday evening. A Focus session is organized on Tuesday afternoon with the title FD-SOI Platforms and Products featuring 7 invited speakers from Renesas, NXP, ST, ARM, GF, Huali and VeriSilicon.

I highly recommend attending this session taking a deep dive in the technology nominated as the best candidate for IoT era.

After the regular three days sessions, a full short course is organized on Thursday entitled FDSOI Design. This year we have invited speakers from Dolphin Design, GF, Mentor Graphics, NXP, Soitec and Floadia Corp. Over the years, contributors and at-tendees of this conference have been coming with the open mind to share, collaborate and create new add-ed values through scientific, formal and informal discussions. We keep insisting on these values by promot-ing networking moments and social events. A welcome reception is organized on Monday evening along with the poster session followed by a Rump session were ideas will be challenged on AI at the Edge: Driving the Next Wave of Semiconductor Growth or Yet Another Hype. Tuesday evening, we all share a cook-out informal dinner. As much as the technical sessions are important, do not miss these moments of net-working and connection.

Finally, I take the liberty to sincerely thank the organizing committee and the conference manager for all the hard work and effort to put together this year’s fantastic conference.

Looking forward to seeing you all at the DoubleTree by Hilton in San Jose, CA on Monday Oct 14th.

Mostafa Emam 2019 General Chair

8:00 AM

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12:40 PM

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8:30 AM

11:00 AM

12:20 PM

1:30 PM

3:30 PM

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8:30 AM

11:00 AM

12:20 PM

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5:00 PM

8:00 AM

12:45 PM

1:45 PM

Keynote Session: FDSOI Ecosystem

Tuesday Tutorial : RF Design

Tuesday, October 15th

2019 Conference at a GlanceMonday, October 14th

Plenary Session

Session 2: RFSOI Session 3: Negative Capacitance Devices

3DVLSI Open Workshop

FDSOI Design Short Course

Lunch (on own)

Session 4: 3D Integration

2019 Confernece "Cook Out"

Session 5: FDSOI Devices

Session 6: Process Technology for 3D Integration Session 7: Materials, Devices and Circuits for Neural Networks

Session 8: Poster Session and Welcome Reception

Rump Session:AI at the Edge: Driving the Next Wave of Semiconductor Growth of Yet Another Hype

Wednesday October 16th

FDSOI Design Short Course (cont)

Session 10: Embedded Memories

Focus Session: FDSOI Platforms and Products II

Focus Session: FDSOI Platforms and Products I

Session 11: Modeling and Simulation

Lunch (on own)

Lunch (provided with Short Course)

Thursday, October 17th

Session 15: 3D Technology

Session 17: Tunnel FETs

Session 20: Advance Devices II

Keynote Session: Low-Power Circuits

Session 16: FDSOI Circuits

Lunch (on own)

Session 18: Advanced Materials and Transistors

Session 19: Advanced Devices I

Awards and Closing Remarks

Advance Program 3 2019 IEEE S3S Conference

7:00AM CONTINENTAL BREAKFAST

MONDAY OCTOBER 14, 2019

10:40AM BREAK

11:00AM SESSION 2: RFSOI

Technical Program

1.01 5G: Ultra Reliable and Low Latency CommunicationVida Ilderem; Vice President, Intel Labs and Director, Wireless Communications Research; Intel, USA (Plenary Speaker)

1.02 Technology Requirements of Power Constrained Sensor and Connectivity ApplicationsHans Stork; Senior Vice President and Chief Technology Officer, ON Semiconductor, (Plenary Speaker)

1.03 Highly Resistive Substrate (HRS) as an Alternative to SOI for RF Front-End ApplicationsYoon-Jong Lee; Senior Vice President and Chief Technology Officer (CTO) at DB HiTek, Korea (Plenary Speaker)

2.02 Buried Oxide on Extended Drain MOSFET (BOX EDMOS) for RF Applications in FDSOI/Bulk Technology

Aliaksei Ivaniukovich1, Kwan Young Kim1, Wooyelo Maeng2, HuiChul Shin2, KangWook Park2, Yoon-Suk Kim1, UiHui Kwon1, Dae Sin Kim1; 1CAE, Semiconductor R&D Center Samsung Electronics, Hwaseong-si, South Korea, 2PA1, Foundry Business Samsung Electronics, Yongin-si, South Korea

2.01 A 28GHz SPDT TRx Switch with 9KV ESD Protection in 22nm SOI CMOS for 5G Mobiles Feilong Zhang1, Cheng Li1, Chenkun Wang1,2, Mengfu Di1, Zijin Pan1, David Harame3 and Albert Wang1; 1Department of Electrical and Computer Engineering, University of California, Riverside, CA USA, 2Marvell Semiconductor, USA, 3 GlobalFoundries, USA

8:00AM SESSION 1: PLENARY SESSION

1.04 Challenges And Opportunities In Transition To 5GSubramani Kengeri; Chief Technology Officer and Vice President of World Wide Client Solutions; GlobalFoundries, San Jose, CA, USA (Plenary Speaker)

Advance Program 4 2019 IEEE S3S Conference

Technical Program

SESSION 3: NEGATIVE CAPACITANCE DEVICES

2.05 A 3.2-3.6GHz SOI-LDMOS Dual-Input Doherty Power Amplifier Saad Boutayeb1, Ayssar Serhan1, Pascal Reynier1, Damien Parat1, Alexis Divay1, Jen-Daniel. Arnould2, Estelle Lauga-Larroze2, Alexandre Giry1; 1CEA LETI, MINATEC Campus Univ Grenoble Alpes Grenoble, France, 2RFIC-Lab Univ Grenoble Alpes, Grenoble, France

3.02 Evaluating Negative Capacitance Technology for RF MOS Varactors Girish Pahwa1 , Amit Agarwal2 and Yogesh Singh Chauhan1; 1Department of

Electrical Engineering, Indian Institute of Technology, Kanpur, India, 2Department of Physics, Indian Institute of Technology Kanpur, Kanpur, India

3.01 HfZrO Ferroelectric Characterization and Parameterization of Response to Arbitrary Excitation Waveform

Md Nur K. Alam1,2, M. Thesberg3, B. Kaczer1, Ph. Roussel1, B. Vermeulen1,4, B. Truijen1, M. I. Popovici1, L.-Å. Ragnarsson1, A. S. Verhulst1, N. Horiguchi1, M. Heyns1,2, and J. Van Houdt1,5; 1IMEC, Leuven, Belgium, 2Department of Materials Engineering, K. U. Leuven, Belgium, 3TU Wien, Vienna, Austria, 4Laboratorium voor Halfgeleiderfysica, K. U. Leuven, 5ESAT, K. U. Leuven

12:40PM LUNCH (ON OWN)

2.04 28 FDSOI RF Figures of Merit down to 4.2 KL. Nyssens1, A. Halder1, B. Kazemi Esfeh1, N. Planes2, D. Flandre1, V. Kilchytska1,J.-P. Raskin1; 1ICTEAM, Université catholique de Louvain, Louvain-la-Neuve,Belgium, 2ST, ST-Microelectronics, Crolles, France

3.03 Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications Manish Gupta and Vita Pi-Ho Hu; Department of Electrical Engineering, National Central University, Taoyuan, Taiwan R.O.C.

2.03 Linear and Efficient NFET-MESFET 5G Cascode Power Amplifiers Using 45nm SOI CMOS

Trevor J. Thornton1, Chaojiang Li2, Payam Mehr1; 1Arizona State University, Tempe AZ, USA, 2GlobalFoundries USA, Essex Junction, VT, USA

3.04 Ferroelectric HfO2: A High Density, Nonvolatile Memory Solution for Changing Computing Requirements

Ava J. Tan; Department of Electrical Engineering & Computer Sciences, University of California, Berkeley USA (Invited Speaker) Ava J Tan, Korok Chatterjee, Jiuren Zhou, Daewoong Kwon, Yu-Hung Liao, Chenming Hu, Sayeef Salahuddin; Department of Electrical Engineering and Computer Science University of California Berkeley, USA

Advance Program 5 2019 IEEE S3S Conference

Technical Program

1:30PM SESSION 4: 3D INTEGRATION

4.03 Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO2 Hybrid Bonding

Yuki Honda1, Msahide Goto1, Toshihisa Watabe1, Msakazu Nanba1, Yshinori Iguchi1, Takuya Saraya2, Msaharu Kobayasi2, Eji Higurashi3, Hroshi Toshhiyoshi1, Tshiro Hiramoto1; 1NHK STRL, Tokyo, Japan, 2The University of Tokyo, Tokyo, Japan, 3AIST, Tsukuba, Japan

4.04 TSV with Embedded Capacitor for ASIC-HBM Power and Signal Integrity Improvement Anak Agung Alit Apriyana, Lin Ye, Tan Chuan Seng; School of Electrical and Electronic Engineering, Nayang Technological University, Singapore

4.02 DBI-Enhanced Architectures Advancements in the Die-to-Wafer DBI Production Process and it’s Impact on Performance

Javi DeLaCruz; Vice President Engineering, Xperi Corporation, San Jose, CA, USA (Invited Speaker)

4.05 Heterogeneous Multi-Dimensional Integrated Circuit for Internet-of-Things ApplicationNazek El-Atab1, Sohail F. Shaikh1, Sherjeel Khan1, Joho Yun1, Muhammad Mustafa Hussain1,2; 1mmh Labs, Computer, Elecctrical and Mathematical Sciences and Engineering Division King Abdullah University of Science and Technology Thuwal, Saudi Arabia, 2Electrical Engineering and Computer Science, University of California, Berkeley California, USA

4.01 Advances in 3D Heterogeneous Structures and Integration for Future ICs Albert Wang; University of California, Riverside, CA, USA (Invited Speaker) Ceng Li, Feilong Zhang, Mengfu Di, Zijin Pan and Albert Wang; Dept. of Electrical and Computer Engineering, University of California, Riverside, CA, USA

SESSION 5: FDSOI DEVICES

5.01 Low-Frequency Noise Transistor Performance for UTBB FDSOI MOSFET-C Filters L. Van Brandt1, B. Kazemi Esfeh1, N. Planes2, V. Kilchytska1, D. Flandre1; 1ICTEAM,Université catholique de Louvain, Louvain-la-Neuve, Belgium, 2ST-

Microelectronics, Crolles, France

5.02 Subthreshold Operation of Self-Cascode Structures Using UTBB FD SOI Planar MOSFETs Lígia Martins d’Oliveira1, Valeriya Kilchytska2, Nicolas Planes3, Denis Flandre2, Michelly de Souza1; 1Centro Universitário FEI – São Bernardo do Campo, Brazil, 2Université catholique de Louvain: ICTEAM – Louvain-la-Neuve, Belgium, 3ST-Microelectronics – Crolles, France

Advance Program 6 2019 IEEE S3S Conference

Technical Program

3:30PM BREAK

3:40PM SESSION 6: PROCESS TECHNOLOGY FOR 3D INTEGRATION

5.04 Optimization of Photoelectron In-Situ Sensing Devices in FD-SOI J. Liu1, M. Arsalan1, A. Zaslavsky2, S. Cristoloveanu3 and J. Wan1; 1State key labof ASIC and System, School of Information Science and Engineering, FudanUniversity, Shanghai, China, 2Department of Physics and School of Engineering,Brown University, Providence, RI, USA, 3IMEP-LAHC, INP-Grenoble/Minatec, Grenoble 38016, France

5.03 Degradation of Sub-Threshold Slope in Ultra-Scaled MOSFETs due to EnergyFiltering at Source ContactJ. Saltin1, N. C. Dao2, P. H. W. Leong2, and H. Y. Wong1; 1EE, San Jose StateUniversity, Electrical Engineering, USA, 2The University of Sydney, Australia

5.06 Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS “PNBody-Tied SOI-FET” and Proposal of CMOS without Vsub Bias

Wataru Yabuki1, Jiro Ida1, Takayuki Mori1, Koichiro Ishibashi2 and Yasuo Arai3; 1Division of Electrical Engineering, Kanazawa Institute of Technology, Nonoichi, Ishikawa Japan, 2The University of Electro-Communications, Tokyo Japan, 3High Energy Accelerator Research Org., KEK, Tsukuba Japan

5.05 Soft Error Tolerance of Standard and Stacked Latches Dependending on Substrate Bias in a FDSOI Process Evaluated by Device SimulationKentaro Kojima, Jun Furuta, and Kazutoshi Kobayashi; Kyoto Institute of Technology, Japan

6.02 Crystal Growth Study of the Grain-Boundary Free (100) Textured Si Thin-Films by Using the CW-Laser Lateral CrystallizationNobuo Sasaki1,2,3, Muhammad Arif2, Yukiharu Uraoka2, Jun Gotoh3,and Shigeto Sugimoto3; 1Sasaki Consulting, Kawasaki Japan, 2Div. Mat. Sci., NAIST, Ikoma Japan, 3V-Technology Co., Ltd., Yokohama Japan

6.01 Stack up Your Chips: Betting on 3D Integration to Augment Moore’s Law Scaling

Saurabh Sinha; ARM, Austin Texas (Invited Speaker) Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline and Greg Yeric; Arm Research, Austin, Texas

6.03 Current Low Volume 3DIC Production: Yields, Concerns and RealitiesRobert Patti; NHanced Semiconductors, Inc, Chicago Illinois (Invited Speaker)

Advance Program 7 2019 IEEE S3S Conference

Technical Program

SESSION 7: MATERIALS, DEVICES AND CIRCUITS FOR NEURAL NETWORKS

7.03 Design and Study of an Artificial Spiking Neuron Enabled by Low-Voltage SiOX-based ReRAM

Jessie XuHua Niu, Yida Li, Hasita Veluri, and Aaron Voon-Yew Thean; Department of Electrical and Computer Engineering, National University of Singapore, Singapore

7.01 Optoelectronics with Oxides and Oxide Heterostructures Alex Demkov; University of Texas, Austin, Texas (Invited Speaker)

7.04 Mixed-Signal Neuromorphic Processors: Quo Vadis? Mohammad Bavandpour, Mohammad Reza Mahmoodi, Shubham Sahay, Dimitri B. Strukov; ECE Department UC Santa Barbara, Santa Barbara, CA, US

7.02 MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal- Resistance Sensing Mechanism for Ternary Neural Network Hardware Masanori Natsui and Takahiro Hanyu; Research Institute of Electrical Communication, Tohoku University, Japan

6:00PM SESSION 8: POSTER SESSION AND RECEPTION

8.01 Impact of Furnace Annealing and Other Process Failures to Be Taken Care During Fabrication of an AlGaN/GaN MOSHEMT Arathy Varghese, Chinnamuthan Periasamy, Lava Bhargava; Department of Electronics and Communication Malaviya National Institute of Technology, Jaipur, India

6.05 Double SOI substrates for Advanced Technologies W. Schwarzenbach, G. Besnard, G. Chabanne, B.-Y. Nguyen; SOITEC, ParcTechnologique des Fontaines, Bernin, France

6.04 Laser Processing For 3D Junctionless Transistor FabricationD. Bosch1,2, P. Acosta Alba1, S. Kerdiles1, V. Benevent1, C. Perrot3, J. Lassarre1, J.Richy1, J. Lacord1, B. Sklenard1, L. Brunet1, P. Batude1, C. Fenouillet-Béranger1,D. Lattard1, J. P. Colinge1, F. Balestra2, F. Andrieu1; 1CEA-LETI, Univ. GrenobleAlpes, France, 2Univ. Grenoble Alpes,CNRS, Grenoble INP, IMEP-LAHC, France,3STMicroelectronics, Crolles

7.05 Materials and Device Research for Advanced Logics and Memory Technologies Wilman Tsai; TSMC Corporate Research, San Jose, CA (Invited Speaker)

Advance Program 8 2019 IEEE S3S Conference

Technical Program

8.05 Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias inThick Front Gate Oxide FDSOI MOSFETs Chetan Kumar Dabhi 1, Pragya Kushwaha2, Harshit Agarwal2, Sarvesh S. Chauhan1, Chenming Hu2, and Yogesh Singh1; 1Chauhan Department of Electrical Engineering, Indian Institute of Technology Kanpur, India, 2University of California, Berkeley, USA

8.06 High Temperature Reliability Studies of Innovative Fuse Programming ModeShine Chung1, Wen-Kuan Fang1, Michael Wendt2, Heng-Kah Lee2; 1Attopsemi Technology, Hsinchu,Taiwan,2GlobalFoundries, Dresden, Germany

8.07 A Line TFET Design Employing Tri-Line-Gate Architecture and U-Shaped Pockets for Minimizing Drain Field EffectsAshita1, Sjad A. Loan2, Mohammad Rafat2; 1Dept. of Applied Sciences and Humanities, Jamia Millia Islamia, New Delhi, India, 2Dept.of Electronics and Communication Engineering Jamia Millia Islamia, New Delhi, India

8.08 Impact of Gate Oxide Traps and In0:53Ga0:47 As/BOX traps on the Performance ofIn0:53Ga0:47 As on insulator TFET and its MitigationMohd Haris, Sajad Loan, Mainuddin; Electronics and CommunicationJamia Millia Islamia, New Delhi, India

8.09 Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFETPragya Kushwaha1, Harshit Agarwal1, Varun Mishra1, Avirup Dasgupta1, Yen- Kai Lin1, Ming-Yen Kao1, Yogesh Singh Chauhan2 , Sayeef Salahuddin1, and Chenming Hu1 ; 1Department of Electrical Engineering and Computer Science University of California Berkeley, USA, 2Department of Electrical Engineering Indian Institute of Technology, Kanpur, India

8.04 A Physical Modeling Study of Mobility Enhancement in Stressed Ge-on- insulator pMOSFET Haoqing Xu1,2, Guilei Wang1, Jiaxin Yao1,2, Huaxiang Yin1,2, Henry Radamson1, and Zhenhua Hu1; 1Integrated Circuit Advanced Process Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, 2University of Chinese Academy of Sciences, Beijing, China

8.03 Investigating the Scalability of Nanowire Junctionless Accumulation Mode FETs using an Intrinsic Pocket

Aakash Kumar Jain, Jaspreet Singh, Mmidala Jagadesh Kumar; Department of Electrical Engineering Indian Institute of Technology Delhi, New Delhi, India

8.02 Optimization of the Back Enhanced SOI MOSFET Working as a Charge-Based BioFET SensorL. S. Yojo1, R. C. Rangel1,2, K. R. A. Sasaki1, C. A. Mori1 and J. A. Martino1; 1LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil, 2FATEC-SP, Faculdade deTecnologia de Sao Paulo, Sao Paulo, Brazil

Advance Program 9 2019 IEEE S3S Conference

8.13 Study of Layout Dependent Radiation Hardness of FinFET SRAM using Full Domain 3D TCAD Simulation Khoa Huynh1, Johan Saltin1, Jin-Woo. Han2, Meyya Meyyappan2, Hiu Yung Wong1; 1Electrical Engineering, San Jose State University, San Jose, USA, 2Exploration Technology, NASA Ames Research Center, Moffett Field, USA

8:00PM RUMP SESSION: AI AT THE EDGE:

DRIVING THE NEXT WAVE OF SEMICONDUCTOR GROWTH OR YET ANOTHER HYPE

8.14 Design and Simulation of High Performance Dopingless Tunnel Diode Faisal Bashir1, Asim Majeed2, Farooq A. Khanday1, M. Tariq Banday1; 1Department of Electronics and Instrumentation Technolgy, University of Kashmir, Srinagar, India, 2Computer Department, College of Science, University of Kirkuk, Bagdad, Iraq

8.15 Negative Capacitance GaN HEMT with Improved Subthreshold Swing and TransconductanceKM. Zhu, JH. Wei, J. Wan; State key lab of ASIC and System, School of Information Science and Engineering, Fudan University, Shanghai, China

8.12 OTA Performance Comparison Designed with Experimental NW-MOSFET and NW-TFET Devices Alexandro de M. Nogueira1, Paula G. D. Agopian1,2, Roberto Rangel1, Joao A. Martino1, Eddy Simoen3, Rita Rooyackers4, Cor Claeys5, Nadine Collaert3; 1LSI/PSI/ USP, University of Sao Paulo, Sao Paulo, Brazil, 2UNESP, Sao Paulo State University, Sao Joao da Boa Vista, Brazil, 3Imec, Leuven, Belgium, 4ClaRoo, Leuven, Belgium, 5E.E. Dept, KU Leuven, Belgium

8.11 TFET based 1T-DRAM: Physics, Significance and Trade-offs Nupur Navlakha, Md. Hasan Raza Ansari, and Abhinav Kranti; Low Power Nanoelectronics Research Group, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Simrol, Indore, India

8.10 Edge Inference with NEM RelaysRawan Naous, Vladimir Stojanović; EECS Department University of California, Berkeley, Berkeley, USA

Technical Program

8.16 P-type Negative Capacitance FinFET with Subthreshold Characteristics and Driving Current Improvement Zhaohao Zhang1, Qingzhu Zhang1, Zhaozhao Hou1,2, Gaobo Xu1, Qiuxia Xu1, Huxiang Zhu1,2, H. Yin1,2; 1Key Laboratory of Microelectronic Devices and Integrated Technologies, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, 2University of Chinese Academy of Sciences, Beijing, China

Advance Program 10 2019 IEEE S3S Conference

TUESDAY OCTOBER 15, 2019

7:00AM CONTINENTAL BREAKFAST

11:00AM SESSION 10: EMBEDDED MEMORIES

10:40AM BREAK

Technical Program

9.01 Accelerating Industry Adoption of SOI Against a Backdrop of a Slowing Moore’s LawJon Cheek; Engineering Manager; NXP Semiconductors, Cedar Park, Texas (Keynote Speaker)

9.02 Characterization Challenges and Solutions for FDSOI TechnologiesTomasz Brozek; PDF Fellow; PDF Solutions, San Jose, CA, USA (Keynote S peaker)Tomasz Brozek1, Meindert Lunenborg2, Franck Arnaud3, Roberto Gonella3, Jean-Christophe Giraudin3, Christian Dutto3, Bertrand Martinet3, Laurent Garchery3, Christopher Hess1, Kelvin Doong4; 1PDF Solutions, Santa Clara, CA, 2PDF Solutions, Montpellier, France, 3ST Microelectronics, Crolles, France, 4PDF Solutions, Hsinchu, Taiwan

10.02 A 64x1 Fuse Memory with 0.4V/1μA Read and 0.9V Program Voltage on 22nm FD-SOI Shine Chung and Wen-Kuan Fang; Attopsemi Technology, Hsinchu, Taiwan

10.03 A ReRAM Memory Compiler with Layout-Precise Performance Evaluation Edward Lee, Daehyun Kim, Venkata Chaitanya Krishna Chekuri, Yun Long, Saibal Mukhopadhyay; Georgia Institute of Technology, Atlanta, USA

10.01 Preliminary Results of a Novel Low Voltage M-OTP in MOS Transistor in 28nm FD-SOI P. Galy1,3, M. Bawedin2 and R. Lethiecq1,2; 1STMicroelectronics, Crolles Cedex,France, 2Univ. Grenoble Alpes, IMEP-LAHC, Grenoble INP Minatec, CNRS, Grenoble,France, 33IT, Universite de Sherbrooke, Canada

8:30AM SESSION 9: KEYNOTE SESSION: FDSOI ECOSYSTEM

Advance Program 11 2019 IEEE S3S Conference

SESSION 11: MODELING AND SIMULATION

Technical Program

11.02 A Ring Oscillator Using Bootstrap Inverter Akinori Yamamoto, Trong-Thuc Hoang and Cong-Kha Pham; Department of Information Science and Technology, University of Electro-Communications, Chofu, Tokyo, Japan

11.03 From 180nm to 7nm: Crosstalk Computing Scalability Study Md Arif Iqbal, Naveen Kumar Macha, Bhavana Tejaswini Repalle, Mostafizur Rahman; Computer Science & Electrical Engineering, University of Missouri, Kansas City, Kansas City, Missouri

11.01 Thermal Noise-Induced Error Simulation Framework for Subthreshold CMOS SRAM Elahe Rezaei1 , Marco Donato2, William Patterson 1, Alexander Zaslavsky 1, R. Iris Bahar1 ; 1School of Engineering, Brown University, Providence, RI USA, 2John A. Paulson School of Engineering and Applied Sciences, Harvard University, Cambridge, MA USA

11.04 Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS Daniel S. Truesdell and Benton H. Calhoun; Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA

12:20PM LUNCH (ON OWN)

11.05 TCAD-Spice Co-Simulation of Ferroelectric Capacitor as an Electrically Trimmable On-Chip Capacitor in Analog Circuit K. Huynh1, A. C. Tenkeu1, K.P. Pun2 and H. Y. Wong1; 1Electrical Engineering, San JoseState University, San Jose, USA, 2Electrical Engineering, Chinese University of HongKong, Hong Kong, China

10.04 Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory Xiang Li1,2, Shy-Jay Lin3, Mahendra DC1, Yu-Ching Liao4, Chengyang Yao2, Azad Naeemi4, Wilman Tsai3, Shan X. Wang1,2; 1Materials Science and Engineering, Stanford University, Stanford, CA, USA, 2Electrical Engineering, Stanford University, Stanford, CA, USA, 3Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, 4Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

10.05 An Energy Efficient Computing-In-Memory Based on Try-Gate SONOS Flash Technology Koji Nii; Floadia Corporation (Invited Speaker)

Advance Program 12 2019 IEEE S3S Conference

3:30PM SESSION 13: FOCUS SESSION: FDSOI PLATFORMS AND PRODUCTS II

Technical Program

13.03 Advanced 22 nm FD-SOI Devices Integration Platform Cuiqin Xu; Shanghai Huali Integrated Circuit Corporation, Shanghai, China (Invited Speaker) Ming Tian, Cuiqin Xu, Haibo Lei; Technology Development DepartmentShanghai Huali Integrated Circuit Corporation Shanghai, China

13.01 The New Era of eMRAM-enabled Smart IoT Devices for the Connected World Phil Morris; ARM (Invited Speaker)

13.04 Adaptive Body-Biasing: A Breakthrough Path to Ultimate Power Savings Lionel Jure; Dolphin Design (Invited Speaker)

8:00PM COOK OUT

12.02 FDSOI Device Selection and Creation and What it Means for Your Next Design Jeff Cunningham; NXP (Invited Speaker)

12.03 22FDX® Embracing IoT, 5G, and Automotive Applications - A Perspective through Global Research Brian Chen; GlobalFoundries (Invited Speaker)

1:30PM SESSION 12: FOCUS SESSION: FDSOI PLATFORMS AND PRODUCTS I

12.01 Silicon-On-Thin-Buried-oxide for Energy Harvesting Applications Ken Imai; Renesas (Invited Speaker)

13.02 FDSOI: Unique Features, Accelerated Process Maturity, and Optimized Manufacturing for Focused Products Jay Guan; Samsung Semiconductor, San Jose, CA (Invited Speaker)

Advance Program 13 2019 IEEE S3S Conference

WEDNESDAY OCTOBER 16, 2019

7:00AM CONTINENTAL BREAKFAST

Technical Program

8:30AM SESSION 14: KEYNOTE SESSION: LOW-POWER CIRCUITS

14.02 Survival of the Fittest: Circuits and Architectures for Computation with Ultra- Wide Power-Performance Adaptation Beyond Voltage Scaling Massimo Alioto; National University of Singapore (Keynote Speaker)

14.03 Looking Back to Move Forward: How FDSOI Is Being Used to Improve Power Consumption of IOT Rob Cosaro; NXP Semiconductors, San Jose, CA (Keynote Speaker)

14.01 FD-SOI and The Exciting New Life of The Analog/RF Designers with Body Biasing Techniques Andreia Cathelin; STMicroelectronics (Keynote Speaker)

11:00AM SESSION 15: 3D TECHNOLOGY

15.01 Chip(let)s Ahoy! Subu Iyer; University of California, Los Angeles, CA (Invited Speaker)

15.02 High brightness and bonding yield of integrated Si-CMOS and GaN LED wafers Kwang Hong Lee1, Lin Zhang1, Li Zhang1, Yue Wang1, Kenneth Eng Kian Lee1, Soo Jin Chua2, Eugene A. Fitzgerald1, Chuan Seng Tan3; 1Low energy electronic systems Singapore-MIT Alliance for Research and Technology Singapore, 2Department of Electrical and Computer Engineering National University of Singapore, Singapore, 3School of electrical and electronic engineering Nanyang Technological University, Singapore

10:40AM BREAK

15.03 Heterogeneous Micro LED Displays Yield Statistics Khaled Ahmed; Intel Corporation, Santa Clara, United States

Advance Program 14 2019 IEEE S3S Conference

Technical Program

` SESSION 16: FDSOI CIRCUITS

15.05 Potential of a novel double-sided fully-depleted silicon-on-insulator CMOS architecture for the next-generation monolithic 3D CPUs and SOCs Amad Houssam Tarakji1 and Nirmal Chaudhary2; 1Device Organization Unit Solidi Technologies, Sacramento, CA, United States of America, 2Engineer consultant (private), Leesburg VA, United States of America

15.04 Microfluidic Cooling for 3D-IC with 3D Printing Package Jun-Han Han, Karina Torres-Castro, Robert E. West, Walter Varhue, Nathan Swami and Mircea Stan; Electrical and Computer Engineering Department University of Virginia Charlottesville, VA, USA

16.01 150-nW FD-SOI Intermittent Startup Circuit for Micropower Energy Harvesting Sensor Minoru Sudo1, Fumiyasu Utsunomiya1, Ami Tanaka2, and Takayuki Douseki2;1Ablic.Inc, Chiba, Japan, 2Ritsumeikan University, Shiga, Japan

16.02 A 0.75-V 58-MHz 340-W SOTB-65nm 32-point DCT Implementation Based on Fixed-rotation Adaptive CORDIC Ngoc-Tu Bui , Trong-Thuc Hoang, Akinori Yamamoto, Duc-Hung Le, and Cong- Kha Pham; University of Electro-Communications (UEC), Chofugaoka, Chofu-shi, Tokyo, Japan

16.03 Femtoampere sensitive current measurement ASIC in 22 nm technology Sarath Kundumattathil Mohanan1,2, Hamza Boukabache1, Daniel Perrin1, Ullrich Pfeiffer2; 1HSE-RP-IL CERN Geneva, Switzerland, 2IHCT University of Wuppertal Wuppertal,Germany

16.04 A 23 GHz VCO with 13% FTR in 22 nm FDSOI Piyush Kumar1 , Jidan AL-Eryani 1,3, David Borggreve2, Enno Böhme2, Pragoti Pran Bora2, Erkan Nevzat Isa2, Linus Maurer1 ; 1Universität der Bundeswehr, Department of Microelectronics and Circuit Design, Neubiberg, Germany, 2Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT, Munich, Germany 3Robert Bosch Gmbh,Reutilengen, Germany

16.05 An 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI Amir Shalom, Alexander Fish, and Adam Teman; Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel

Advance Program 15 2019 IEEE S3S Conference

Technical Program

SESSION 18: ADVANCED MATERIALS AND TRANSISTORS

1:30PM SESSION 17: TUNNEL FETS

17.03 Improved Electrical Characteristics of P-type Tunnel Field-Effect Transistor With Source-Pocket Junction Formed Using High-Angle Implantation Gaobo Xu, Huaxiang Yin, Qiuxia Xu, Guilong Tao, Guoliang Tian, Zhihao Li, Jinshun Bi, Jianhui Bu, Zhenhua Wu, Qingzhu Zhang, Yongliang Li, Jinbiao Liu, Junfeng Li, Huilong Zhu, Chao Zhao and Wenwu Wang; Keylaboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

17.02 New Pre-Requisites for Steep Sub-Threshold Tunnel Transistors Sri Krishna Vadlamani1, Sapan Agarwal2, Eli Yablonovitch1; 1Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA, 2Sandia National Laboratories, Albuquerque, USA

17.05 Impact of On-Current on the Static and Dynamic Performance of TFET InvertersAtieh Farokhnejad1, Fabian Horst1, Alexander Kloes1, Benjamin Iñíguez2 and François Lime2; 1NanoP, TH Mittelhessen University of Applied Sciences, Giessen, Germany, 2DEEEA, Universitat Rovira i Virgili, Tarragona, Spain

17.04 Two-stage Amplifier Design Based on Experimental Line-Tunnel FET Data Walter Gonçalez Filho1, Joao A. Martino1, Roberto Rangel1, Paula G. D. Agopian1,2, E. Simoen3, Rita Rooyackers4, Cor Claeys4,5, Nadine Collaert3; 1LSI/PSI/USP,University of Sao Paulo, Sao Paulo, Brazil, 2UNESP, Sao Paulo State University,Sao Joao da Boa Vista, Brazil, 3Imec, Leuven, Belgium, 4ClaRoo, Belgium, 5E.E. Dept,KU Leuven, Belgium

17.01 Group IV/oxide semiconductor bi-layer tunneling FETShinich Takagi; University of Tokyo (Invited Speaker)

18.01 Carrier Mobility Variation Induced by the Substrate Bias in Ω-gate SOI Nanowire MOSFETs F. E. Bergamaschi1, T. A. Ribeiro1, B. C. Paz2, M. de Souza1, S. Barraud2, M. Cassé2, M. Vinet2, O. Faynot2, M. A. Pavnello1; 1Electrical Engineering Department CentroUniversitário FEI São Bernardo do Campo, Brazil, 2Département des ComposantsSilicium SCME/LCTE CEA-Leti Minatec Grenoble, France

12:30PM LUNCH (ON OWN)

Advance Program 16 2019 IEEE S3S Conference

Technical Program

18.05 Potential Well Based FDSOI MOSFET: A Novel Planar Device for 10 nm Gate LengthShafi Qureshi and Shruti Mehrotra; Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur India

18.04 Quantitative Evaluation of Mobility Scattering Mechanisms in Ultra-Thin-Body Ge-OI pMOSFETs Sicong Yuan1, Walter Schwarzenbach2, Zhuo Chen1, Bich-Yen Nguyen2, and Rui Zhang1; 1College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China, 2Soitec, Parc Technologique des Fontaines Bernin, France

SESSION 19: ADVANCED DEVICES I

19.02 A Benchmark Study of Complementary-Field Effect Transistor (CFET) ProcessIntegration Options: Comparing Bulk vs. SOI vs. DSOI starting substrates

Benjamin Vincent1, J. Ervin2, J. Boemmels3, J. Ryckaert3; 1Coventor SARL Villebon- Sur-Yvette, France, 2Coventor Inc. Waltham, MA USA, 3imec, Leuven, Belgium

19.01 High Breakdown Voltage MESFETs Integrated with SOI CMOS TechnologiesTrevor Thornton; School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA (Invited Speaker)

18.03 Charge Trap Layer (CTL) SOI Substrates using Float Zone Wafers Achieving Low Substrate Losses Jeffrey Libbert1, Leif Jensen2, Theis Leth Sveigaard2, Mike Seacrist1, Carissma Hudson1, Shawn G. Thomas1; 1GlobalWafers, St. Peters, MO, USA, 2Topsil GlobalWafers, Frederikssund, Denmark

18.02 Si Layers Transfer On Sapphire or Silicon with High-k Stack of PEALD Dielectric Nanolayers

Vladimir Popov1, Valentin Antonov1, Alexey Leushin1, Ida Tyschenko2, Anton Gutakovskiy2, Andrey Miakonkich3 Konstantin Rudenko3; 1Laboratory of Silicon Material Science, Rzhanov Institute of Semiconductor Physics SB RAS, Novosibirsk, Russia, 2Laboratory of Nanodiagnostics and Nanolithography Rzhanov Institute of Semiconductor Physics SB RAS Novosibirsk, Russia, 3Laboratory of Microstructuring and Submicron Devices Valiev Institute of Physics and Technology RAS Moscow, Russia

19.03 Si/SiGe gate normal Tunneling FETs Qing-Tai Zhao; Research Center Juelich (Invited Speaker)

Advance Program 17 2019 IEEE S3S Conference

Technical Program

3:40PM SESSION 20: ADVANCE DEVICES II

20.05 Performance Enhancement of 4T-IFGC DRAM in 7nm NC-FinFET Technology Node Koshal Sharma, Amol D. Gaidhane, Ygesh Singh Chauhan; Department of Electrical Engineering Indian Institute of Technology Kanpur, Kanpur, India

20.04 Methodology for defining the characterization corners of foundation IPs and hard macros in an adaptive body-biased controlled area Mathieu Louvat1, Andrea Bonzo2, Anthony Mialon3, Philippe Flatresse1, Sebastien Genevey1, Lionel Jure1, Vincent Huard1; 1CTO Office, Dolphin Design, Meylan, France, 2SoC Integration, Dolphin Design, Meylan, France, 3Memory Design Team, Dolphin Design, Meylan, France

20.03 New Design Principles for Cold Electronics Erik P. DeBenedictis and Michael P. Frank; Center for Computing Research Sandia

National Laboratories Albuquerque, NM

AWARDS AND CLOSING REMARKS

20.01 Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI Wing-Tsi Wong, Kamlesh Singh, Jos Huisken, and Josė Pineda de Gyvez;Electronic Systems group, Eindhoven University of Technology, Eindhoven, The Netherlands

3:20PM BREAK

20.02 Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, Henk Corporaal, and Josė Pineda de Gyvez; Electronic Systems group, Eindhoven University of Technology, Eindhoven, The Netherlands

19.04 Statistical Characterization and Modelling of Gate-Induced Drain Leakage Variability in Advanced FDSOI DevicesT. A. Karatsori1, C. Cavalcante2, J. Lacord2, P. Batude2, C. Theodorou1, G. Ghibaudo1; 1IMEP-LAHC, Univ. Grenoble Alpes, Minatec, Grenoble, France, 2CEA-LETI, Univ. Grenoble Alpes, Minatec, Grenoble, France

Advance Program 18 2019 IEEE S3S Conference

FDSOI DESIGN SHORT COURSE THURSDAY FULL DAY COURSE

THE FDSOI DESIGN SHORT COURSE IS AVAILABLE FOR AN ADDITIONAL FEE AND INCLUDES A LIGHT BREAKFAST AND LUNCH. PRESENTATION MATERIALS WILL BE PROVIDED ON A USB DRIVE.

Education

This 2019 edition features a panel of world-renowned experts from the Semiconductor industry who will further explore the FDSOI Design new directions, cover a wide scope of topics ranging from technological standpoint or new targeted applications to low power design solutions and more specifically applied to FDSOI design.

The goal of this short course is also to encourage networking and trigger potential partnerships for future collaboration.

CONTINENTAL BREAKFAST

Short Course Opening and Welcome Philippe Flatresse, Business Development & Marketing Director, Dolphin Design

GLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIES

Embedded Flash Memory Technologies and Applications in Advanced Nodes Memories Koji Nii, Vice President, Global Marketing & Sales, Floadia Corporation

BREAK

Enabling the Adaptive Body Bias in Modern IoT ApplicationsVincent Huard, CTO, Dolphin Design

SoC Design Realization with Adaptive Body Bias Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics Didier Roland, Application Engineers Manager, Mentor Graphics

LUNCH

Analog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R&D

Low Power Solutions for SoC Architectures Antonio Pullini, Senior Hardware Designer, GreenWaves Technologies

BREAK

SOI to RF Sidina Wane, CEO, eV-technologies

WRAP UP

Advance Program 19 2019 IEEE S3S Conference

Education

RF DESIGN TUTORIALTUESDAY 1:20PM

THIS TUTORIAL IS INCLUDED IN THE CONFERENCE TECHNICAL PROGRAM REGISTRATION

RF-DTCO for mmWave Circuits Bertrand Parvais, imec, Belgium

Chip-Package-PCB-Antenna Co-Design for Smart 5G Solutions: Requirement for Unified Modeling and Instrumentation Platforms

Sidina Wane, EV-Technologies, France

Advance Program 20 2019 IEEE S3S Conference

Satellite Functions

SATELLITE FUNCTIONS

3DVLSI OPEN WORKSHOP Tuesday

CEA-Leti, IRT NanoElec and Qualcomm are pleased to invite you for a new 3DVLSI Open Workshop dedicated to high density 3D-IC and CoolCubeTM (Monolithic/Sequential 3D) technologies.

The workshop is held Tuesday, Octover 15 at the same location as the IEEE S3S Conference.

The 3DVLSI project’s goals include building a complete ecosystem that takes the technology from design to fabrication. A first 3DVLSI open Workshop was organized back in 2014. Since then, the workshop has offered presentations from Applied Materials, ARM, Atrenta, Cadence, CEA-Leti, Georgia Tech, Globalfoundries, HPE, Intel, Mentor Graphics, Monolithic3D, Qualcomm, Stanford University, TSMC and many more.

Registration is free and available to S3S attendees.

However, since seating is limited, registration is by invitation only. If interested, please send an email to severine.cheramy@cea.fr.

Advance Program 21 2019 IEEE S3S Conference

Additional Agenda Items

Our conference would not be complete without our cookout. Combining great food and pleasant company is all part of what makes our conference so special. The cookout is another great way to network and meet your fellow attendees. Relax and enjoy yourself.

This year we will have for our member’s convenience a hospitality suite located in the hotel. This will be a location that everyone will have access to during conference hours. Think of it as a place where you can get away from conference proper. Sit down in comfortable surroundings and enjoy a conversation with colleagues. Have a light refreshment and just get away from things for a few minutes.

Remember to start your day right!

One of the perks of the Technical or Combined Membership is a light breakfast daily (Monday thru Wednesday). Don’t worry, our breakfast also includes coffee for those who need more that a bite of food to get them started.

OTHER FUNCTIONS

COOKOUT Tuesday 8:00PM

HOSPITALITY SUITE Monday thru Wednesday 10:00AM to 6:00PM

BREAKFAST Monday thru Wednesday 7:00AM to 8:00AM

RUMP SESSION Monday 8:00PM

Join us as a panel of experts discusses this years topic: AI at the Edge: Driving the Next Wave of Semiconductor Growth or Yet Another Hype

Advance Program 22 2019 IEEE S3S Conference

Conference Hotel

DOUBLETREE BY HILTON SAN JOSE

2050 Gateway Place, San Jose, CA 95110 +1 408 453-4000

Just minutes from San Jose International Airport, our hotel offers free Wi-Fi in the sleeping rooms. A complimentary 24-hour airport shuttle service is available for your convenience to SJC running every 20 minutes.

Looking for a bite to eat? The DoubleTree San Jose offers a variety of dining experiences.

Spencer’s features exquisite steaks & chops, an extensive wine list and decadent desserts. The Sushi Bar and 2050 Lobby Lounge & Bar, overlooking our sparkling pool, serves libations to what your appetite desires before or after dinner.

Hotel Rates

The DoubleTree by Hilton San Jose is pleased to offer a special discounted rate of $229.00 (plus 14.4% occupancy tax and a $1.25 per night HBIDF) single/double occupancy for conference attendees.

The rate will be good from Saturday, 12 October 2019 thru Friday, 18 October 2019. A major credit card or deposit will be needed when you make a reservation to guarantee your room.

All hotel reservations must be made by 5:00pm PDT, 2 October 2019. After October 2nd, you will need to contact the hotel directly as reservations will only be accepted if space is available.

We highly recommend you make your reservations early as we are limited on rooms this year due to other conferences in the area.

Student Rate Rooms We have a few rooms available for students at a discounted rate. First priority will go to those students who are presenting papers. Please contact manager@S3Sconference.org for assistance.

Make a Reservation Use the following link to reserve your room today!

RESERVE YOUR ROOM NOW

Visit our website for additional hotel information

Advance Program 23 2019 IEEE S3S Conference

Travel Information

AIRPORT

SHUTTLE SERVICE

LOCAL TRANSPORTATION

RENTAL CARS

PARKING AT THE DOUBLETREE

INTERNATIONAL TRAVELERS

The nearest international airport is San Jose International Airport (SJC). This is the smaller of the two international airports that service San Jose, but is the most convenient to our conference hotel.

San Francisco International Airport (SFO), located 30 miles away, offers more travel options as it is the larger airport.

The DoubleTree by Hilton San Jose offers a free 24-hour shuttle to and from San Jose International Airport only. The shuttles run every 20 minutes.

At the San Jose Airport, the hotel courtesy shuttles pickup passengers from the Offsite Courtesy Shuttle Stop conveniently located at the Terminal A Ground Transportation Center, stop #8 or at Terminal B at the Ground Transportation Center, stop #10 directly across the street from Baggage Claim.

If you are traveling in from San Francisco International Airport (SFO), we sug-gest you use Super Shuttle or comparable door to door shuttle service.

The VTA light rail system is a great way to get around San Jose. The closest station is a mere 5 minute walk away from the DoubleTree San Jose.

Both the San Jose International airport and San Francisco Airport offer repre-sentation from all the major car rental companies.

For a complete listing and contact information please see SJC Car Rentals for San Jose International .

For a listing of car rental options from San Francisco Airport, see SFO Car Rentals.

The DoubleTree San Jose self-parking is available at our group rate of $24.00 per day.

Please note: those that travel in will be charged a full day rate for each entrance. Members staying at the hotel will receive in and out privileges.

For information on traveling to the United States. Please visit the U.S. Department of States website for the most current information.

If you find you are in need of a Visa, contact manager@s3sconference.org for information on obtaining a letter for your embassy.

Advance Program 24 2019 IEEE S3S Conference

Conference Registration

ON-SITE 2019 CONFERENCE REGISTRATION SCHEDULE

CREDIT CARD PAYMENTS

CHECK PAYMENTS

WIRE TRANSFER PAYMENTS

CANCELLATIONS

To pay by credit card please use our ONLINE registration form.

We accept Visa, Master-Card and American Express. You will need to have the card with you when registering as you need to provide the security code when you enter your card information.

The 3-digit security code for Visa and MasterCard is located on the back of the card. The 4 digit code for American Express is located on the front of the card.

While payment may be made via bank transfer (by wiring funds), it is discour-aged and there is an additional $25 fee per transfer to cover handling costs. If a bank transfer is necessary, please contact the conference manager at manager@s3sconference.org for further instructions and the appropriate ac-count numbers.

Cancellation requests must be made in writing to the conference manager.Refund requests received by October 1, 2019 will receive a refund of registration fees less a $50 processing fee.

All refunds will be processed after the conference.

Sunday, October 13

Monday, October 14

Tuesday, October 15

Wednesday, October 16

Thursday, October 17

6:00PM to 8:00PM

7:00AM to 5:00PM

7:00AM to 5:00PM

7:00AM to 12:00PM

7:00PM to 12:00PM

Complete the registration form and mail it with your check to:IEEE S3S Conference, 6930 De Celis Place, #36, Van Nuys, CA 91406Please make the check payable to 2016 IEEE S3S Conference.

All checks must be drawn on a US bank and in US funds only.

Registration forms received without payment will not be honored.

If you have any questions please do not hesitate to contact the conference manager at manager@s3sconference.org or call (818) 795-3768

Advance Program 25 2019 IEEE S3S Conference

REGISTRATION SOI-3DI-Subthreshold Microelectronics Technology

Unified ConferenceOctober 14-17, 2019 • DoubleTree by Hilton San Jose • San Jose CA

Complete and print this page for mail or email

NAME TO APPEAR ON BADGE

*LAST NAME, FIRST NAME, MIDDLE INITIAL

*COMPANY, AGENCY OR ACADEMIC INSTITUTION

STUDENT REGISTRATION: Please give institution and graduation year

*PREFERRED MAILING ADDRESS *MAIL STOP

*CITY / STATE / ZIP / COUNTRY

*TELEPHONE NUMBER

*EMAIL ADDRESS

IEEE MEMBER NUMBER

Do you have any special needs or dietary restrictions? If YES - Please let us know so we can attempt to accommodate your needs:

*As you want it to appear on the Conference List of Attendees

Make check payable to “2019 IEEE S3S Conference” and mail along with this completed form to:

2019 IEEE S3S CONFERENCE 6930 De Celis Place #36, Van Nuys, CA 91406

• Registrations received without paymentwill not be accepted

• Credit cards accepted via online registration only

• Wire Transfers must be approved in advance andare subject to a $25 fee.

• No telephone registrations will be available

IEEE MemberNon MemberStudent IEEE MemberStudent Non Member

$900$1125$425$545

$975$1225$500$620

by Oct 2nd After Oct 2nd

IEEE MemberNon MemberStudent IEEE MemberStudent Non Member

$600$750$300$400

$650$800$380$450

Short Course Only (Thursday)IEEE MemberNon MemberStudent IEEE MemberStudent Non Member

$400$450$125$175

$450$500$150$200

Tutorial Only (Tuesday)IEEE MemberNon MemberStudent IEEE MemberStudent Non Member

$75$100$50$75

$75$100$50$75

Total Registration Fees

We welcome guests at our cookout. The cookout is included with the purchase of the Technical Program, so you do not need to purchase again. Below is for any guests you would wish to bring with you.

Tuesday Guest Cookout @ $80 ea. =

TOTAL ENCLOSED

Combined Conference and Short Course (Monday thru Thurs)

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REGISTRATION FEESAdvance registration fees apply to completed forms and payment received by September 20, 2019

Technical Program Only (Monday thru Wednesday)

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2019 Committee

Short Course Chair Philippe Flatresse

Dolphin Design philippe.flatresse@dolphin.fr

Multimedia Chair Yuh-Yue Chen

RichWave Technology Corp.yychen@richwave.com.tw

Rump Session Chair Jon Cheek

SOI Industry Consortium

Poster Session Chair Michelly De Souza

Centro Universitario da FEImichelly@fei.edu.br

Tutorial Coordinator Mostafa Emam

Incizemostafa.emam@incize.com

Digital Commuinications Chair

Joao Antonio MartinoUniversity of Sao paulo

martino@lsi.usp.br

General Chair Mostafa Emam

Incizemostafa.emam@incize.com

SOI Chair Shawn Thomas

GlobalWaferssthomas@gw-semi.com

Publicity Chair - Asia Nobuyuki Sugii

Hitachin-sugii@ieee.org

Technical Chair Bich-Yen Nguyen

SOITECbich-yen.nguyen@soitec.com

3D Technology Chair Paul Franzon

North Carolina State UniversityPaulf@ncsu.edu

Publicity Chair - EuropeNadine Collaert

imecNadine.Collaert@imec.be

Treasurer Bruce Doris

IBMbdoris@us.ibm.com

Low-Voltage Devices Chair Nu Xu

Samsung

Secretary Ali Khakifirooz

Intelali.khakifirooz@intel.com

Sponsorship ChairJean-Eric Michallet

CEA-LETIjean-eric.michallet@cea.fr

Low Power Circuits ChairPhilippe Flatresse

Dolphin Design philippe.flatresse@dolphin.fr

2019 Committee

Shawn ThomasGlobalWafers

thomas@gw-semi.com

Siva AdusumilliGlobalFoundries

Mike AllesVanderbilt University

Fred AllibertSoitec

Gary BronnerRambus

Yuh-Yue ChenRichWave Technology Corp

Kangguo ChengIBM

Bruce DorisIBM

Alain DuvalletpSemi

Olivier FaynotCEA-Leti

Samuel FungTSMC

Pascale GoukerMIT Lincoln Laboratory

Mark HallNXP

Michel HaondSTMicroelectronics

Toshiro HiramotoUniversity of Tokyo

Keiji IkedaToshiba

Joao Antonio MartinoUniversity São Paulo

Meishoku MasaharaNational Institute of AIST

Bich-yen NguyenSoitec

Yasuhisa OmuraKansai University

Mario PelellaOn Semiconductory

Jamie SchaeferGlobalFoundries

Nobuyuki SugiiHitachi

Yoshiki YamamotoRenasas

Yi ZhaoZhejiang University

Huilong ZhuInstitute of Microelectronics

EXECUTIVE COMMITTEE

SENIOR COMMITTEE

SOI TECHNOLOGY COMMITTEE

Advance Program 27 2019 IEEE S3S Conference

Paul FranzonNorth Carolina State University

Paulf@ncsu.edu

Eric Beyneimec

Andy CarterTeledyne

Yang DuVanguard International

Semiconductor

Mukta FarooqIBM

Eugene FitzgeraldMIT

Jin-Woo HanNASA

Subu IyerUCLA

Amandine JouveCEA-Leti

Sung-Kyu Lim Georgia Institute of Technology

Tsu-Jae King LiuUniversity of California Berkeley

Zvi Or-BachMonolithIC 3D

Robert PattinHanced Semiconductors

Arifur RahmanIntel

Chuan Seng TanNanyang Technological

University

Thomas UhrmannEVG

Maud VinetCEA-Leti

S.J. Ben YooUniversity of California, Davis

Philip WongStanford University

3D TECHNOLOGY COMMITTEE

Nuo XuSamsung

Lew CohnNRO

Michelly de SouzaCentro Universitário FEI

Michael FritzePotomac Institute

Ru HuangPeking University

Louis HutinCEA-Leti

Ali KhakifroozIntel

Jong-Ho LeeSeoul National University

Farnaz NirouiMIT

Dan RadackInstitute for Defense Analyses

Alan SeabaughUniversity of Notre Dame

Changhwan ShinUniversity of Seoul

Steven VitaleMIT Lincoln Laboratory

Jing WanFudan University

Lan WeiUniversity off Waterloo

Eli Yablonovitch University of California, Berkeley

Jeng-Bang (Tony) YauIBM

David ZubiaiUniveristy of Texas, El Paso

LOW-VOLTAGE DEVICES COMMITTEE

Philippe FlatresseDolphin Design

philippe.flatresse@dolphin.fr

Khaled Ahmed Intel

Bevan BaasUniversity of California, Davis

Imran BashirCypress Semiconductors

Edith BeigneFacebook

David BolUniversité Catholique

de Louvain

Jeff CunninghamNXP

Patrick DrennanQualcomm

Stéphane EmeryCSEM

Alex FishBar-Ilan University

Sumeet GuptaPurdue University

Vincent HuardDolphin Design

Lauri KoskinenUniversity of Turku

Davide RossiUniversity di Bologna

Mingoo SeokColumbia University

Makoto TakamiyaUniversity of Tokyo

LOW-POWER CIRCUITS COMMITTEE

2019 Committee

Advance Program 28 2019 IEEE S3S Conference