22ldpc decoding v2

7/28/2019 22ldpc Decoding v2

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Error Correction and LDPC decoding

1


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Error Correction in Communication Systems

2

Error: Given the original frame k and the

received frame k, how many corresponding bitsdiffer?

Hamming distance (Hamming, 1950).

Example:

Transmitted frame: 1110011

Received frame: 1011001

Number of errors:

noise

TransmitterBinary

informationCorrectedinformationframe

Corruptedframe

channel Receiver

3


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3

Error Detection and Correction

Add extra information to the original data being

transmitted. Frame = k data bits + m bits for error control: n = k + m.

Error detection: enough info to detect error.

Need retransmissions. Error correction: enough info to detect and

correct error.

Forward error correction (FEC).


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Encoder(Adding

Redundancy)

ChannelDecoder

(Error Detection

and Correction

Noise

Binary

information

Corrected

information

Encoded

information

Corruptedinformation

with noise

Reed Solomon

codes

Hammingcodes

LDPC

Introduced

Convolutional

codes

BCH codes

Renewed interest

in LDPC

Turbocodes

19701960 1990 20001980

Practicalimplementation

of codes LDPC beats

Turbo and

convolutional

codes


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Modulation

The information format is changed *******

Binary Phase Shift-Keying (BPSK) Modulation

1-2X

5

signal power is two times noise power


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Key terms

Encoder : adds redundant bits to the sender's bit stream to

create a codeword. Decoder: uses the redundant bits to detect and/or correct as

many bit errors as the particular error-control code will allow.

Communication Channel: the part of the communication

system that introduces errors. Ex: radio, twisted wire pair, coaxial cable, fiber optic cable, magnetic

tape, optical discs, or any other noisy medium

Additive white Gaussian noise (AWGN)

Larger noise makes the

distribution wider

6


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Important metrics

Bit error rate (BER): The probability of bit error.

We want to keep this number small

Ex: BER=10-4 means if we have transmitted10,000 bits, there is 1 bit

error.

BER is a useful indicator of system performance independent of error

channel

BER=Number of error bits/ total number of transmitted bits Signal to noise ratio (SNR): quantifies how much a signal has

been corrupted by noise.

defined as the ratio of signal power to the noise power corrupting the

signal. A ratio higher than 1:1 indicates more signal than noise

often expressed using the logarithmic decibel scale:

Important number: 3dB means7 signal power is two times noise power


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Goal: Attain lower BER at smaller SNR

Error correction is a key componentin communication and storageapplications.

Coding example: Convolutional,Turbo, and Reed-Solomon codes

What can 3 dB of coding gain buy?

A satellite can send data with half the

required transmit power A cellphone can operate reliably with

half the required receive power Signal to Noise Ratio (dB)

Figure courtesy of B. Nikolic, 2003(modified)

B

it

ErrorProbability

100

10-1

10-2

10-3

10-4

0 1 2 3 4 5 6 7 8

3 dBConvolutional

code

Uncoded system

noise

8

Information

k-bit

channel

Codeword

n-bitReceivedword

n-bitDecoder

(check parity,detect error)

Encoder

(add parity)

Corrected

Information

k-bit


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LDPC Codes and Their Applications

Low Density Parity Check (LDPC) codes have superior

error performance 4 dB coding gain over convolutional codes

Standards and applications

10 Gigabit Ethernet (10GBASE-T) Digital Video Broadcasting

(DVB-S2, DVB-T2, DVB-C2)

Next-Gen Wired Home

Networking (G.hn)

WiMAX (802.16e) WiFi (802.11n)

Hard disks

Deep-space satellite missions

Signal to Noise Ratio (dB)

B

it

ErrorProbability

100

10-1

10-2

10-3

10-4

0 1 2 3 4 5 6 7 8

4 dBConv. code

Uncoded

Figure courtesy of B. Nikolic, 2003(modified)9


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Future Wireless Devices Requirements

Increased throughput 1Gbps for next generation of WiMAX

(802.16m) and LTE (Advanced LTE) 2.2 Gbps WirelessHD UWB [Ref]

Power budget likely Current smart phones require 100 GOPS

within 1 Watt [Ref]

Required reconfigurability fordifferent environments A rate-compatible LDPC code is proposed

for 802.16m [Ref]

Required reconfigurability for

different communication standards Ex: LTE/WiMax dual-mode cellphones

require Turbo codes (used in LTE) andLDPC codes (used in WiMAX)

Requires hardware sharing for silicon areasaving


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Future Digital TV Broadcasting Requirements

High definition television for

stationery and mobile users DTMB/DMB-TH (terrestrial/mobile),ABS-S (satellite), CMMB(multimedia/mobile)

Current Digital TV (DTV)standards are not well-suited formobile devices Require more sophisticated signal

processing and correction algorithms

Require Low power

Require Low error floor

Remove multi-level coding

Recently proposed ABS-S

LDPC codes (15,360-bitcode length, 11 code rates)achieves FER < 10-7without concatenation [Ref]


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Future Storage Devices Requirements

Ultra high-density storage

2 Terabit per square inch [ref] Worsening InterSymbol Interference (ISI) [ref]

High throughput Larger than 5 Gbps [ref]

Low error floor Lower than 10-15 [ref]

Remove multi-level coding

Next generation of Hitachi IDRC read-channel technology [9]


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Encoding Picture Example

H.ViT=0

1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1

0 1 0 0 1 0 0 0 1 0 1 1

0 1 1 0 0 1 0 0 0 1 1 00 1 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0

...

V=

1 0 0 0 0 0 0 0 0 0 . . .1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 0 0 . . .1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 0 . . .0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0

0 0 0 1 0 0 0 0 0 0 . . .0 0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1

...

H=

Parity Image

V=

Binary multiplication called syndrome check


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Decoding Picture Example

2 0 4 0 6 0 8 0 1 0 0 1 20 1 4 0 1 60 1 8 0 2 00

50

100

150

200

250

2 0 4 0 6 0 8 0 1 0 0 1 20 1 40 1 6 0 1 80 2 00

50

100

150

200

250

50 100 150 200

50

100

150

200

250

2 0 4 0 6 0 8 0 1 0 0 1 20 1 4 0 1 60 1 8 0 2 00

50

100

150

200

250

Iterative message passing decoding

Receivernoise

Iteration 1

Transmitter

Iteration 5 Iteration 15 Iteration 16

channel

Ethernet cable,

Wireless,

or Hard disk


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LDPC CodesParity Check Matrix

Defined by a large binary matrix, called aparity check matrixorHmatrix

Each row is defined by a parity equation

The number of columns is the code length

Example: 6x 12 Hmatrix for a12-bit LDPC code

No. of columns=12 (i.e. Receivedword (V) = 12 bit)

No. of rows= 6

No. of ones per row=3 (row weight) No. of ones per col= 2 (column weight)

15

100001010

010100001

001001100

001100010

100010001

10010100

H =

C1

V3 V4 V8V1 V2 V5 V6 V7 V9

C2

C3

C4

C5

C6

001

010010

100

001

100

V11V10 V12

0


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LDPC CodesTanner Graph

Interconnect representation ofHmatrix

Two sets of nodes: Check nodes and Variable nodes

Each row of the matrix is represented by a Check node

Each column of matrix is represented by a Variable node

A message passing method is used between nodes to correct errors

(1) Initialization with Receivedword

(2) Messages passing until correct

Example:V3 to C1, V5 to C1,

V8to C1, V10to C1

C2to V1, C5 to V1

16

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Variable nodes

Receivedwordfrom channel

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Variable nodes

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Variable nodes

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0


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Transmission scenario

17


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Message Passing: Variable node processing

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

is the original received information from the channel18

:message from check tovariable node

:message from variableto check node

jij

hj

j

ij

Z '1,' '

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

ijjij Z


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Message Passing: Check node processing(MinSum)

Sfactorsign ijjjhjjjhj

ijMSij

ijij

'

',1,'',1,'

' min''

19

Sign Magnitude

After check nodeprocessing, the next

iteration starts with

another variable

node processing

(begins a new

iteration)

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V6 V7 V8 V9 V10 V11 V12V6

Check nodes

Variable nodes

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0


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Code Estimation

Based on your modulation

scheme (here BPSK)

estimate the transmitted

bits

20

^V^V

Z


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Syndrome Check

Compute syndrome

Ex:

21

H.ViT=0 (Binary multiplication)

If syndrome =0, terminate

decoding

Else, continue another iteration

^


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Example

Encoded information V= [1 0 1 0 1 0 1 0 1 1 1 1]

22

BPSK modulated= [-1 1 -1 1 -1 1 -1 1 -1 -1 -1 -1]

(Received data from channel)=

[ -9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8]

Estimated code=

V= 1 0 1 0 1 0 0 0 1 1 1 1^

Information

k-bit

channel

Codeword (V)

n-bitReceivedword()

n-bitDecoder

(iterativeMinSum)

Encoder

Corrected

Information

n-bitBPSK

modulation

E V i bl d i (it ti 1)


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Ex: Variable node processing (iteration 1)

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

23

0

-9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8

12

15

0

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

1Z

=

E Ch k d i


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Ex: Check node processing (Iteration 1)

24

100001010

010100001

001010100001100010

100010001

10001100

H

001

010

010100

001

100

0

1)1)(1)(1()(

}5.2,6.1,6.3{||

13

13

Sign

Min

=-9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8

)(

||

14

14

Sign

)(

||

18

18

Sign

)(

||

110

110

Sign

1Sfactor Here assume

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V6 V7 V8 V9 V10 V11 V12V6

E C d E ti ti (It ti 1)


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Ex: Code Estimation (Iteration 1)

25

^V

^V

Z

= 1 0 1 0 1 0 0 0 1 1 1 1

Z==

[ -9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8]

^V

E S d Ch k (it ti 1)


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Ex: Syndrome Check (iteration 1)

Compute syndrome

H.ViT=0 (Binary multiplication)^

26

100001010010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001100

0

i

i

hhj

ji

SyndromeSyndromSum

vXORSyndrome

ijij 0|

)(

Sumsyndrome=2 Not ZERO => Error, continue decoding

1

0

1

0

1

0

0

0

1

1

1

1

x

0

0

1

1

10

0

S d it ti


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Second iteration

In variable node processing, compute , and Z based on the algorithm

27

Z= [-12.1 7.1 -4.5 7.7 -7.2 4.4 -4.2 7.2 -10.0 -7.7 -8.9 -8.1]

[ 1 0 1 0 1 0 1 0 1 1 1 1 ]^V=

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

-1.4 -1.6

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

=-9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8=

E S d Ch k (it ti 2)


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Ex: Syndrome Check (iteration 2)

Compute syndrome

H.ViT=0 (Binary multiplication)^

28

100001010010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001100

0

i

i

hhj

ji

SyndromeSyndromSum

vXORSyndrome

ijij 0|

)(

Sumsyndrome= ZERO => corrected code Terminate Decoding

1

0

1

0

1

0

1

0

1

1

1

1

x

0

0

0

0

00

0


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Full Parallel LDPC Decoder Examples


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Full-Parallel LDPC Decoder Examples

For all data in the plot:

Same automatic place & route flow is used

CPU: Quad Core, Intel Xeon 3.0GHz

Ex 1: 1024-bit decoder, [JSSC2002]

52.5 mm2, 50% logic utilization, 160 nm CMOS

Ex 2: 2048 bit decoder, [ISCAS 2009]

18.2 mm2, 25% logic utilization, 30 MHz,

65 nm CMOS

CPU time for place & route>10 days

105

106

107

0

100

200

300

Number of wire connections

CPU

time(hours)

512 Chk &1024 Var

Proc.

384 Chk

& 2048

Var Proc.

Serial Decoder Example


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Serial Decoder Example

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Variable nodes

Mem

Row Col

Mem

Row Col

Mem

Row Col

(2)compute V1

and storeV2 V3

V4 V5 V6

V7 V8 V9

V10 V11 V12

(1)initialize memory(clear contents)

(3)nowcompute C1

and storeC2 C3

C4 C5 C6

Decoding Architectures


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Decoding Architectures

Partial parallel decoders

Multiple processing unitsand shared memories

Throughput: 100 Mbps-Gbps

Requires Large memory

(depending on the size) Requires Efficient Control and

schedulingVar Var Var Var

Mem Mem Mem Mem

Mem Mem Mem Mem

Mem Mem Mem Mem

Chk

Chk

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

Reported LDPC Decoder ASICs


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Reported LDPC Decoder ASICs

2000 2002 2004 2006 2008 201010

1

102

103

104

105

Year

Throughput(Mbps)

Partial-parallel Decoder

Full-parallel Decoder

10GBASE-T

802.16e

DVB-S2

802.11n

802.11a/g

Throughput Across Fabrication Technologies


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Throughput Across Fabrication Technologies

Existing ASIC implementations without early termination

Full-parallel decoders have the highest throughput

659013016018010

1

10

2

103

104

CMOS Technology (nm)

Throughput(Mbp

s)



Energy per Decoded Bit in Different Technologies


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Energy per Decoded Bit in Different Technologies

Existing ASIC implementations without early termination

Full-parallel decoders have the lowest energy dissipation

659013016018010

-1

10

0

101

102


Ene

rgyperbit(nJ/bit)



Circuit Area in Different Technologies


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Circuit Area in Different Technologies

Full-parallel decoders have the largest area due to the high

routing congestion and low logic utilization

659013016018010

0

101

102

103


Area

ofDecoderChip

(mm

2)



Key optimization factors


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Key optimization factors

Architectural optimization

Parallelism

Memory

Data path wordwidth (fixedpoint format)

37

Check

Node + + +_ i

i

ii=1

+

Variable Node

clk

Wc

ii=1

Wc

1...Wc



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38

BER performance versus quantization format


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BER performance versus quantization format

39 SNR(dB)

Check Node Processor


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41

Variable Node Processor


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Variable Node Processor

Based on the variable

update equation The same as the

original MinSum and

SPA algorithms

Variable node

hardware complexity

is mainly reduced via

wordwidth reduction

jijhj

ij

ij

'

1,' '

+

+

+3

i

i + jSMto 2's

2's to

SM

2's to

SMwc

SM

to 2's

j=1:wc

1

1

wc

+

+

++

+

+

-

- SAT

SAT

8

6

5

8

7

7

7

seven 5-bit

inputs

Partial parallel decoder example


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Partial parallel decoder example

43

802 11ad LDPC code


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802.11ad LDPC code

22ldpc decoding v2

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