2/3-port ethercat® slave controller with integrated ... · pd 50 µa (typical) internal pull-down....

LAN9252

2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

Highlights• 2/3-port EtherCAT slave controller with 3 Fieldbus

Memory Management Units (FMMUs) and 4 SyncManagers

• Interfaces to most 8/16-bit embedded controllers and 32-bit embedded controllers with an 8/16-bit bus

• Integrated Ethernet PHYs with HP Auto-MDIX• Wake on LAN (WoL) support• Low power mode allows systems to enter sleep

mode until addressed by the Master• Cable diagnostic support• 1.8V to 3.3V variable voltage I/O• Integrated 1.2V regulator for single 3.3V operation• Low pin count and small body size package

Target Applications• Motor Motion Control• Process/Factory Automation• Communication Modules, Interface Cards• Sensors• Hydraulic & Pneumatic Valve Systems• Operator Interfaces

Key Benefits• Integrated high-performance 100Mbps Ethernet

transceivers- Compliant with IEEE 802.3/802.3u (Fast Ethernet)- 100BASE-FX support via external fiber transceiver- Loop-back modes- Automatic polarity detection and correction- HP Auto-MDIX

• EtherCAT slave controller- Supports 3 FMMUs- Supports 4 SyncManagers- Distributed clock support allows synchronization with

other EtherCAT devices- 4K bytes of DPRAM

• 8/16-Bit Host Bus Interface- Indexed register or multiplexed bus- Allows local host to enter sleep mode until addressed by

EtherCAT Master- SPI / Quad SPI support

• Digital I/O Mode for optimized system cost• 3rd port for flexible network configurations• Comprehensive power management features

- 3 power-down levels- Wake on link status change (energy detect)- Magic packet wakeup, Wake on LAN (WoL), wake on

broadcast, wake on perfect DA- Wakeup indicator event signal

• Power and I/O- Integrated power-on reset circuit- Latch-up performance exceeds 150mA

per EIA/JESD78, Class II- JEDEC Class 3A ESD performance- Single 3.3V power supply

(integrated 1.2V regulator)• Additional Features

- Multifunction GPIOs- Ability to use low cost 25MHz crystal for reduced BOM

• Packaging- Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP-

EP• Available in commercial, industrial, and extended

industrial* temp. ranges*Extended temp. (105ºC) is supported only in the 64-QFN with anexternal voltage regulator (internal regulator must be disabled) and2.5V (typ) Ethernet magnetics.

2015 Microchip Technology Inc. DS00001909A-page 1

LAN9252

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DS00001909A-page 2 2015 Microchip Technology Inc.

mailto:[email protected]://www.microchip.comhttp://www.microchip.com


LAN92521.0 Preface ............................................................................................................................................................................................ 42.0 General Description ........................................................................................................................................................................ 83.0 Pin Descriptions and Configuration ............................................................................................................................................... 114.0 Power Connections ....................................................................................................................................................................... 295.0 Register Map ................................................................................................................................................................................. 326.0 Clocks, Resets, and Power Management ..................................................................................................................................... 377.0 Configuration Straps ..................................................................................................................................................................... 518.0 System Interrupts .......................................................................................................................................................................... 539.0 Host Bus Interface ........................................................................................................................................................................ 6210.0 SPI/SQI Slave ........................................................................................................................................................................... 10211.0 Ethernet PHYs .......................................................................................................................................................................... 12012.0 EtherCAT .................................................................................................................................................................................. 19613.0 EEPROM Interface ................................................................................................................................................................... 29514.0 Chip Mode Configuration .......................................................................................................................................................... 29615.0 General Purpose Timer & Free-Running Clock ........................................................................................................................ 29716.0 Miscellaneous ........................................................................................................................................................................... 30117.0 JTAG ......................................................................................................................................................................................... 30518.0 Operational Characteristics ....................................................................................................................................................... 30719.0 Package Outlines ...................................................................................................................................................................... 32220.0 Revision History ........................................................................................................................................................................ 325

LAN9252

1.0 PREFACE

1.1 General Terms

TABLE 1-1: GENERAL TERMSTerm Description

10BASE-T 10 Mbps Ethernet, IEEE 802.3 compliant100BASE-TX 100 Mbps Fast Ethernet, IEEE802.3u compliantADC Analog-to-Digital ConverterALR Address Logic ResolutionAN Auto-NegotiationBLW Baseline WanderBM Buffer Manager - Part of the switch fabricBPDU Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol informa-

tionByte 8 bitsCSMA/CD Carrier Sense Multiple Access/Collision DetectCSR Control and Status RegistersCTR CounterDA Destination AddressDWORD 32 bitsEPC EEPROM ControllerFCS Frame Check Sequence - The extra checksum characters added to the end of an

Ethernet frame, used for error detection and correction.FIFO First In First Out bufferFSM Finite State MachineGPIO General Purpose I/OHost External system (Includes processor, application software, etc.)IGMP Internet Group Management ProtocolInbound Refers to data input to the device from the hostLevel-Triggered Sticky Bit This type of status bit is set whenever the condition that it represents is asserted. The

bit remains set until the condition is no longer true and the status bit is cleared by writ-ing a zero.

lsb Least Significant BitLSB Least Significant ByteLVDS Low Voltage Differential SignalingMDI Medium Dependent InterfaceMDIX Media Independent Interface with CrossoverMII Media Independent InterfaceMIIM Media Independent Interface ManagementMIL MAC Interface LayerMLD Multicast Listening DiscoveryMLT-3 Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a

change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”.

msb Most Significant BitMSB Most Significant Byte


LAN9252

NRZI Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and leaves the signal unchanged for a “0”

N/A Not ApplicableNC No ConnectOUI Organizationally Unique IdentifierOutbound Refers to data output from the device to the hostPISO Parallel In Serial OutPLL Phase Locked LoopPTP Precision Time ProtocolRESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must

always be zero for write operations. Unless otherwise noted, values are not guaran-teed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses.

RTC Real-Time ClockSA Source AddressSFD Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an

Ethernet frame.SIPO Serial In Parallel OutSMI Serial Management InterfaceSQE Signal Quality Error (also known as “heartbeat”)SSD Start of Stream DelimiterUDP User Datagram Protocol - A connectionless protocol run on top of IP networksUUID Universally Unique IDentifierWORD 16 bits

TABLE 1-1: GENERAL TERMS (CONTINUED)Term Description


LAN9252

1.2 Buffer Types

TABLE 1-2: BUFFER TYPES

Buffer Type Description

IS Schmitt-triggered input

VIS Variable voltage Schmitt-triggered input

VO8 Variable voltage output with 8 mA sink and 8 mA source

VOD8 Variable voltage open-drain output with 8 mA sink


VOD12 Variable voltage open-drain output with 12 mA sink

VOS12 Variable voltage open-source output with 12 mA source


PU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled.Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added.

PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled.Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added.

AI Analog input

AIO Analog bidirectional

ICLK Crystal oscillator input pin

OCLK Crystal oscillator output pin

ILVPECL Low voltage PECL input pin

OLVPECL Low voltage PECL output pin

P Power pin


LAN9252

1.3 Register Nomenclature

TABLE 1-3: REGISTER NOMENCLATURERegister Bit Type Notation Register Bit Description

R Read: A register or bit with this attribute can be read.W Read: A register or bit with this attribute can be written.

RO Read only: Read only. Writes have no effect.WO Write only: If a register or bit is write-only, reads will return unspecified data.WC Write One to Clear: Writing a one clears the value. Writing a zero has no effect

WAC Write Anything to Clear: Writing anything clears the value.RC Read to Clear: Contents is cleared after the read. Writes have no effect.LL Latch Low: Clear on read of register.LH Latch High: Clear on read of register.SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no

effect. Contents can be read.SS Self-Setting: Contents are self-setting after being cleared. Writes of one have no

effect. Contents can be read.RO/LH Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it

is read, the bit will either remain high if the high condition remains, or will go low if the high condition has been removed. If the bit has not been read, the bit will remain high regardless of a change to the high condition. This mode is used in some Ethernet PHY registers.

NASR Not Affected by Software Reset. The state of NASR bits do not change on assertion of a software reset.

RESERVED Reserved Field: Reserved fields must be written with zeros to ensure future compati-bility. The value of reserved bits is not guaranteed on a read.


LAN9252

2.0 GENERAL DESCRIPTIONThe LAN9252 is a 2/3-port EtherCAT slave controller with dual integrated Ethernet PHYs which each contain a full-duplex 100BASE-TX transceiver and support 100Mbps (100BASE-TX) operation. The LAN9252 supports HP Auto-MDIX, allowing the use of direct connect or cross-over LAN cables. 100BASE-FX is supported via an external fibertransceiver.

The LAN9252 includes an EtherCAT slave controller with 4K bytes of Dual Port memory (DPRAM) and 3 Fieldbus Mem-ory Management Units (FMMUs). Each FMMU performs the task of mapping logical addresses to physical addresses.The EtherCAT slave controller also includes 4 SyncManagers to allow the exchange of data between the EtherCAT mas-ter and the local application. Each SyncManager's direction and mode of operation is configured by the EtherCAT mas-ter. Two modes of operation are available: buffered mode or mailbox mode. In the buffered mode, both the localmicrocontroller and EtherCAT master can write to the device concurrently. The buffer within the LAN9252 will alwayscontain the latest data. If newer data arrives before the old data can be read out, the old data will be dropped. In mailboxmode, access to the buffer by the local microcontroller and the EtherCAT master is performed using handshakes, guar-anteeing that no data will be dropped.

Two user selectable host bus interface options are available:

• Indexed register accessThis implementation provides three index/data register banks, each with independent Byte/WORD to DWORD conversion. Internal registers are accessed by first writing one of the three index registers, followed by reading or writing the corresponding data register. Three index/data register banks support up to 3 independent driver threads without access conflicts. Each thread can write its assigned index register without the issue of another thread overwriting it. Two 16-bit cycles or four 8-bit cycles are required within the same 32-bit index/data register - however, these access can be interleaved. Direct (non-indexed) read and write accesses are supported to the process data FIFOs. The direct FIFO access provides independent Byte/WORD to DWORD conversion, support-ing interleaved accesses with the index/data registers.

• Multiplexed address/data busThis implementation provides a multiplexed address and data bus with both single phase and dual phase address support. The address is loaded with an address strobe followed by data access using a read or write strobe. Two back to back 16-bit data cycles or 4 back to back 8-bit data cycles are required within the same 32-bit DWORD. These accesses must be sequential without any interleaved accesses to other registers. Burst read and write accesses are supported to the process data FIFOs by performing one address cycle followed by multiple read or write data cycles.

The HBI supports 8/16-bit operation with big, little, and mixed endian operations. Two process data RAM FIFOs inter-face the HBI to the EtherCAT slave controller and facilitate the transferring of process data information between the hostCPU and the EtherCAT slave. A configurable host interrupt pin allows the device to inform the host CPU of any internalinterrupts.

An SPI / Quad SPI slave controller provides a low pin count synchronous slave interface that facilitates communicationbetween the device and a host system. The SPI / Quad SPI slave allows access to the System CSRs, internal FIFOsand memories. It supports single and multiple register read and write commands with incrementing, decrementing andstatic addressing. Single, Dual and Quad bit lanes are supported with a clock rate of up to 80 MHz.

The LAN9252 supports numerous power management and wakeup features. The LAN9252 can be placed in a reducedpower mode and can be programmed to issue an external wake signal (IRQ) via several methods, including “MagicPacket”, “Wake on LAN”, wake on broadcast, wake on perfect DA, and “Link Status Change”. This signal is ideal fortriggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power statevia a host processor command or one of the wake events.

For simple digital modules without microcontrollers, the LAN9252 can also operate in Digital I/O Mode where 16 digitalsignals can be controlled or monitored by the EtherCAT master.

To enable star or tree network topologies, the device can be configured as a 3-port slave, providing an additional MIIport. This port can be connected to an external PHY, forming a tap along the current daisy chain, or to another LAN9252creating a 4-port solution. The MII port can point upstream (as Port 0) or downstream (as Port 2).

LED support consists of a standard RUN indicator and a LINK / Activity indicator per port. A 64-bit distributed clock isincluded to enable high-precision synchronization and to provide accurate information about the local timing of dataacquisition.

The LAN9252 can be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator.The linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for lower systempower dissipation.


LAN9252

The LAN9252 is available in commercial, industrial, and extended industrial temperature ranges. Figure 2-1 details atypical system application, while Figure 2-2 provides an internal block diagram of the LAN9252.

The LAN9252 can operate in Microcontroller, Expansion, or Digital I/O mode:

FIGURE 2-1: SYSTEM BLOCK DIAGRAM

FIGURE 2-2: INTERNAL BLOCK DIAGRAM

LAN9252Microprocessor/Microcontroller

Local Bus

EEPROM

Magnetics RJ45

25MHz

Magnetics RJ45

EtherCAT SlaveEtherCAT

Master

EtherCAT Slave

EtherCAT Slave

PHY RJ45

EtherCAT Slave

100 PHYw/ fiber

Registers

EtherCAT Slave Controller

SyncManager

FMMU

ESC Address Space

Registers / RAM

Loopback

Port 0

Auto Fowarder

Loopback

Port 2

Auto Fowarder

LEDController

To optional LEDs

System Interrupt

Controller

IRQ

System Clocks/Reset Controller

External25MHz Crystal

I2C EEPROM

100 PHYw/ fiber

Registers

LAN9252

Ethernet

Ethernet

Parallel Data Interface

To 8/16-bitHost Bus, MII, SPI, Digital IOs, GPIOs

To I2C

Loopback

Port 1

Auto Fowarder

MII


LAN9252

Microcontroller Mode: The LAN9252 communicates with the microcontroller through an SRAM-like slave interface.The simple, yet highly functional host bus interface provides a glue-less connection to most common 8 or 16-bit micro-processors and microcontrollers as well as 32-bit microprocessors with an 8 or 16-bit external bus.

Alternatively, the device can be accessed via SPI or Quad SPI, while also providing up to 16 inputs or outputs for generalpurpose usage.

Expansion Mode: While the device is in SPI or Quad SPI mode, a third networking port can be enabled to provide anadditional MII port. This port can be connected to an external PHY, to enable star or tree network topologies, or toanother LAN9252 to create a four port solution. This port can be configured for the upstream or downstream direction.

Digital I/O Mode: For simple digital modules without microcontrollers, the LAN9252 can operate in Digital I/O Modewhere 16 digital signals can be controlled or monitored by the EtherCAT master. Six control signals are also provided.

Figure 2-3 provides a system level overview of each mode of operation.

FIGURE 2-3: MODES OF OPERATION

LAN9252

Microprocessor/Microcontroller

SPI / Quad SPI

LAN9252


Host Bus Interface

Magnetics or Fiber Xcvr

RJ45

or Fiber


RJ45

or Fiber


RJ45

or Fiber


RJ45

or Fiber

Microcontroller Mode(via Host Bus Interface)

Microcontroller Mode(via SPI)

Digital I/Os

LAN9252

PHY

MII

LAN9252Magnetics or Fiber XcvrRJ45

or Fiber


RJ45

or Fiber


RJ45

or Fiber


RJ45

or Fiber


Digital I/O Mode

Expansion Mode

GPIOs


SPI / Quad SPI

RJ45

or Fiber


LAN9252

3.0 PIN DESCRIPTIONS AND CONFIGURATION

3.1 64-QFN Pin Assignments

FIGURE 3-1: 64-QFN PIN ASSIGNMENTS (TOP VIEW)

Note: When a “#” is used at the end of the signal name, it indicates that the signal is active low. For example,RST# indicates that the reset signal is active low.

The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Sec-tion 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".

Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.

(Connect exposed pad to ground with a via field)VSS

LAN925264-QFN(Top View)

5

6

7

8

9

10

11

12

21 22 23 24 25 26 27 28

44

43

42

41

40

39

38

37

60 59 58 57 56 55 54 53

FXLOSEN

REG_EN

FXSDA/FXLOSA/FXSDENA

FXSDB/FXLOSB/FXSDENB

RST#

D2/AD2/SOF/SIO2

D1/AD1/EOF/SO/SIO1

VDDIO

LINKACTLED1/TDI/CHIP_MODE1

RUNLED/E2PSIZE

EESCL/TCK

VDDCR

D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK

D3/AD3/WD_TRIG/SIO3

RB

IAS

VD

D12

TX1

VD

D33

TX

RX

1

VD

D33

BIA

S

RX

PA

CS/

DIG

IO13

/GPI

13/G

PO13

/MII

_RX

D1

A1/

ALE

LO

/OE_

EX

T/M

II_C

LK

25

D11

/AD

11/D

IGIO

5/G

PI5/

GPO

5/M

II_T

XD

0

D12

/AD

12/D

IGIO

6/G

PI6/

GPO

6/M

II_T

XD

1

VD

DIO

D9/

AD

9/LA

TC

H_I

N/S

CK

TX

NA

EESDA/TMS

TX

PA

A2/

AL

EH

I/D

IGIO

10/G

PI10

/GPO

10/

LIN

KA

CTL

ED

2/M

II_L

INK

POL

RX

NA

VD

DC

RIRQ

52 5162 61

3

4

13

14

19 20 29 30

36

35

46

45D

10/A

D10

/DIG

IO4/

GPI

4/G

PO4/

MII

_TX

EN

A3/

DIG

IO11

/GPI

11/G

PO11

/MII

_RX

DV

A4/

DIG

IO12

/GPI

12/G

PO12

/MII

_RX

D0

WR

/EN

B/D

IGIO

14/G

PI14

/GPO

14/M

II_R

XD

2

VDDCR

VDD33

OSCVSS

OSCVDD12V

DD

12T

X2

RX

PB

RX

NB

TX

PB

TESTMODE

D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO

D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC

VDDIO

1

2OSCO

OSCI

16

15

D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0

D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1

17 18

D0/

AD

0/W

D_S

TATE

/SI/

SIO

0

SYN

C1/

LATC

H1

32V

DD

IO

RD

/RD

_WR

/DIG

IO15

/GPI

15/G

PO15

/MII

_RX

D3

31

34

33 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER

SYNC0/LATCH0

48

VDDIO47

LINKACTLED0/TDO/CHIP_MODE0

50 49

D5/

AD

5/O

UT

VA

LID

/SC

S#

D4/

AD

4/D

IGIO

3/G

PI3/

GPO

3/M

II_L

INK

64

TX

NB

VD

D33

TX

RX

2

63


LAN9252

Table 3-1 details the 64-QFN package pin assignments in table format. As shown, select pin functions may changebased on the device’s mode of operation. For modes where a specific pin has no function, the table cell will be markedwith “-”.

TABLE 3-1: 64-QFN PACKAGE PIN ASSIGNMENTS

Pin Number

HBI Indexed Mode Pin Name

HBI Multiplexed Mode Pin Name

Digital I/O Mode Pin Name

SPI with GPIO Mode Pin Name

SPI with MII Mode Pin Name

1 OSCI

2 OSCO

3 OSCVDD12

4 OSCVSS

5 VDD33

6 VDDCR

7 REG_EN

8 FXLOSEN

9 FXSDA/FXLOSA/FXSDENA

10 FXSDB/FXLOSB/FXSDENB

11 RST#

12 D2 AD2 SOF SIO2

13 D1 AD1 EOF SO/SIO1

14 VDDIO

15 D14 AD14 DIGIO8 GPI8/GPO8 MII_TXD3/TX_SHIFT1


17 D0 AD0 WD_STATE SI/SIO0

18 SYNC1/LATCH1

19 D9 AD9 LATCH_IN SCK

20 VDDIO

21 D12 AD12 DIGIO6 GPI6/GPO6 MII_TXD1


23 D10 AD10 DIGIO4 GPI4/GPO4 MII_TXEN

24 VDDCR

25 A1 ALELO OE_EXT - MII_CLK25

26 A3 - DIGIO11 GPI11/GPO11 MII_RXDV

27 A4 - DIGIO12 GPI12/GPO12 MII_RXD0

28 CS DIGIO13 GPI13/GPO13 MII_RXD1

29 A2 ALEHI DIGIO10 GPI10/GPO10 LINKACTLED2/MII_LINKPOL

30 WR/ENB DIGIO14 GPI14/GPO14 MII_RXD2


LAN9252

31 RD/RD_WR DIGIO15 GPI15/GPO15 MII_RXD3

32 VDDIO

33 A0/D15 AD15 DIGIO9 GPI9/GPO9 MII_RXER

34 SYNC0/LATCH0

35 D3 AD3 WD_TRIG SIO3

36 D6 AD6 DIGIO0 GPI0/GPO0 MII_RXCLK

37 VDDIO

38 VDDCR

39 D7 AD7 DIGIO1 GPI1/GPO1 MII_MDC

40 D8 AD8 DIGIO2 GPI2/GPO2 MII_MDIO

41 TESTMODE

42 EESDA/TMS

43 EESCL/TCK

44 IRQ

45 RUNLED/E2PSIZE

46 LINKACTLED1/TDI/CHIP_MODE1

47 VDDIO

48 LINKACTLED0/TDO/CHIP_MODE0

49 D4 AD4 DIGIO3 GPI3/GPO3 MII_LINK

50 D5 AD5 OUTVALID SCS#

51 VDD33TXRX1

52 TXNA

53 TXPA

54 RXNA

55 RXPA

56 VDD12TX1

57 RBIAS

58 VDD33BIAS

59 VDD12TX2

60 RXPB

61 RXNB

62 TXPB

63 TXNB

64 VDD33TXRX2

Exposed Pad VSS

TABLE 3-1: 64-QFN PACKAGE PIN ASSIGNMENTS (CONTINUED)

Pin Number







LAN9252

3.2 64-TQFP-EP Pin Assignments

.

FIGURE 3-2: 64-TQFP-EP PIN ASSIGNMENTS (TOP VIEW)

Note: When an “#” is used at the end of the signal name, it indicates that the signal is active low. For example,RST# indicates that the reset signal is active low.

The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Sec-tion 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".

Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.

(Connect exposed pad to ground with a via field)VSS

LAN925264-TQFP-EP

(Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

FXLO

SEN

RE

G_E

N

FXSD

A/F

XL

OSA

/FX

SDE

NA

FXSD

B/F

XL

OSB

/FX

SDE

NB

RST

#

D2/

AD

2/SO

F/SI

O2

D1/

AD

1/E

OF/

SO/S

IO1

VD

DIO

VD

DC

R

VD

D33

OSC

VSS

OSC

VD

D12

OSC

O

OSC

I

D13

/AD

13/D

IGIO

7/G

PI7/

GPO

7/M

II_T

XD

2/TX

_SH

IFT0

D14

/AD

14/D

IGIO

8/G

PI8/

GPO

8/M

II_T

XD

3/TX

_SH

IFT1

CS/DIGIO13/GPI13/GPO13/MII_RXD1

A1/ALELO/OE_EXT/MII_CLK25

D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0

D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1

VDDIO

D9/AD9/LATCH_IN/SCK

A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL

VDDCR

D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN

A3/DIGIO11/GPI11/GPO11/MII_RXDV

A4/DIGIO12/GPI12/GPO12/MII_RXD0

WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2

D0/AD0/WD_STATE/SI/SIO0

SYNC1/LATCH1

VDDIO

RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3

LIN

KA

CTL

ED1/

TDI/

CH

IP_M

OD

E1

RU

NL

ED

/E2P

SIZ

E

EE

SCL

/TC

K

VD

DC

R

D6/

AD

6/D

IGIO

0/G

PI0/

GPO

0/M

II_R

XC

LK

D3/

AD

3/W

D_T

RIG

/SIO

3

EE

SDA

/TM

S

IRQ

TE

STM

OD

E

D8/

AD

8/D

IGIO

2/G

PI2/

GPO

2/M

II_M

DIO

D7/

AD

7/D

IGIO

1/G

PI1/

GPO

1/M

II_M

DC

VD

DIO

A0/

D15

/AD

15/D

IGIO

9/G

PI9/

GPO

9/M

II_R

XE

R

SYN

C0/

LA

TC

H0

VD

DIO

LIN

KA

CTL

ED0/

TDO

/CH

IP_M

OD

E0

RBIAS

VDD12TX1

VDD33TXRX1

VDD33BIAS

RXPA

TXNA

TXPA

RXNA

VDD12TX2

RXPB

RXNB

TXPB

D5/AD5/OUTVALID/SCS#

D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK

TXNB

VDD33TXRX2


LAN9252

Table 3-2 details the 64-TQFP-EP package pin assignments in table format. As shown, select pin functions may changebased on the device’s mode of operation. For modes where a specific pin has no function, the table cell will be markedwith “-”.

TABLE 3-2: 64-TQFP-EP PACKAGE PIN ASSIGNMENTS

Pin Number






1 OSCI

2 OSCO

3 OSCVDD12

4 OSCVSS

5 VDD33

6 VDDCR

7 REG_EN

8 FXLOSEN

9 FXSDA/FXLOSA/FXSDENA

10 FXSDB/FXLOSB/FXSDENB

11 RST#

12 D2 AD2 SOF SIO2

13 D1 AD1 EOF SO/SIO1

14 VDDIO



17 D0 AD0 WD_STATE SI/SIO0

18 SYNC1/LATCH1

19 D9 AD9 LATCH_IN SCK

20 VDDIO



23 D10 AD10 DIGIO4 GPI4/GPO4 MII_TXEN

24 VDDCR

25 A1 ALELO OE_EXT - MII_CLK25

26 A3 - DIGIO11 GPI11/GPO11 MII_RXDV

27 A4 - DIGIO12 GPI12/GPO12 MII_RXD0

28 CS DIGIO13 GPI13/GPO13 MII_RXD1

29 A2 ALEHI DIGIO10 GPI10/GPO10 LINKACTLED2/MII_LINKPOL

30 WR/ENB DIGIO14 GPI14/GPO14 MII_RXD2


LAN9252

31 RD/RD_WR DIGIO15 GPI15/GPO15 MII_RXD3

32 VDDIO

33 A0/D15 AD15 DIGIO9 GPI9/GPO9 MII_RXER

34 SYNC0/LATCH0

35 D3 AD3 WD_TRIG SIO3

36 D6 AD6 DIGIO0 GPI0/GPO0 MII_RXCLK

37 VDDIO

38 VDDCR

39 D7 AD7 DIGIO1 GPI1/GPO1 MII_MDC

40 D8 AD8 DIGIO2 GPI2/GPO2 MII_MDIO

41 TESTMODE

42 EESDA/TMS

43 EESCL/TCK

44 IRQ

45 RUNLED/E2PSIZE

46 LINKACTLED1/TDI/CHIP_MODE1

47 VDDIO

48 LINKACTLED0/TDO/CHIP_MODE0

49 D4 AD4 DIGIO3 GPI3/GPO3 MII_LINK

50 D5 AD5 OUTVALID SCS#

51 VDD33TXRX1

52 TXNA

53 TXPA

54 RXNA

55 RXPA

56 VDD12TX1

57 RBIAS

58 VDD33BIAS

59 VDD12TX2

60 RXPB

61 RXNB

62 TXPB

63 TXNB

64 VDD33TXRX2

Exposed Pad VSS

TABLE 3-2: 64-TQFP-EP PACKAGE PIN ASSIGNMENTS (CONTINUED)

Pin Number







LAN9252

3.3 Pin DescriptionsThis section contains descriptions of the various LAN9252 pins. The pin descriptions have been broken into functionalgroups as follows:

• LAN Port A Pin Descriptions• LAN Port B Pin Descriptions• LAN Port A & B Power and Common Pin Descriptions• EtherCAT MII Port & Configuration Strap Pin Descriptions• Host Bus Pin Descriptions• SPI/SQI Pin Descriptions• EtherCAT Distributed Clock Pin Descriptions• EtherCAT Digital I/O and GPIO Pin Descriptions• EEPROM Pin Descriptions• LED & Configuration Strap Pin Descriptions• Miscellaneous Pin Descriptions• JTAG Pin Descriptions• Core and I/O Power Pin Descriptions

TABLE 3-3: LAN PORT A PIN DESCRIPTIONSNum Pins Name Symbol


1

Port A TP TX/RX Positive

Channel 1 TXPAAIO

Port A Twisted Pair Transmit/Receive Positive Channel 1. See Note 1

Port A FX TX Positive OLVPECL

Port A Fiber Transmit Positive.

1

Port A TP TX/RX Negative

Channel 1 TXNAAIO

Port A Twisted Pair Transmit/Receive Negative Channel 1. See Note 1.

Port A FX TX Negative OLVPECL

Port A Fiber Transmit Negative.

1

Port A TP TX/RX Positive

Channel 2 RXPAAIO

Port A Twisted Pair Transmit/Receive Positive Channel 2. See Note 1.

Port A FX RX Positive AI

Port A Fiber Receive Positive.

1

Port A TP TX/RX Negative

Channel 2 RXNAAIO

Port A Twisted Pair Transmit/Receive Negative Channel 2. See Note 1.

Port A FX RX Negative AI

Port A Fiber Receive Negative.


LAN9252

Note 1: In copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions asthe receive pair. The pin name symbols for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will beswapped internally.

Note 2: Configuration strap pins are identified by an underlined symbol name. Configuration strap values arelatched on power-on reset or RST# de-assertion. Refer to Section 7.0, "Configuration Straps," on page 51for more information.

1

Port A FX Signal Detect

(SD)FXSDA ILVPECL

Port A Fiber Signal Detect. When FX-LOS mode is not selected, this pin functions as the Signal Detect input from the external transceiver. A level above 2 V (typ.) indicates valid signal.

When FX-LOS mode is selected, the input buffer is disabled.

Port A FX Loss Of Signal

(LOS) FXLOSAIS

(PU)

Port A Fiber Loss of Signal. When FX-LOS mode is selected (via fx_los_strap_1), this pin functions as the Loss of Signal input from the external trans-ceiver. A high indicates LOS while a low indicates valid signal.

When FX-LOS mode is not selected, the input buffer and pull-up are disabled.

Port A FX-SD Enable Strap FXSDENA AI

Port A FX-SD Enable. When FX-LOS mode is not selected, this strap input selects between FX-SD and copper twisted pair mode. A level above 1 V (typ.) selects FX-SD.


See Note 2.

Note: Port A is connected to the EtherCAT port 0 or 2.

TABLE 3-4: LAN PORT B PIN DESCRIPTIONSNum Pins Name Symbol


1

Port B TP TX/RX Positive

Channel 1 TXPBAIO

Port B Twisted Pair Transmit/Receive Positive Channel 1. See Note 3

Port B FX TX Positive OLVPECL

Port B Fiber Transmit Positive.

1

Port B TP TX/RX Negative

Channel 1 TXNBAIO

Port B Twisted Pair Transmit/Receive Negative Channel 1. See Note 3.

Port B FX TX Negative OLVPECL

Port B Fiber Transmit Negative.

TABLE 3-3: LAN PORT A PIN DESCRIPTIONS (CONTINUED)Num Pins Name Symbol



LAN9252

Note 3: In copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions asthe receive pair. The pin name symbols for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will beswapped internally.


1

Port BTP TX/RX Positive

Channel 2 RXPBAIO

Port B Twisted Pair Transmit/Receive Positive Channel 2. See Note 3.

Port B FX RX Positive AI

Port B Fiber Receive Positive.

1

Port B TP TX/RX Negative

Channel 2 RXNBAIO

Port B Twisted Pair Transmit/Receive Negative Channel 2. See Note 3.

Port B FX RX Negative AI

Port B Fiber Receive Negative.

1

Port B FX Signal Detect

(SD)FXSDB ILVPECL

Port B Fiber Signal Detect. When FX-LOS mode is not selected, this pin functions as the Signal Detect input from the external transceiver. A level above 2 V (typ.) indicates valid signal.


Port B FX Loss Of Signal

(LOS) FXLOSBIS

(PU)

Port B Fiber Loss of Signal. When FX-LOS mode is selected (via fx_los_strap_2), this pin functions as the Loss of Signal input from the external trans-ceiver. A high indicates LOS while a low indicates valid signal.

When FX-LOS mode is not selected, the input buffer and pull-up are disabled.

Port B FX-SD Enable Strap FXSDENB AI

Port B FX-SD Enable. When FX-LOS mode is not selected, this strap input selects between FX-SD and copper twisted pair mode. A level above 1 V (typ.) selects FX-SD.


See Note 4.

Note: Port B is connected to EtherCAT port 1.

TABLE 3-4: LAN PORT B PIN DESCRIPTIONS (CONTINUED)Num Pins Name Symbol



LAN9252

Note 5: Refer to Section 4.0, "Power Connections," on page 29, the device reference schematics, and the deviceLANCheck schematic checklist for additional connection information.

TABLE 3-5: LAN PORT A & B POWER AND COMMON PIN DESCRIPTIONSNum Pins Name Symbol


1 Bias Reference RBIAS AI

Used for internal bias circuits. Connect to an exter-nal 12.1 kΩ, 1% resistor to ground.

Refer to the device reference schematic for connec-tion information.

Note: The nominal voltage is 1.2 V and theresistor will dissipate approximately1 mW of power.

1Port A and B

FX-LOS Enable Strap

FXLOSEN AI

Port A and B FX-LOS Enable. This 3 level strap input selects between FX-LOS and FX-SD / copper twisted pair mode.

A level below 1 V (typ.) selects FX-SD / copper twisted pair for ports A and B, further determined by FXSDENA and FXSDENB.

A level of 1.5 V selects FX-LOS for port A and FX-SD / copper twisted pair for port B, further deter-mined by FXSDENB.

A level above 2 V (typ.) selects FX-LOS for ports A and B.

1+3.3 V Port A Analog Power

SupplyVDD33TXRX1 P

See Note 5.

1+3.3 V Port B Analog Power

SupplyVDD33TXRX2 P

See Note 5.

1+3.3 V Master

Bias Power Supply

VDD33BIAS PSee Note 5.

1

Port A Transmitter

+1.2 V Power Supply

VDD12TX1 P

This pin is supplied from either an external 1.2 V supply or from the device’s internal regulator via the PCB. This pin must be tied to the VDD12TX2 pin for proper operation.

See Note 5.

1

Port B Transmitter

+1.2 V Power Supply

VDD12TX2 P

This pin is supplied from either an external 1.2 V supply or from the device’s internal regulator via the PCB. This pin must be tied to the VDD12TX1 pin for proper operation.

See Note 5.


LAN9252

Note 6: A series terminating resistor is recommended for the best PCB signal integrity.Note 7: An external supplemental pull-up may be needed, depending upon the input current loading of the external

MAC/PHY device.


TABLE 3-6: ETHERCAT MII PORT & CONFIGURATION STRAP PIN DESCRIPTIONSNum Pins Name Symbol


1 25 MHz Clock MII_CLK25 VO12Note 6This pin is a free-running 25 MHz clock that can be used as the clock input to the PHY.

4 Receive Data MII Port MII_RXD[3:0]VIS(PD)

These pins are the receive data from the external PHY.

1 Receive Data Valid MII Port MII_RXDVVIS(PD)

This pin is the receive data valid signal from the external PHY.

1 Receive Error MII Port MII_RXERVIS(PD)

This pin is the receive error signal from the external PHY.

1 Receive Clock MII Port MII_RXCLKVIS(PD)

This pin is the receive clock from the external PHY.

4

Transmit Data MII Port MII_TXD[3:0] VO8

These pins are the transmit data to the external PHY.

MII Transmit Timing Shift

Configuration Strap

TX_SHIFT[1:0]VIS(PU)

Note 7

These straps configure the value of the external MII Bus TX timing shift hard-strap. See Note 8.

TX_SHIFT[1] is on MII_TXD[3] and TX_SHIFT[0] is on MII_TXD[2].

1 Transmit Data Enable MII Port MII_TXEN VO8This pin is the transmit data enable signal to the external PHY.

1 Link StatusMII Port MII_LINK VISThis pin is the provided by the PHY to indicate that a 100 Mbit/s Full Duplex link is established. The polar-ity is configurable via the link_pol_strap_mii strap.

1 SMI Clock MII_MDC VO8 This pin is the serial management clock to the exter-nal PHY.

1 SMI Data MII_MDIO VIS/VO8

This pin is the serial management interface data input/output to the external PHY.

Note: An external pull-up is required to ensurethat the non-driven state of the MDIOsignal is a logic one.


LAN9252

TABLE 3-7: HOST BUS PIN DESCRIPTIONSNum Pins Name Symbol


1

Read RD VIS

This pin is the host bus read strobe.

Normally active low, the polarity can be changed via the HBI Read, Read/Write Polarity bit of the PDI Configuration Register (HBI Modes).

Read or Write RD_WR VIS

This pin is the host bus direction control. Used in conjunction with the ENB pin, it indicates a read or write operation.

The normal polarity is read when 1, write when 0 (R/nW) but can be changed via the HBI Read, Read/Write Polarity bit of the PDI Configuration Register (HBI Modes).

1

Write WR VIS

This pin is the host bus write strobe.

Normally active low, the polarity can be changed via the HBI Write, Enable Polarity bit of the PDI Config-uration Register (HBI Modes).

Enable ENB VIS

This pin is the host bus data enable strobe. Used in conjunction with the RD_WR pin it indicates the data phase of the operation.

Normally active low, the polarity can be changed via the HBI Write, Enable Polarity bit of the PDI Config-uration Register (HBI Modes).

1 Chip Select CS VIS

This pin is the host bus chip select and indicates that the device is selected for the current transfer.

Normally active low, the polarity can be changed via the HBI Chip Select Polarity bit of the PDI Configu-ration Register (HBI Modes).

5 Address A[4:0] VIS

These pins provide the address for non-multiplexed address mode.

In 16-bit data mode, bit 0 is not used.


LAN9252

16

Data D[15:0] VIS/VO8

These pins are the host bus data bus for non-multi-plexed address mode.

In 8-bit data mode, bits 15-8 are not used and their input and output drivers are disabled.

Address & Data AD[15:0] VIS/VO8

These pins are the host bus address / data bus for multiplexed address mode.

Bits 15-8 provide the upper byte of address for sin-gle phase multiplexed address mode.

Bits 7-0 provide the lower byte of address for single phase multiplexed address mode and both bytes of address for dual phase multiplexed address mode.

In 8-bit data dual phase multiplexed address mode, bits 15-8 are not used and their input and output drivers are disabled.

1 Address Latch Enable High ALEHI VIS

This pin indicates the address phase for multiplexed address modes. It is used to load the higher address byte in dual phase multiplexed address mode.

Normally active low (address saved on rising edge), the polarity can be changed via the HBI ALE Polar-ity bit of the PDI Configuration Register (HBI Modes).

1 Address Latch Enable Low ALELO VIS

This pin indicates the address phase for multiplexed address modes. It is used to load both address bytes in single phase multiplexed address mode and the lower address byte in dual phase multi-plexed address mode.

Normally active low (address saved on rising edge), the polarity can be changed via the HBI ALE Polar-ity bit of the PDI Configuration Register (HBI Modes).

TABLE 3-7: HOST BUS PIN DESCRIPTIONS (CONTINUED)Num Pins Name Symbol



LAN9252

Note 9: Although this pin is an output for SPI instructions, it includes a pull-up since it is also SIO bit 1.

TABLE 3-8: SPI/SQI PIN DESCRIPTIONSNum Pins Name Symbol


1 SPI/SQI Slave Chip Select SCS#VIS(PU)

This pin is the SPI/SQI slave chip select input. When low, the SPI/SQI slave is selected for SPI/SQI transfers. When high, the SPI/SQI serial data out-put(s) is(are) 3-stated.

1 SPI/SQI Slave Serial Clock SCKVIS(PU)

This pin is the SPI/SQI slave serial clock input.

4

SPI/SQI Slave Serial Data

Input/OutputSIO[3:0] VIS/VO8(PU)

These pins are the SPI/SQI slave data input and output for multiple bit I/O.

SPI Slave Serial Data Input SI

VIS(PU)

This pin is the SPI slave serial data input. SI is shared with the SIO0 pin.

SPI Slave Serial Data Output SO

VO8(PU)

Note 9

This pin is the SPI slave serial data output. SO is shared with the SIO1 pin.

TABLE 3-9: ETHERCAT DISTRIBUTED CLOCK PIN DESCRIPTIONSNum Pins Name Symbol


2

Sync SYNC[1]SYNC[0] VO8These pins are the Distributed Clock Sync (OUT) or Latch (IN) signals. The direction is bitwiseconfigurable.

Note: These signals are not driven (highimpedance) until the EEPROM isloaded.

Latch LATCH[1]LATCH[0] VIS

TABLE 3-10: ETHERCAT DIGITAL I/O AND GPIO PIN DESCRIPTIONSNum Pins Name Symbol


16

General Purpose Input GPI[15:0] VIS

These pins are the general purpose inputs and are directly mapped into the General Purpose Inputs Register. Consistency of the general purpose inputs is not provided.

General Purpose Output GPO[15:0] VO8

These pins are the general purpose outputs and reflect the values of the General Purpose Outputs Register without watchdog protection.


16 Digital I/O DIGIO[15:0] VIS/VO8

These pins are the input/output or bidirectional data.


1 Output Valid OUTVALID VO8

This pin indicates that the outputs are valid and can be captured into external registers.

Note: The signal is not driven (high imped-ance) until the EEPROM is loaded.


LAN9252

1 Latch In LATCH_IN VISThis pin is the external data latch signal. The input data is sampled each time a rising edge of LATCH_IN is recognized.

1 Watchdog Trigger WD_TRIG VO8

This pin is the SyncManager Watchdog Trigger out-put.


1 Watchdog State WD_STATE VO8

This pin is the SyncManager Watchdog State out-put. A 0 indicates the watchdog has expired.


1 Start of Frame SOF VO8

This pin is the Start of Frame output and indicates the start of an Ethernet/EtherCAT frame.


1 End of Frame EOF VO8

This pin is the End of Frame output and indicates the end of an Ethernet/EtherCAT frame.


1 Output Enable OE_EXT VIS This pin is the Output Enable input. When low, it clears the output data.

TABLE 3-11: EEPROM PIN DESCRIPTIONSNum Pins Name Symbol


1EEPROM I2C

Serial Data Input/Output

EESDA VIS/VOD8

When the device is accessing an external EEPROM this pin is the I2C serial data input/open-drain out-put.

Note: This pin must be pulled-up by an exter-nal resistor at all times.

1 EEPROM I2C

Serial Clock EESCL VOD8

When the device is accessing an external EEPROM this pin is the I2C clock open-drain output.

Note: This pin must be pulled-up by an exter-nal resistor at all times.

TABLE 3-10: ETHERCAT DIGITAL I/O AND GPIO PIN DESCRIPTIONS (CONTINUED)Num Pins Name Symbol



LAN9252

TABLE 3-12: LED & CONFIGURATION STRAP PIN DESCRIPTIONSNum Pins Name Symbol


1

Link/ActivityLED Port 2 LINKACTLED2

VOD12/VOS12

This pin is the Link/Activity LED output (off=no link, on=link without activity, blinking=link and activity) for port 2.

This pin is configured to be an open-drain/open-source output. The choice of open-drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset.

Note: Refer to Section 12.10, "LEDs," onpage 208 to additional information.

MII Port Link Polarity Configuration

Strap

MII_LINKPOL VIS(PU)

This strap configures the polarity of the MII_LINK pin by setting the value of link_pol_strap_mii. See Note 10.

1

Run LED RUNLED VOD12/VOS12

This pin is the Run LED output and is controlled by the AL Status Register.

This pin is configured to be open-drain/open-source output. The choice of open-drain vs. open-source as well as the polarity of this pin depends upon the strap value sampled at reset.


EEPROM Size Configuration

StrapE2PSIZE VIS(PU)

This strap configures the value of the EEPROM size hard-strap. See Note 10.

A low selects 1K bits (128 x 8) through 16K bits (2K x 8).

A high selects 32K bits (4K x 8) through 4Mbits (512K x 8).

1

Link / Activity LED Port 1 LINKACTLED1

VOD12/VOS12




Chip Mode Configuration

Strap 1CHIP_MODE1 VIS(PU)

This strap, along with CHIP_MODE0, configures the value of the Chip Mode hard-strap. See Note 10.


LAN9252


1

Link / Activity LED Port 0 LINKACTLED0

VOD12/VOS12




Chip Mode Configuration

Strap 0CHIP_MODE0 VIS(PU)

This strap, along with CHIP_MODE1, configures the value of the Chip Mode hard-strap. See Note 10.

TABLE 3-13: MISCELLANEOUS PIN DESCRIPTIONSNum Pins Name Symbol


1 Interrupt Output IRQ VO8/VOD8

Interrupt request output. The polarity, source and buffer type of this signal is programmable via the Interrupt Configuration Register (IRQ_CFG). For more information, refer to Section 8.0, "System Interrupts," on page 53.

1 System Reset Input RST#VIS/VOD8

(PU)

As an input, this active low signal allows external hardware to reset the device. The device also con-tains an internal power-on reset circuit. Thus this signal may be left unconnected if an external hard-ware reset is not needed. When used this signal must adhere to the reset timing requirements as detailed in the Section 18.0, "Operational Character-istics," on page 307.

As an output, this signal is driven low during POR or in response to an EtherCAT reset command sequence from the Master Controller or Host inter-face.

1 Regulator Enable REG_EN AIWhen tied to 3.3 V, the internal 1.2 V regulators are enabled.

1 Test Mode TESTMODE VIS(PD)This pin must be tied to VSS for proper operation.

1 Crystal Input OSCI ICLK

External 25 MHz crystal input. This signal can also be driven by a single-ended clock oscillator. When this method is used, OSCO should be left uncon-nected.

1 Crystal Output OSCO OCLK External 25 MHz crystal output.

1 Crystal +1.2 V Power Supply OSCVDD12 PSupplied by the on-chip regulator unless configured for regulator off mode via REG_EN.

1 Crystal Ground OSCVSS P Crystal ground.

TABLE 3-12: LED & CONFIGURATION STRAP PIN DESCRIPTIONS (CONTINUED)Num Pins Name Symbol



LAN9252

Note 11: Refer to Section 4.0, "Power Connections," on page 29, the device reference schematic, and the deviceLANCheck schematic checklist for additional connection information.

TABLE 3-14: JTAG PIN DESCRIPTIONSNum Pins Name Symbol


1 JTAG Test Mux Select TMS VISJTAG test mode select

1 JTAG TestClock TCK VISJTAG test clock

1 JTAG TestData Input TDI VISJTAG data input

1 JTAG TestData Output TDO VO12JTAG data output

TABLE 3-15: CORE AND I/O POWER PIN DESCRIPTIONSNum Pins Name Symbol


1Regulator

+3.3 V Power Supply

VDD33 P

+3.3 V power supply for internal regulators. See Note 11.

Note: +3.3 V must be supplied to this pin evenif the internal regulators are disabled.

5+1.8 V to +3.3 V

Variable I/O Power

VDDIO P+1.8 V to +3.3 V variable I/O power. See Note 11.

3+1.2 V Digital Core Power

SupplyVDDCR P

Supplied by the on-chip regulator unless configured for regulator off mode via REG_EN.

1 µF and 470 pF decoupling capacitors in parallel to ground should be used on pin 6. See Note 11.

1 pad Ground VSS P

Common ground. This exposed pad must be con-nected to the ground plane with a via array.


LAN9252

4.0 POWER CONNECTIONSFigure 4-1 and Figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respec-tively. Refer to the device reference schematic and the device LANCheck schematic checklist for additional information.Section 4.1 provides additional information on the devices internal voltage regulators.

FIGURE 4-1: POWER CONNECTIONS - REGULATORS ENABLED

+1.8 V to +3.3 V

VDDCR

Core Logic & PHY digital

VDD12TX2

Ethernet PHY 1Analog

1.0 µF0.1 ESR

VDD33BIAS

VDD33TXRX1

VSS

VDDCR


VDD12TX1

VDD33TXRX2

Ethernet Master Bias

IO Pads

To PHY1 Magnetics

To PHY2 Magnetics

Note: Bypass and bulk caps as needed for PCB

VDDIO

VDD33

+3.3 V

+3.3 V

470 pF

Crystal Oscillator

VSS

PLL(exposed pad)

(or separate 2.5V)

(or separate 2.5V)

VDDIO

VDDIO

VDDIO

VDDIO

VDDCR

OSCVDD12

OSCVSS

+3.3 V (IN)

+1.2 V (OUT)

Internal 1.2 V Core Regulator

enable

+3.3 V (IN)

+1.2 V (OUT)

Internal 1.2 V OscillatorRegulator

VSSenable

REG_EN

(Pin 6)


LAN9252

FIGURE 4-2: POWER CONNECTIONS - REGULATORS DISABLED

+1.8 V to +3.3 V

VDDCR

Core Logic & PHY digital

VDD12TX2


VDD33BIAS

VDD33TXRX1

VSS

VDDCR


VDD12TX1

VDD33TXRX2

Ethernet Master Bias

IO Pads

To PHY1 Magnetics

To PHY2 Magnetics

Note: Bypass and bulk caps as needed for PCB

VDDIO

VDD33

+3.3 V

+3.3 V

Crystal Oscillator

VSS

PLL(exposed pad)

(or separate 2.5V)

(or separate 2.5V)

VDDIO

VDDIO

VDDIO

VDDIO

VDDCR

OSCVDD12

OSCVSS

+3.3 V (IN)

+1.2 V (OUT)

Internal 1.2 V Core Regulator

enable

+3.3 V (IN)

+1.2 V (OUT)

Internal 1.2 V OscillatorRegulator

VSSenable

REG_EN

+1.2 V

(Pin 6)


LAN9252

4.1 Internal Voltage RegulatorsThe device contains two internal 1.2 V regulators:

• 1.2 V Core Regulator• 1.2 V Crystal Oscillator Regulator

4.1.1 1.2 V CORE REGULATORThe core regulator supplies 1.2 V volts to the main core digital logic, the I/O pads, and the PHYs’ digital logic and canbe used to supply the 1.2 V power to the PHY analog sections (via an external connection).

When the REG_EN input pin is connected to 3.3 V, the core regulator is enabled and receives 3.3 V on the VDD33 pin.A 1.0 uF 0.1 ESR capacitor must be connected to the VDDCR pin associated with the regulator.When the REG_EN input pin is connected to VSS, the core regulator is disabled. However, 3.3 V must still be suppliedto the VDD33 pin. The 1.2 V core voltage must then be externally input into the VDDCR pins.

4.1.2 1.2 V CRYSTAL OSCILLATOR REGULATORThe crystal oscillator regulator supplies 1.2 V volts to the crystal oscillator. When the REG_EN input pin is connected to3.3 V, the crystal oscillator regulator is enabled and receives 3.3 V on the VDD33 pin. An external capacitor is notrequired.

When the REG_EN input pin is connected to VSS, the crystal oscillator regulator is disabled. However, 3.3 V must stillbe supplied to the VDD33 pin. The 1.2 V crystal oscillator voltage must then be externally input into the OSCVDD12 pin.


LAN9252

5.0 REGISTER MAPThis chapter details the device register map and summarizes the various directly addressable System Control and Sta-tus Registers (CSRs). Detailed descriptions of the System CSRs are provided in the chapters corresponding to theirfunction. Additional indirectly addressable registers are available in the various sub-blocks of the device. These regis-ters are also detailed in their corresponding chapters.

Directly Addressable Registers• Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214• Section 5.1, "System Control and Status Registers," on page 34

Indirectly Addressable Registers• Section 11.2.16, "PHY Registers," on page 142• Section 12.14, "EtherCAT Core CSR Registers (Indirectly Addressable)," on page 223

Figure 5-1 contains an overall base register memory map of the device. This memory map is not drawn to scale, andshould be used for general reference only. Table 5-1 provides a summary of all directly addressable CSRs and theircorresponding addresses.

Note: Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 7.

Not all device registers are memory mapped or directly addressable. For details on the accessibility of thevarious device registers, refer the register sub-sections listed above.


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FIGURE 5-1: REGISTER ADDRESS MAP

000h

020h

300h314h

03Ch

01ChEtherCAT Process RAM Read FIFO

EtherCAT Process RAM Write FIFO

Test0E0h

0FCh

EtherCAT

318h

3FFh

Interrupts054h05Ch

GP Timer and Free Run Counter09Ch08Ch

Note: Not all registers are shown


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5.1 System Control and Status RegistersThe System CSRs are directly addressable memory mapped registers with a base address offset range of 050h to 314h.These registers are addressable by the Host via the Host Bus Interface (HBI) or SPI/SQI. For more information on thevarious device modes and their corresponding address configurations, see Section 2.0, "General Description," onpage 8.

Table 5-1 lists the System CSRs and their corresponding addresses in order. All system CSRs are reset to their defaultvalue on the assertion of a chip-level reset.

The System CSRs can be divided into the following sub-categories. Each of these sub-categories is located in the cor-responding chapter and contains the System CSR descriptions of the associated registers. The register descriptionsare categorized as follows:

• Section 6.2.3, "Reset Registers," on page 42• Section 6.3.5, "Power Management Registers," on page 47• Section 8.3, "Interrupt Registers," on page 56• Section 12.13, "EtherCAT CSR and Process Data RAM Access Registers (Directly Addressable)," on page 214• Section 16.1, "Miscellaneous System Configuration & Status Registers," on page 301

Note: Unlisted registers are reserved for future use.

TABLE 5-1: SYSTEM CONTROL AND STATUS REGISTERSAddress Register Name (Symbol)

000h-01Ch EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA)020h-03Ch EtherCAT Process RAM Write Data FIFO (ECAT_PRAM_WR_DATA)

050h Chip ID and Revision (ID_REV)054h Interrupt Configuration Register (IRQ_CFG)058h Interrupt Status Register (INT_STS)05Ch Interrupt Enable Register (INT_EN)064h Byte Order Test Register (BYTE_TEST)074h Hardware Configuration Register (HW_CFG)084h Power Management Control Register (PMT_CTRL)08Ch General Purpose Timer Configuration Register (GPT_CFG)090h General Purpose Timer Count Register (GPT_CNT)09Ch Free Running 25MHz Counter Register (FREE_RUN)

Reset Register1F8h Reset Control Register (RESET_CTL)

EtherCAT Registers300h EtherCAT CSR Interface Data Register (ECAT_CSR_DATA)304h EtherCAT CSR Interface Command Register (ECAT_CSR_CMD)308h EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN)30Ch EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD)310h EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN)314h EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD)


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5.2 Special Restrictions on Back-to-Back Cycles

5.2.1 BACK-TO-BACK WRITE-READ CYCLESIt is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. Theserestrictions concern reading registers after any write cycle that may affect the register. In all cases there is a delaybetween writing to a register and the new value becoming available to be read. In other cases, there is a delay betweenwriting to a register and the subsequent side effect on other registers.

In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established.These periods are specified in Table 5-2. The host processor is required to wait the specified period of time after writingto the indicated register before reading the resource specified in the table. Note that the required wait period is depen-dent upon the register being read after the write.

Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee thatthe minimum write-to-read timing restriction is met. Table 5-2 shows the number of dummy reads that are requiredbefore reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum cycletiming of 45ns. For microprocessors with slower busses the number of reads may be reduced as long as the total timeis equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are notrequired as long as the minimum time period is met.

Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficienttime between writes and read. It is required of the system design and register access mechanisms to ensure the propertiming. For example, a write and read to the same register may occur faster than a write and read to different registers.

For 8 and 16-bit write cycles, the wait time for the back-to-back write-read operation applies only to the writing of thelast BYTE or WORD of the register, which completes a single DWORD transfer.

For Indexed Address mode HBI operation, the wait time for the back-to-back write-read operation applies only to accessto the internal registers and FIFOs. It does not apply to the Host Bus Interface Index Registers or the Host Bus InterfaceConfiguration Register.

TABLE 5-2: READ AFTER WRITE TIMING RULES

After Writing... wait for this many nanoseconds...

or Perform this many Reads of BYTE_TEST…(assuming Tcyc of 45ns)

before reading...

any register 45 1 the same register or any other register affected

by the write

Interrupt Configuration Regis-ter (IRQ_CFG)

60 2 Interrupt Configuration Regis-ter (IRQ_CFG)

Interrupt Enable Register (INT_EN)


60 2 Interrupt Status Register (INT_STS)

Interrupt Status Register (INT_STS)



Power Management Control Register (PMT_CTRL)

165 4 Power Management Control Register (PMT_CTRL)




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5.2.2 BACK-TO-BACK READ CYCLESThere are also restrictions on specific back-to-back host read operations. These restrictions concern reading specificregisters after reading a resource that has side effects. In many cases there is a delay between reading the device, andthe subsequent indication of the expected change in the control and status register values.

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-lished. These periods are specified in Table 5-3. The host processor is required to wait the specified period of timebetween read operations of specific combinations of resources. The wait period is dependent upon the combination ofregisters being read.

Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee thatthe minimum wait time restriction is met. Table 5-3 below also shows the number of dummy reads that are required forback-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc(45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equalto, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long asthe minimum time period is met.

Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficienttime between reads. It is required of the system design and register access mechanisms to ensure the proper timing.For example, multiple reads to the same register may occur faster than reads to different registers.

For 8 and 16-bit read cycles, the wait time for the back-to-back read operation is required only after the reading of thelast BYTE or WORD of the register, which completes a single DWORD transfer. There is no wait requirement betweenthe BYTE or WORD accesses within the DWORD transfer.

General Purpose Timer Con-figuration Register

(GPT_CFG)

55 2 General Purpose Timer Con-figuration Register

(GPT_CFG)

170 4 General Purpose Timer Count Register (GPT_CNT)

EtherCAT Process RAM Write Data FIFO

(ECAT_PRAM_WR_DATA)

50 2 EtherCAT Process RAM Write Command Register

(ECAT_PRAM_WR_CMD)

TABLE 5-3: READ AFTER READ TIMING RULES

After reading... wait for this many nanoseconds...


before reading...

EtherCAT Process RAM Read Data FIFO

(ECAT_PRAM_RD_DATA)

50 2 EtherCAT Process RAM Read Command Register

(ECAT_PRAM_RD_CMD)

TABLE 5-2: READ AFTER WRITE TIMING RULES (CONTINUED)

After Writing... wait for this many nanoseconds...


before reading...


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6.0 CLOCKS, RESETS, AND POWER MANAGEMENT

6.1 ClocksThe device provides generation of all system clocks as required by the various sub-modules of the device. The clockingsub-system is comprised of the following:

• Crystal Oscillator• PHY PLL

6.1.1 CRYSTAL OSCILLATORThe device requires a fixed-frequency 25 MHz clock source for use by the internal clock oscillator and PLL. This is typ-ically provided by attaching a 25 MHz crystal to the OSCI and OSCO pins as specified in Section 18.7, "Clock Circuit,"on page 320. Optionally, this clock can be provided by driving the OSCI input pin with a single-ended 25 MHz clocksource. If a single-ended source is selected, the clock input must run continuously for normal device operation. Powersavings modes allow for the oscillator or external clock input to be halted.

The crystal oscillator can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 45.

For system level verification, the crystal oscillator output can be enabled onto the IRQ pin. See Section 8.2.7, "ClockOutput Test Mode," on page 56.

Power for the crystal oscillator is provided by a dedicated regulator or separate input pin. See Section 4.1.2, "1.2 V Crys-tal Oscillator Regulator," on page 31.

6.1.2 PHY PLLThe PHY module receives the 25 MHz reference clock and, in addition to its internal clock usage, outputs a main systemclock that is used to derive device sub-system clocks.

The PHY PLL can be disabled as describe in Section 6.3.4, "Chip Level Power Management," on page 45. The PHYPLL will be disabled only when requested and if the PHY ports are in a power down mode.

Power for PHY PLL is provided by an external input pin, usually sourced by the device’s 1.2V core regulator. See Section4.0, "Power Connections," on page 29.

Note: Crystal specifications are provided in Table 18-12, “Crystal Specifications,” on page 320.


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6.2 ResetsThe device provides multiple hardware and software reset sources, which allow varying levels of the device to be reset.All resets can be categorized into three reset types as described in the following sections:

• Chip-Level Resets- Power-On Reset (POR)- RST# Pin Reset- EtherCAT System Reset

• Multi-Module Resets- DIGITAL RESET (DIGITAL_RST)

• Single-Module Resets- Port A PHY Reset- Port B PHY Reset- EtherCAT Controller Reset

The device supports the use of configuration straps to allow automatic custom configurations of various device param-eters. These configuration strap values are set upon de-assertion of all chip-level resets and can be used to easily setthe default parameters of the chip at power-on or pin (RST#) reset. Refer to Section 6.3, "Power Management," onpage 43 for detailed information on the usage of these straps.

Table 6-1 summarizes the effect of the various reset sources on the device. Refer to the following sections for detailedinformation on each of these reset types.

TABLE 6-1: RESET SOURCES AND AFFECTED DEVICE FUNCTIONALITY

Module/Functionality POR

RST#Pin

EtherCATSystem Reset

DigitalReset

EtherCATModule Reset

25 MHz Oscillator (1)Voltage Regulators (2)EtherCAT Core X X X X XPHY A X X XPHY B X X XPHY Common (3) Voltage Supervision (3) PLL (3)SPI/SQI Slave X X X XHost Bus Interface X X X XPower Management X X X XGeneral Purpose Timer X X X XFree Running Counter X X X XSystem CSR X X X XConfig. Straps Latched YES YES YES NO(4)EEPROM Loader Run YES YES YES YES YESTristate Output Pins(5) YES YES YESRST# Pin Driven Low YES YESNote 1: POR is performed by the XTAL voltage regulator, not at the system level

2: POR is performed internal to the voltage regulators3: POR is performed internal to the PHY4: Strap inputs are not re-latched5: Only those output pins that are used for straps


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6.2.1 CHIP-LEVEL RESETSA chip-level reset event activates all internal resets, effectively resetting the entire device. A chip-level reset is initiatedby assertion of any of the following input events:

• Power-On Reset (POR)• RST# Pin Reset• EtherCAT System Reset

Chip-level reset/configuration completion can be determined by first polling the Byte Order Test Register (BYTE_TEST).The returned data will be invalid until the Host interface resets are complete. Once the returned data is the correct byteordering value, the Host interface resets have completed.

The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configura-tion Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bitindicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG),Power Management Control Register (PMT_C-TRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internalresources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READYbit is set.

A chip-level reset involves tuning of the variable output level pads, latching of configuration straps and generation of themaster reset.

CONFIGURATION STRAPS LATCHINGDuring POR, EtherCAT reset or RST# pin reset, the latches for the straps are open. Following the release of POR, Eth-erCAT reset or RST# pin reset, the latches for the straps are closed.

VARIABLE LEVEL I/O PAD TUNINGFollowing the release of the EtherCAT, POR or RST# pin resets, a 1 uS pulse (active low), is sent into the VO tuningcircuit. 2 uS later, the output pins are enabled. The 2 uS delay allows time for the variable output level pins to tune beforeenabling the outputs and also provides input hold time for strap pins that are shared with output pins.

MASTER RESET AND CLOCK GENERATION RESETFollowing the enabling of the output pins, the reset is synchronized to the main system clock to become the masterreset. Master reset is used to generate the local resets and to reset the clocks generation.

6.2.1.1 Power-On Reset (POR)A power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied tothe device. This event resets all circuitry within the device. Configuration straps are latched and EEPROM loading isperformed as a result of this reset. The POR is used to trigger the tuning of the Variable Level I/O Pads as well as achip-level reset.

The POR can also used as a system level reset. RST# becomes an open-drain output and is asserted for the POR time.Its purpose is to perform a complete reset of the EtherCAT slave and/or to hold an external PHY in reset while the Eth-erCAT core is in reset. As an open-drain output, RST is intended to be wired OR’d into the system reset.

Following valid voltage levels, a POR reset typically takes approximately 21 ms.

6.2.1.2 RST# Pin ResetDriving the RST# input pin low initiates a chip-level reset. This event resets all circuitry within the device. Use of thisreset input is optional, but when used, it must be driven for the period of time specified in Section 18.6.3, "Reset andConfiguration Strap Timing," on page 317. Configuration straps are latched, and EEPROM loading is performed as aresult of this reset.

Note: The Ethernet PHY should be connected to the RST# pin so that the PHY is held in reset until the EtherCATSlave is ready. Otherwise, the far end Link Partner would detect valid link signals from the PHY and would“open” its port assuming that the local EtherCAT Slave was ready.

The RST# pin is not driven until all voltages are operational. External, system level solutions are necessaryif the system needs to be held in reset during power ramp-up.


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A RST# pin reset typically takes approximately 760 s.

Please refer to Table 3-13, “Miscellaneous Pin Descriptions,” on page 27 for a description of the RST# pin.

6.2.1.3 EtherCAT System ResetAn EtherCAT system reset, initiated by a special sequence of three independent and consecutive frames/commands,is functionally identical to a RST# pin reset, except that during an EtherCAT system reset, the RST# pin becomes anopen-drain output and is asserted for the minimum required time of 80 ms.

The RST# is an open-drain output intended to be wired OR’d into the system reset.

6.2.2 BLOCK-LEVEL RESETSThe block level resets contain an assortment of reset register bit inputs and generate resets for the various blocks. Blocklevel resets can affect one or multiple modules.

6.2.2.1 Multi-Module ResetsMulti-module resets activate multiple internal resets, but do not reset the entire chip. Configuration straps are not latchedupon multi-module resets. A multi-module reset is initiated by assertion of the following:

• DIGITAL RESET (DIGITAL_RST)

Multi-module reset/configuration completion can be determined by first polling the Byte Order Test Register(BYTE_TEST). The returned data will be invalid until the Host interface resets are complete. Once the returned data isthe correct byte ordering value, the Host interface resets have completed.

The completion of the entire chip-level reset must be determined by polling the READY bit of the Hardware Configura-tion Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set. When set, the READY bitindicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG),Power Management Control Register (PMT_C-TRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internalresources should not be done by S/W while the READY bit is cleared. Writes to any address are invalid until the READYbit is set.

DIGITAL RESET (DIGITAL_RST)A digital reset is performed by setting the DIGITAL_RST bit of the Reset Control Register (RESET_CTL). A digital resetwill reset all device sub-modules except the Ethernet PHYs. EEPROM loading is performed following this reset. Con-figuration straps are not latched as a result of a digital reset.

A digital reset typically takes approximately 760 s.

6.2.2.2 Single-Module ResetsA single-module reset will reset only the specified module. Single-module resets do not latch the configuration straps.A single-module reset is initiated by assertion of the following:

• Port A PHY Reset• Port B PHY Reset• EtherCAT Controller Reset

Note: The RST# pin is pulled-high internally. If unused, this signal can be left unconnected. Do not rely on internalpull-up resistors to drive signals external to the device.

Note: The purpose of connecting the RST# pin into the system reset is to perform a complete reset of the Ether-CAT slave. The EtherCAT master issues this reset in rare and extreme cases when the local microcontrol-ler is seriously halted and can not be otherwise informed to reinitialize.

Note: The digital reset does not reset register bits designated as NASR.


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Port A PHY ResetA Port A PHY reset is performed by setting the PHY_A_RST bit of the Reset Control Register (RESET_CTL) or the SoftReset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port A PHY reset,the PHY_A_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by thisreset.

Port A PHY reset completion can be determined by polling the PHY_A_RST bit in the Reset Control Register(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.Under normal conditions, the PHY_A_RST and Soft Reset bit will clear approximately 102 uS after the Port A PHY resetoccurrence.

In addition to the methods above, the Port A PHY is automatically reset after returning from a PHY power-down mode.This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer toSection 11.2.8, "PHY Power-Down Modes," on page 131 for additional information.

Refer to Section 11.2.10, "Resets," on page 135 for additional information on Port A PHY resets.

If Port A PHY is in 100BASE-FX mode, it is reset when the Enhanced link detection function detects errors on port 0 (2port mode or 3 port downstream mode) or on port 2 (3 port upstream mode).

Port B PHY ResetA Port B PHY reset is performed by setting the PHY_B_RST bit of the Reset Control Register (RESET_CTL) or the SoftReset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port B PHY reset,the PHY_B_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by thisreset.

Port B PHY reset completion can be determined by polling the PHY_B_RST bit in the Reset Control Register(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.Under normal conditions, the PHY_B_RST and Soft Reset bit will clear approximately 102 us after the Port B PHY resetoccurrence.

In addition to the methods above, the Port B PHY is automatically reset after returning from a PHY power-down mode.This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer toSection 11.2.8, "PHY Power-Down Modes," on page 131 for additional information.

Refer to Section 11.2.10, "Resets," on page 135 for additional information on Port B PHY resets.

If Port B PHY is in 100BASE-FX mode, it is reset when the Enhanced link detection function detects errors on port 1.

EtherCAT Controller ResetA compete device and system reset can be initiated by either the EtherCAT master or by the local host by writing thevalue sequence of 0x52 (‘R’), 0x45 (‘E’) and 0x53 (‘S’) into the ESC Reset ECAT Register (for the master) or the ESCReset PDI Register (for the local host). This will trigger the reset described in Section 6.2.1.3, "EtherCAT System Reset".A reset of just the EtherCAT Controller may be performed by setti

2/3-port ethercat® slave controller with integrated ... · pd 50 µa (typical) internal pull-down....

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