2.5d/3d ic packaging technologies2 . © 2017 packaging technology electronic megatrends : 2021...

1 . © 2017 Packaging Technology

Missed some

GND tracesManually add

these traces

2.5D/3D IC Packaging Technologies -

Design and Analysis challenges

John RowlandSVP, Unisoc Spreadtrum & RDA Technologies

2018-10-17


Electronic Megatrends : 2021 Market Values

Reference : IMAPS DPC 2018 : will AI be the real opportunity for 3D and 2.5D integration ?


6M

5M

2M

1M

-

Wate

r sta

rt in m

illio

ns

4M

3M

2016 2017 2018 2019 2020 2021 2022

High-end

applications

Middle-end

applications

Low-end

applications

Reference -

Forecasts 3D TSV and 2.5D - 2016-2022 by 12" wafer start

Wafer start per year(12" eq) will almost reach 5 million in 2022


• High-Bandwidth

• High Performance Computing

• Edge computing

• Deep learning or Deep Neural

Networks

Data Center Entertainment Gaming

AI and Machine Learning

Marketing Motivation

边缘计算正在改变整个物联网(IoT)场景


Where 2.5D/3D interconnections Growth is Coming From ?

SiP Drivers:

Higher performance,

Lower cost, Shorter design time

Lower power consumption

Higher performance

Partitioning by technology node

Heterogeneous Integration

Lower System Level Cost


MEMS and SENSORS in Mobile Devices

Security

Sound

3D Imaging

Inside Mobile Phone: 3 Sensors in 2007, 20 Sensors in 2021

70% Reduction in PKG Size

enabled by 3D TSV and WLP


High Performance Market and ApplicationsWhere 3D stacked components make the point

ICT &

Networking

HPC for Data

Analytics

Consumer

Computing(Gaming +AR/VR)

Aerospace

and defense

Automotive

computing

Medical

computing

TSV Stacked

memory√ √ √ √

Silicon

Interposer√ √ √ √ √ √

3D System

on Chip *√ √

Silicon

photonics√ √ √ √

3D Stacked IC find their place in performance demanding applications

* 3D System on Chip consists in logic-on-logic and memory-on-logic stacked 3D IC


Why AI & Deep Learning Take place Now ?

Deep learning has gained more interests for the last 5 years


Deep Learning Hardware• Hardware for TRAINING require large bandwidth, 3D-based products offer solutions

• INFERENCE require less bandwidth but low latency. Interposer could come as a solution

because of its modularity and its capacity to integrate more than on chip.

• Main player offer clear different product lines as solutions for both steps

TRAINING INFERENCE

3D and 2.5D packages have enabled performance

hardware for deep learning applications


High Bandwidth Memory - HBM2

Wide I/O 2 - WideIO2

Hybrid Memory Cube- HMC Gen2

8GB HBM2 Pkg: 40,000 TSVs

Single Die: 5000+ TSVs

BW: 256GB/s 1,024 I/O

High-Bandwidth Memory Type


HIGH-BANDWIDTH MemoryHBMx is becoming a standard


3D NAND Roadmap (NVM)


AMD GPU VEGA Product -2.5D/3D Package with HBM2

• AMD GPU Vera Package Supply Chain

• GLOBALFOUNDRIES GPU and interposer

• ASE Assembly

• Samsung HBM2

• IBIDEN laminate subtrate

TSV inside HBM and Silicon Interposer


CPU/GPUHBM2 DRAM HBM2 DRAM

CPU/GPU

Silicon Interposer - with TSV

with TSV


Challenges from Alternative Technologies

Alternative TSV-Less Technology

TSV-less interposer and advanced high density substrates

OSATs and IDMs are looking for alternative low-cost technologies

High-Density Fan-out and low-cost demand to emerge


HBM2 HBM2 CPU/GPU

Embedded Multi-Die Interconnect Bridge(EMIB)- TSVless

TSVless


EMIB Vs Silicon Interposer

A True Packaging Breakthrough

Industry Standard 2.5D EMIB

ⅹ Normal package yield ranges √

ⅹ No additional process costs from TSVs √

ⅹ Simple to Design √

Substrate

Silicon Interposer

Substrate

../EMIB.mp4

../EMIB.mp4


2.5D/3D IC Power, Signal and Thermal Integrity

Challenges comes from Chip-package and PCB

/Board interconnection extraction and simulation

Off-chip decap placement alternatives to

suppress mid-frequency noise


Si-Interposer

Typical Physical Dimension and Material Property

the interposer uses one-sided 3 layers of redistribution layer (RDL) and through-silicon via (TSV).


Interconnection Channel Modeling

HBM2

CPU/GPU/NPU

FPGA

1) Modeling connectivity of complicated 3DIC structure

2) Parasitic modeling of packages (Interposer), board PCB

3) Power, Signal and thermal modeling of interconnects of stacked dies

4) Noise source modeling for power, signal and thermal

5) Interface (Bump, Ball and TSV) modeling

The channel performance for the

parallel interface (HBM channel)

depends the interposer

interconnect

Si interconnect loss and time constant

Impact of slotted ground considered

Silicon substrate loss included for M1 microstrip


Chip-Interposer-Package-Board Hierarchical PDN Model

Power Distribution Impedance


Eye diagrams of the HBM channel (a) without SSO noise, (b) with SSO noise (c) with SSO and interposer

decaps and (d) with SSO and package decaps

Eye Diagrams of Parallel Bus -HBM2 @2Gbps


The channel performance for the parallel interface

depends the interposer channel interconnect

crosstalk

The Frequency-Domain Responses of the HBM Interposer Channels

FEXT NEXTIL


Summary

3D integration is taking place for real, 2018 the

golden year as volume production increases

• 3D TSV and 2.5 packaging platforms are gaining

interests for high-performance applications

Artificial intelligence using deep learning

algorythms require consequent number of

memory cubes

High Bandwith Memory (HBM) is becoming a

standard

• Shortage of HBM2 in 2017

• Increase of production capacity in 2018

• HBM 3rd generation expected 2019 -2020

Emergence of alternative packaging technologies

• TSV less platforms under development but none

in volume production

2.5d/3d ic packaging technologies2 . © 2017 packaging technology electronic megatrends : 2021...

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