2720 ieee journal of solid-state circuits, vol....

2720 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

A 0.5-GHz to 2.5-GHz PLL With Fully DifferentialSupply Regulated Tuning

Merrick Brownlee, Student Member, IEEE, Pavan Kumar Hanumolu, Student Member, IEEE,Kartikeya Mayaram, Fellow, IEEE, and Un-Ku Moon, Senior Member, IEEE

Abstract—This paper describes a wide-range clock generationphase-locked loop (PLL) incorporating several features that makeit suitable for integration in highly scaled processes. A fully dif-ferential supply regulated tuning scheme is used to combat powersupply noise. The charge pump uses a resistor rather than an activecurrent source to define the pumping current in order to reducethe charge pump flicker noise. Fabricated in a 0.18- m CMOSprocess, the PLL occupies 0.15 mm2 die area and achieves a fre-quency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, thepower consumption is 14 mA from a 1.8-V supply while the jitteris 2.36 ps rms.

Index Terms—Phase-locked loop, power supply noise, supplyregulation, charge pump, flicker noise, voltage-controlledoscillator.

I. INTRODUCTION

AS INTEGRATED circuit fabrication technologiesprogress, reduced minimum feature size and supply

voltages improve the speed, power consumption, and die areaconsumption of digital circuitry. This trend toward higherlevels of integration, however, complicates the design of thesupportive analog circuitry by increasing device noise, in-creasing mismatch, and decreasing supply voltage. One ofthese important analog circuits is the phase-locked loop (PLL)that is used to generate and distribute clocks in all high-perfor-mance digital systems.

This paper describes a PLL design well suited to highly inte-grated digital environments [1]. The rest of this introduction isdivided into two parts: the first discusses the PLL design issuesspecific to such highly integrated environments while the secondreviews PLL noise issues. The issues raised provide the motiva-tion for the two unique ideas used in this work which are de-scribed in Sections II and III: fully differential supply regulatedtuning and a low flicker noise charge pump, respectively. Thephase-frequency detector (PFD) and divider designs are brieflycovered in Section IV. Finally, measurement results are shownin Section V before conclusions are drawn in Section VI.

A. Integration Issues

A typical application where a PLL would face the aforemen-tioned integration problems is shown in Fig. 1. High levels of

Manuscript received April 13, 2006; revised July 20, 2006. This work wassupported by the Semiconductor Research Corporation (SRC) under Contract2003-HJ-1076, and partly by Intel.

The authors are with the School of Electrical Engineering and Com-puter Science, Oregon State University, Corvallis, OR 97331 USA (e-mail:[email protected]).

Digital Object Identifier 10.1109/JSSC.2006.884194

Fig. 1. Typical highly integrated clock generation PLL application.

integration lead to large digital systems that must be partitionedinto many smaller subsystems in order for the design to be man-ageable and efficient. Each subsystem operates at a differentfrequency as speed requirements will vary and, therefore, eachrequires its own clock generation PLL. Rather than design aseparate PLL optimized for each frequency, a single wide-rangedesign is desirable.

Having many instances of the PLL integrated on the samedie means that die area consumption is critical. This die areaconstraint and the need for a wide tuning range mandates theuse of a ring voltage-controlled oscillator (VCO). Integratingmany PLLs also magnifies the importance of power consump-tion. Since the PLL will cover a wide range of frequencies, it isimportant that the design be power efficient over the entire fre-quency range.

Another major consequence of the highly integrated envi-ronment is that the digital circuitry will induce switching noiseon the PLL supply. Scaling trends allow higher levels of digitalfunctionality, which increases these switching currents. At thesame time, the supply voltage is shrinking because of powerconsiderations. Therefore, supply noise is quickly becoming alarger fraction of the total supply voltage and any reasonabledeep-submicron PLL design must have good supply noiseimmunity.

B. PLL Noise Issues

The most critical performance specification for PLL clockgenerators is jitter. Any uncertainty in the clock provided by thePLL subtracts from the timing margins for the digital logic andultimately limits the speed of the digital system. An importantstep in clock generation design is to identify the PLL blocks thatare the major contributors to jitter.

One of these noise critical blocks is the VCO. In fact, ringVCOs are known to be particularly noisy. It can be shown thatVCO jitter due to intrinsic noise sources (thermal and flicker)is reduced when the delay cells are designed for high swingand fast switching [2]. Such delay cells, however, operate by

0018-9200/$20.00 © 2006 IEEE

BROWNLEE et al.: A 0.5-GHZ TO 2.5-GHZ PLL WITH FULLY DIFFERENTIAL SUPPLY REGULATED TUNING 2721

Fig. 2. (a) PLL block diagram. (b) Charge pump and VCO noise transfer functions.

charging a load capacitance through a low resistance switchconnected to either ground on the falling edge or on therising edge (e.g., an inverter). The problem with these full-swingdelay cells is, therefore, that they are very sensitive to the supplyvoltage.

The charge pump is the second major PLL noise contributor.Using the block diagram shown in Fig. 2(a), transfer functionsfrom the charge pump and VCO to the PLL output can be cal-culated, revealing the relevant noise band for each. The chargepump transfer function is found to be low-pass while the VCOtransfer function is high-pass with an equal bandwidth [3], [4][see Fig. 2(b)]. This exposes a bandwidth tradeoff that restrictsthe designer. A low bandwidth reduces low-frequency chargepump noise contribution at the cost of increasing the high-fre-quency VCO noise contribution, whereas a high bandwidth re-duces the VCO noise contribution while increasing the chargepump noise contribution.

For our application, it was determined that the VCO noisewas a more inherent noise source and a wide bandwidth waschosen to suppress it. Therefore, the reduction of low-frequencycharge pump noise became essential. In deep-submicron pro-cesses, flicker noise is dominant at low frequencies. In fact, theflicker noise corner was found to be comparable to the widePLL bandwidth, so that charge pump flicker noise was largelyunsuppressed while thermal noise was mostly suppressed. Thecharge pump described in Section III circumvents this problemby using a unique architecture that drastically reduces the chargepump flicker noise corner.

II. FULLY DIFFERENTIAL SUPPLY REGULATED TUNING

Single-ended supply regulated tuning is an existing technique[5], [6] that makes use of the fact that the oscillation frequencyof full-swing VCOs is proportional to the supply voltage. There-fore, the supply voltage of the delay cells can be used as thecontrol voltage as shown in Fig. 3. This isolates the delay cellsfrom the positive supply. The buffer in Fig. 3 is needed to keepthe VCO from loading the loop filter and is essentially a supplyregulator.

This regulation loop is able to isolate the positive supply ofthe delay cells from noise on the positive external supply, buthas no effect on the ground noise. Therefore, a decoupling ca-pacitor is added between the positive supply and ground to keepthe difference constant in the presence of ground noise. For afinite decoupling capacitor, however, the translation of groundnoise to common-mode noise is imperfect and some amount

Fig. 3. Supply regulated tuning concept.

Fig. 4. Ground noise to differential supply noise gain as a function of decou-pling capacitance.

of ground noise will appear as differential supply noise. Fig. 4shows the simulated ground noise to differential supply noisegain as a function of decoupling capacitance for 10-MHz and100-MHz sinusoidal ground noise. As expected, for small ca-pacitance values, the capacitor couples the positive supply toground very poorly and almost all of the ground noise appearsas differential supply noise . As the capacitor size in-creases, the coupling improves and approaches perfect coupling

for very large capacitance. It is also expected thatfaster noise components will be better coupled, so the 100-MHznoise is the best case.

If we use the liberal estimate of ground noise as a singlehigh-frequency (100-MHz), 50-mV tone, a 120-nF capacitor isrequired to reduce this noise to 10 mV. A MOS capacitor of thissize would be approximately 100 times larger than the entire ac-tive die area of the chip described in this paper.


Fig. 5. Fully differential supply regulated tuning.

Fig. 6. Fully differential buffer.

In this work, rather than regulating the positive supply andrelying on a large capacitor to couple the positive and nega-tive supplies, both supplies are included in the regulation loop.This can be achieved by using the difference between positiveand negative delay cell supplies as a differential control voltageas shown in Fig. 5. A much smaller decoupling capacitor isincluded to reduce noise not attenuated by the imperfect reg-ulation loop and for stability of the regulation loop (see theAppendix for details). Fully differential tuning also accommo-dates a fully differential charge pump and loop filter which iso-lates those blocks from supply noise. Another benefit is thatthe need for a low-to-high-swing converter is eliminated sincethe common-mode feedback of the fully differential buffer willforce the common-mode of the oscillator output to midrail. Al-though not available for this work, a triple-well process shouldbe used when possible so that the bulks of the nMOS devices inthe delay cells can also be isolated from the negative supply.

The fully differential buffer needed for fully differentialsupply regulated tuning is not a simple extension of thesingle-ended case, as that would lead to an operational ampli-fier (opamp) with both outputs shorted to both inputs. Instead,the two-input opamp in unity gain configuration shown inFig. 6 can be used. The problem with opamps in unity gainconfiguration is that the input common-mode range limits theoutput swing which, in this case, limits the VCO tuning range.Noticing, however, that the input pair labeled “A” in Fig. 6 willbe forced by the loop to be approximately equal to the positivesupply voltage of the delay cells, which is always above midrail,it is possible to use an nMOS input pair to achieve a large inputcommon-mode range. Similarly, pair “B” can achieve a largeinput common-mode range by using a pMOS input pair. Theresulting opamp is shown in Fig. 7.

The amount of current consumed by the ring VCO is propor-tional to the oscillation frequency and inversely proportional tothe jitter. Therefore, a high-speed low-jitter VCO requires theopamp to provide a prohibitively large current. A solution is toadd transistors between the external supply ( and ground)and the internal supply ( and ), so that current is drawnfrom the external supply rather than the output of the opamp.Another benefit of adding these transistors is that the output

Fig. 7. Two-input-pair fully differential buffer opamp with large inputcommon-mode range.

Fig. 8. Final VCO configuration.

swing requirements of the opamp are relaxed. The final VCOconfiguration incorporating this idea is shown in Fig. 8. A min-imum number (3) of basic inverter delay cells are used to min-imize parasitics and noise-contributing transistors. The single-ended nature of the inverter delay cells is tolerated because ofsupply regulation. As shown in Fig. 8, poly resistors are used tosense the common-mode of the delay cell supplies and a simplefeedback loop forces this common-mode voltage to midrail.

There are several considerations in the design of the supplyregulation loop, including stability, bandwidth, dropout, andpeaking in the transfer function from the external to internalsupply. The Appendix gives detailed information on this designprocess.

As mentioned earlier, low-power operation that scales wellwith frequency is an important consideration in wide-range PLLdesign [7]. Power consumption in full-swing ring VCOs can beexpressed as

(1)

where is the power, is the peak current drawn by thedelay cell during switching, is the supply voltage, andis the frequency of oscillation. For traditional tuning methodswhere the VCO output swing is constant over the tuning range,

and are also constant over the tuning range, and


Fig. 9. Power savings of quadratic scaling compared to linear scaling.

Fig. 10. Traditional charge pump.

power scales linearly with the oscillation frequency. Supply reg-ulated tuning, on the other hand, scales the internal supply of thedelay cells with frequency, which means that scales withfrequency. Therefore, the power in the supply regulated tuningcase is proportional to and the scaling with frequency isquadratic. Fig. 9 illustrates how quadratic scaling gives signifi-cant power savings for the lower end of the VCO tuning range.

III. LOW FLICKER NOISE CHARGE PUMP

As explained earlier, charge pump flicker noise is a problemin deep-submicron PLL designs. A potential solution to thisproblem is to find a way to use a flicker-noise-free passive de-vice to define the charge pump current rather than an active de-vice with large flicker noise. Before explaining how that canbe done, it is instructive to review the operation of a traditionalcharge pump. In a traditional charge pump (Fig. 10), the UPand DN pulses from the PFD drive switches connected in se-ries with transistor current sources which convert the voltagepulses to current pulses of equal width. The down current pulseis subtracted from the up current pulse at the output node andthe resulting signal drives the loop filter.

The proposed charge pump is shown in Fig. 11. Here, thevoltage pulses are converted to current pulses by the resistorsbetween the UP and DN inputs and the opamp inputs [8]. In-stead of directly subtracting the current pulses before drivingthe loop filter, the difference information is contained in a dif-ferential signal which drives a differential loop filter. As desired,the charge pump current is now defined by a flicker-noise-freeresistor rather than a transistor.

The opamp needed in the proposed charge pump does con-tribute flicker noise as modeled by the noise source at the

Fig. 11. Proposed charge pump.

Fig. 12. Comparison of current noise spectra of traditional and proposed chargepumps.

output of the opamp shown in Fig. 11. The control-voltage-to-output transfer function of the PLL is bandpass, however, so theopamp flicker noise contribution is significantly reduced.

The simulated charge pump current noise spectrum is plottedin Fig. 12. For the sake of comparison, the current noise spec-trum of a traditional charge pump with equal pumping current isalso shown. It is apparent that the flicker noise corner is reducedin the proposed design. These noise spectra were obtained fromperiodic noise simulations which take into account the fact thatthe traditional charge pump current noise is passed only duringthe fraction of the reference period when the PFD reset pulse ishigh.

IV. PFD AND DIVIDER

The PFD is a simple digital state machine. When driving atraditional charge pump, it is important that the reset pulses arewide enough to turn on the switches in the charge pump in orderto avoid a dead zone. A wider reset pulse, however, exaggeratesthe ripple on the control voltage caused by mismatch betweenthe UP and DN current sources. The proposed charge pump re-duces this ripple in two ways. First, the mismatch is less because


Fig. 13. Narrow reset pulse phase-frequency detector.

Fig. 14. Die photograph.

the two resistors have better matching than a pMOS currentsource has to an nMOS current source. Second, the reset pulsewidth can be minimized since there are no switches that mustbe turned on. The PFD described in [9] and shown in Fig. 13was used in this work. This PFD was designed for high-speedoperation where narrow reset pulses are required.

The divider is a cascade of divide-by-two stages. The firststage must operate at a relatively high frequency to cover thehigh end of the VCO tuning range. In order to meet the speedrequirements, the divide-by-two stage was implemented usingtruly single phase clock (TSPC) flip-flops which are describedin [10].

V. MEASUREMENT RESULTS

The PLL was fabricated in a 0.18- m CMOS technology andoccupies 0.15 mm . Fig. 14 shows a die photograph. The mea-sured jitter histogram1 showing 2.36 ps rms jitter at an oscil-lation frequency of 2.4 GHz is depicted in Fig. 15. Shown inFig. 16 is the measured jitter over the frequency range. As ex-pected, the jitter increases linearly with the period, maintaininga constant fraction of the period.

In order to quantify the dynamic power supply noise sensi-tivity, the experiment depicted in Fig. 17 was performed where

1The histogram shows absolute jitter with respect to the PLL reference clock[11].

Fig. 15. Measured jitter histogram at 2.4 GHz.

Fig. 16. Measured jitter as a function of oscillation period (left axis) and as apercentage of oscillation period (right axis).

Fig. 17. Dynamic supply noise sensitivity measurement.

a 50-mV tone was added to the supply and the jitter degrada-tion was measured. The amplitude of the tone was measuredat the supply pin to accurately obtain the signal level enteringthe device under test. As described in the Appendix, the supplyregulation loop will cause the supply sensitivity to be a low-passshape. Fig. 18 shows the measured jitter for 1-MHz, 10-MHz,and 1-GHz supply tones, which demonstrates the ability of theloop to suppress high-frequency supply noise. For the 1-MHzcase, the rms jitter is degraded to 14.8 ps. At 10 MHz, the rmsjitter has reduced slightly to 9.92 ps, while at 1 GHz, the rmsjitter is only 3.11 ps, which is very close to the jitter measuredwith a clean supply. The performance of the PLL is summarizedin Table I.


Fig. 18. Measured jitter histogram for (a) 1-MHz, (b) 10-MHz, and (c) 1-GHzsupply tone.

The quadratic scaling expected by the analysis in Section IIwas verified by measuring the VCO power as a function of fre-quency. The measurement, shown in Fig. 19, does indeed showquadratic scaling.

VI. CONCLUSION

By addressing integration related issues, we have demon-strated a PLL well-suited for clock generation in modern digitalintegrated circuits. The wide range and small die area of the ringVCO used in the PLL enable the design to be reused for eachof the many digital subsystems operating at different speedsthat comprise a large digital system. The supply noise sensitive

TABLE IPERFORMANCE SUMMARY

Fig. 19. Measured VCO power as a function of frequency showing quadraticscaling.

delay cells used in the ring VCO are tolerated in the presenceof large digital switching noise through the use of fully differ-ential supply regulated tuning. A wide bandwidth is employedto reduce the inherently large ring VCO jitter. Since the widebandwidth exacerbates the charge pump flicker noise problem,a novel low flicker noise charge pump architecture was devel-oped. With many instances of the PLL on the same die, powerconsumption is important. The design was shown to be powerefficient over the entire frequency range.

APPENDIX

SUPPLY REGULATED TUNING DESIGN PROCESS

Designing a supply regulated tuning loop requires careful bal-ancing of several considerations. Referring to Fig. 20, whichshows the single-ended case for the sake of simplicity, we canlist the following considerations.

• Since the attenuation of supply noise is characterized bythe transfer function , we want high DC at-tenuation, a low bandwidth for better high-frequency at-tenuation (since the transfer function is low-pass), and nopeaking.

• Since the transfer function is in the PLL signalpath, it must have sufficiently high bandwidth so that itdoes not compromise the PLL loop stability.


Fig. 20. Simplified supply regulated tuning for analysis.

• The supply regulation loop must also be stable, so careshould be taken to ensure sufficient phase margin for theregulator loop transfer function .

• Since the tuning range of the VCO is constrained by theswing at , the dropout of the regulator should be low.

• The above considerations must be met with minimal powerand die area overhead.

This Appendix is intended to yield insight into the processof designing a supply regulated tuning loop that successfullybalances these considerations.

As derived in [12], the transfer function from the externalsupply to the internal supply can be written as

(2)

where is the output impedance of,

which is the DC gain of the pMOS device, is the DC gainof the amplifier, is the pole at , and

is the amplifier pole.Rewriting (2) using control system notation, we get

(3)

From (2) and (3),

(4)

(5)

Peaking occurs if the zero frequency is lower than the fre-quency where the transfer function rolls off due to the two poles.Therefore, care must be taken to ensure that is greater than

.To that end, we define a parameter so that

(6)

From (4) and (6), we can write in terms of as

(7)

which shows that must be the dominant pole.It can be shown that for , the two poles are complex.

From (5) and (7), we see that

(8)

Fig. 21. Typical open- and closed-loop gain response.

In order to ensure that there is no peaking due to the complexpoles, we will restrict , which means .

When , there are two real poles. As increases, thepoles split and the higher pole is approximately . Therefore,the higher pole and the zero cancel and the transfer function issingle-pole-like. The bandwidth of the transfer function is setby the lower real pole, which decreases with .

Behavioral PLL simulations reveal that the bandwidth ofmust be about 5–10 times larger than the PLL

bandwidth to ensure that the regulator does not compromise thestability of the PLL. can be written in terms of theregulator loop gain

(9)

where

(10)

Fig. 21 shows a plot of and . Since the feed-back factor in this case is 1, the bandwidth of , , issimply the unity-gain bandwidth of , so

(11)

From (7) and (11), we see that

(12)

Also shown in Fig. 21 is the loop-gain phase responsefor phase margin calculation. The phase margin

can be written as

(13)

Assuming a large gain , the second term is approximately90 and substituting (12) into the third term simplifies (13) to

(14)


Fig. 22. � ; ! , and ! as a function of x.

From (2), the DC gain of is . There-fore, to increase the DC supply noise attenuation, we want alarge and a large DC gain . Rearranging (11), we get

(15)

which shows that increasing decreases , which increasesthe size of the capacitor C. Thus, there exists an optimum choiceof that balances DC supply noise attenuation with capacitorarea. Notice from (15) that the choice of a wide PLL bandwidth,and thus a large , eases this tradeoff somewhat.

Having chosen a value for , the only remaining decision isthe value of parameter , from which we can derive , , andthe 3-dB bandwidth of , , which determineshow much high-frequency supply noise is filtered by the regu-lation loop. Shown in Fig. 22 is a plot of these three parametersas a function of .

In order to choose properly, we must consider the value ofthat is optimum for each parameter individually. The phase

margin approaches its maximum value of 90 as increases. Alarge value of is also desired to yield a small which isdesired to filter supply noise. On the other hand, for low dropoutthe pMOS device must have a small overdrive voltage whichmandates a large aspect ratio. We have also seen that this deviceshould be long to maximize for DC supply noise attenuation.Having a large decreases because of the large gatecapacitance. Therefore, a small is desired to enable a small

.The dashed lines in Fig. 22 show a reasonable compromise

of which leads to , , and.

ACKNOWLEDGMENT

The authors thank National Semiconductor for providing ICfabrication, and particularly O. Norman for his sponsorship.

REFERENCES

[1] M. Brownlee, P. Hanumolu, K. Mayaram, and U. Moon, “A 0.5 to 2.5GHz PLL with fully differential supply regulated tuning,” IEEE ISSCCDig. Tech. Papers, pp. 588–589, Feb. 2006.

[2] A. Hajimiri and T. Lee, The Design of Low Noise Oscillators. Boston,MA: Kluwer Academic, 1999.

[3] P. Hanumolu, M. Brownlee, K. Mayaram, and U. Moon, “Analysis ofcharge-pump phase-locked loops,” IEEE Trans. Circuits Syst. I, Reg.Papers, vol. 51, no. 9, pp. 1665–1674, Sep. 2004.

[4] M. Perrott, M. Trott, and C. Sodini, “A modeling approach for ��fractional-N frequency synthesizers allowing straightforward noiseanalysis,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028–1038,Aug. 2002.

[5] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz, “Adaptivebandwidth DLLs and PLLs using regulated supply CMOS buffers,” inSymp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 124–127.

[6] V. von Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, “A 320 MHz,1.5 [email protected] V CMOS PLL for microprocessor clock generation,”IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1715–1722, Nov. 1996.

[7] J. Kim and M. Horowitz, “Adaptive supply serial links with sub-1-Voperation and per-pin clock recovery,” IEEE J. Solid-State Circuits, vol.37, no. 11, pp. 1403–1413, Nov. 2002.

[8] F. Gardner, Phaselock Techniques. New York: Wiley, 2005.[9] M. Mansuri, D. Liu, and C. Yang, “Fast frequency acquisition

phase-frequency detectors for Gsamples/s phase-locked loops,” IEEEJ. Solid-State Circuits, vol. 37, no. 10, pp. 138–452, Oct. 2002.

[10] J. Yuan and C. Svensson, “High speed CMOS circuit technique,” IEEEJ. Solid-State Circuits, vol. 24, no. 2, pp. 62–70, Feb. 1989.

[11] J. McNeill, “Jitter in ring oscillators,” IEEE J. Solid-State Circuits, vol.32, no. 6, pp. 870–879, Jun. 1997.

[12] E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, “Replica com-pensated linear regulators for supply-regulated phase-locked loops,”IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006.

Merrick Brownlee (S’02) received the B.S. degreein applied science from George Fox University, New-berg, OR, in 2001, and the B.S. degree in electricaland computer engineering from Oregon State Uni-versity, Corvallis, in 2002. He is currently workingtoward the Ph.D. degree in electrical engineering atOregon State University.

During the summer of 2004, he was with Na-tional Semiconductor Corporation, Ft. Collins, CO,working on data converters and during the summerof 2005, he was with Intel Corporation, Hillsboro,

OR, working on high-speed I/O circuits. His current research interests involvehigh-speed I/O circuit topics including clock generation, clock and datarecovery, and equalization.

Mr. Brownlee received the Analog Devices Outstanding Student DesignerAward in 2004.

Pavan Kumar Hanumolu (S’99) received the B.E.(Hons.) degree in electrical and electronics engi-neering and the M.Sc. (Hons.) degree in mathematicsfrom the Birla Institute of Technology and Science,Pilani, India, in 1998, the M.S. degree in electricaland computer engineering from the WorcesterPolytechnic Institute, Worcester, MA, in 2001, andthe Ph.D. degree in electrical engineering from theOregon State University, Corvallis, in 2006.

From 1998 to 1999, he was a Design Engineer atCypress Semiconductors, Bangalore, India, working

on phase-locked loops for LVDS interfaces. During the summers of 2002 and2003, he was with Intel Circuits Research Labs, Hillsboro, OR, where he in-vestigated clocking and equalization schemes for input/output (I/O) interfaces.Currently, he is an Assistant Professor in the School of Electrical Engineeringand Computer Science, Oregon State University. His research interests includeequalization, clock and data recovery for high-speed I/O interfaces, data con-verters and low-voltage mixed-signal circuit design.


Kartikeya Mayaram (S’82–M’88–SM’99–F’05)received the B.E. (Hons.) degree in electrical en-gineering from the Birla Institute of Technologyand Science, Pilani, India, in 1981, the M.S. degreein electrical engineering from the State Universityof New York, Stony Brook, in 1982 and the Ph.D.degree in electrical engineering from the Universityof California, Berkeley, in 1988.

From 1988 to 1992, he was a Member of Tech-nical Staff in the Semiconductor Process and DesignCenter of Texas Instruments Incorporated, Dallas,

TX. From 1992 to 1996, he was a Member of Technical Staff at Bell Labs,Allentown, PA. He was an Associate Professor in the School of ElectricalEngineering and Computer Science, Washington State University, Pullman,from 1996 to 1999, and in the Electrical and Computer Engineering Departmentat Oregon State University, Corvallis, from 2000 to 2003. Currently, he isa Professor in the School of Electrical Engineering and Computer Science,Oregon State University. His research interests are in the areas of circuitsimulation, device simulation and modeling, simulation and modeling ofsubstrate coupling in mixed-signal ICs, integrated simulation environments formicrosystems, and analog/RF design.

Dr. Mayaram received the National Science Foundation (NSF) CAREERAward in 1997. He has served on the technical program committees of sev-eral conferences and was on the editorial board of IEEE TRANSACTIONS ON

COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS as an As-sociate Editor from 1995 to 2001 and as the Editor-in-Chief from 2002 to 2005.

Un-Ku Moon (S’92–M’94–SM’99) received theB.S. degree from the University of Washington,Seattle, in 1987, the M.Eng. degree from CornellUniversity, Ithaca, NY, in 1989, and the Ph.D. degreefrom the University of Illinois at Urbana-Champaignin 1994, all in electrical engineering.

He has been with the School of Electrical Engi-neering and Computer Science, Oregon State Uni-versity, Corvallis, since 1998, where he is currentlya Professor. Before joining Oregon State University,he was with Bell Laboratories from 1988 to 1989,

and from 1994 to 1998. His technical contributions have been in the area ofanalog and mixed-signal circuits including highly linear and tunable contin-uous-time filters, telecommunication circuits including timing recovery and dataconverters, and ultra-low-voltage analog circuits for CMOS.

Prof. Moon is a recipient of the National Science Foundation CAREERAward, and the Engelbrecht Young Faculty Award from Oregon State Uni-versity College of Engineering. He has served as an Associate Editor of theIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL

SIGNAL PROCESSING. He currently serves as an Associate Editor of the IEEEJOURNAL OF SOLID-STATE CIRCUITS. He currently serves on the TechnicalProgram Committee of the IEEE Custom Integrated Circuits Conference andthe Analog Signal Processing Technical Committee of the IEEE Circuits andSystems Society, and as a member of the IEEE Solid-State Circuits SocietyAdministrative Committee and the IEEE Circuits and Systems Society Boardof Governors.

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