08007 Rev: I Amendment/0ay 1998

A2

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n

nnnn

GTgwssaaP

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B

08007I-1Publication# Issue Date: MA0A14 Address Inputs 262,144

Bit Cell Matrix

X DecoderFINAL

m27C25656 Kilobit (32 K x 8-Bit) CMOS EPROM

ISTINCTIVE CHARACTERISTICSFast access time Speed options as fast as 45 nsLow power consumption 20 A typical CMOS standby currentJEDEC-approved pinoutSingle +5 V power supply10% power supply tolerance standard100% Flashrite programming Typical programming time of 4 seconds

n Latch-up protected to 100 mA from 1 V to VCC + 1 V

n High noise immunityn Versatile features for simple interfacing

Both CMOS and TTL input/output compatibility Two line control functions

n Standard 28-pin DIP, PDIP, and 32-pin PLCC packages

ENERAL DESCRIPTIONhe Am27C256 is a 256-Kbit, ultraviolet erasable pro-rammable read-only memory. It is organized as 32Kords by 8 bits per word, operates from a single +5 Vupply, has a static standby mode, and features fastingle address location programming. Products arevailable in windowed ceramic DIP packages, as wells plastic one time programmable (OTP) PDIP andLCC packages.ata can be typically accessed in less than 55 ns, al-

owing high-performance microprocessors to operateithout any WAIT states. The device offers separateutput Enable (OE#) and Chip Enable (CE#) controls,

thus eliminating bus contention in a multiple bus micro-processor system.AMDs CMOS process technology provides highspeed, low power, and high noise immunity. Typicalpower consumption is only 80 mW in active mode, and100 W in standby mode.All signals are TTL levels, including programming sig-nals. Bit locations may be programmed singly, inblocks, or at random. The device supports AMDsFlashrite programming algorithm (100 s pulses), re-sulting in a typical programming time of 4 seconds.

LOCK DIAGRAM

CE#OE#

VCCVSSVPP

Data Outputs DQ0DQ7

Output Buffers

Y Gating

Y Decoder

Output Enable Chip Enable

and Prog Logic

2P

CT

N12

PA

CD

OV

V

V

NRODUCT SELECTOR GUIDE

ONNECTION DIAGRAMSop View

DIP PLCC

otes:. JEDEC nomenclature is in parenthesis.. Dont use (DU) for PLCC.

IN DESIGNATIONS0A14 = Address InputsE# (E#) = Chip Enable InputQ0DQ7 = Data Input/OutputsE# (G#) = Output Enable InputCC = VCC Supply Voltage

PP = Program Voltage Input

SS = GroundC = No Internal Connection

LOGIC SYMBOL

Family Part Number Am27C256

Speed OptionsVCC = 5.0 V 5% -255

VCC = 5.0 V 10% -45 -55 -70 -90 -120 -150 -200

Max Access Time (ns) 45 55 70 90 120 150 200 250CE# (E#) Access (ns) 45 55 70 90 120 150 200 250OE# (G#) Access (ns) 30 35 40 40 50 50 50 50

345

21

910111213

2322212019

7

8

1817

6

2827

1614

262524

15

A6A5A4A3A2A1A0

DQ0

A7

DQ1DQ2VSS

A8A9A11OE# (G#)A10CE# (E#)DQ7

VCCA14

DQ6

A13

DQ5DQ4DQ3

VPPA12

08007I-2D

Q5

DU

DQ4

DQ3DU

1 31 302345678910111213

17 18 19 20161514

292827262524232221

32A6A5A4A3A2A1A0NC

DQ0

A8A9A11NCOE# (G#)A10CE# (E#)DQ7DQ6

A7 A12

V PP

V CC

A14

A13

DQ1

DQ2 V S

S

08007I-3

15

8

DQ0DQ7

A0A14

CE# (E#)

OE# (G#)

08007I-4Am27C256

OUAbRDERING INFORMATIONV EPROM Products

MD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formedy a combination of the following:

Valid CombinationsValid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.

DEVICE NUMBER/DESCRIPTIONAm27C256256 Kilobit (32 K x 8-Bit) CMOS UV EPROM

AM27C256 -45 D C

OPTIONAL PROCESSINGBlank = Standard ProcessingB = Burn-In

TEMPERATURE RANGEC = Commercial (0C to +70C)I = Industrial (40C to +85C)E = Extended (55C to +125C)

PACKAGE TYPED = 28-Pin Ceramic DIP (CDV028)

SPEED OPTIONSee Product Selector Guide and Valid Combinations

B

Valid Combinations

AM27C256-45DC, DCB, DI, DIB

AM27C256-55

AM27C256-70

DC, DCB, DI, DIB, DE, DEB

AM27C256-90

AM27C256-120

AM27C256-150

AM27C256-200

AM27C256-255VCC = 5.0 V 5%

DC, DCB, DI, DIBAm27C256 3

4OOAbRDERING INFORMATIONTP EPROM Products

MD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formedy a combination of the following:

Valid CombinationsValid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.

DEVICE NUMBER/DESCRIPTIONAm27C256256 Kilobit (32 K x 8-Bit) CMOS OTP EPROM

AM27C256 -55 P C

OPTIONAL PROCESSINGBlank = Standard Processing

TEMPERATURE RANGEC = Commercial (0C to +70C)I = Industrial (40C to +85C)

PACKAGE TYPEP = 28-Pin Plastic DIP (PD 028)J = 32-Pin Square Plastic Leaded Chip Carrier (PL 032)

SPEED OPTIONSee Product Selector Guide and Valid Combinations

Valid Combinations

AM27C256-55 JC, PC

AM27C256-70

JC, PC, JI, PI

AM27C256-90

AM27C256-120

AM27C256-150

AM27C256-200

AM27C256-255Am27C256

FDItsctomom

Nsappmw

DUalc

TVCFpTEsrgmpdpaqoett5

PBi

PPappUNCTIONAL DESCRIPTIONevice Erasure

n order to clear all locations of their programmed con-ents, the device must be exposed to an ultraviolet lightource. A dosage of 15 W seconds/cm2 is required toompletely erase the device. This dosage can be ob-ained by exposure to an ultraviolet lampwavelengthf 2537 with intensity of 12,000 W/cm2 for 15 to 20inutes. The device should be directly under and about

ne inch from the source, and all filters should be re-oved from the UV light source prior to erasure.ote that all UV erasable devices will erase with lightources having wavelengths shorter than 4000 , suchs fluorescent light and sunlight. Although the erasurerocess happens over a much longer time period, ex-osure to any light source should be prevented foraximum system reliability. Simply cover the packageindow with an opaque label or substance.

evice Programmingpon delivery, or after each erasure, the device hasll of its bits in the ONE, or HIGH state. ZEROs are

oaded into the device through the programming pro-edure.he device enters the programming mode when 12.75 0.25 V is applied to the VPP pin, OE# is at VIH andE# is at VIL.or programming, the data to be programmed is ap-lied 8 bits in parallel to the data pins.he flowchart in the Programming section of thePROM Products Data Book (Section 5, Figure 5-1)hows AMDs Flashrite algorithm. The Flashrite algo-ithm reduces programming time by using a 100 s pro-ramming pulse and by giving each address only asany pulses to reliably program the data. After each

ulse is applied to a given address, the data in that ad-ress is verified. If the data does not verify, additionalulses are given until it verifies or the maximum pulsesllowed is reached. This process is repeated while se-uencing through each address of the device. This partf the algorithm is done at VCC = 6.25 V to assure thatach EPROM bit is programmed to a sufficiently high

hreshold voltage. After the final address is completed,he entire EPROM memory is verified at VCC = VPP =.25 V.

lease refer to Section 5 of the EPROM Products Dataook for additional programming information and spec-

fications.

rogram Inhibitrogramming different data to multiple devices in par-llel is easily accomplished. Except for CE#, all like in-uts of the devices may be common. A TTL low-levelrogram pulse applied to one devices CE# input with

VPP = 12.75 V 0.25 V and OE# HIGH will programthat particular device. A high-level CE# input inhibitsthe other devices from being programmed.

Program VerifyA verification should be performed on the programmedbits to determine that they were correctly programmed.The verify should be performed with OE# at VIL, CE# atVIH, and VPP between 12.5 V and 13.0 V.

Autoselect ModeThe autoselect mode provides manufacturer and de-vice identification through identifier codes on DQ0DQ7. This mode is primarily intended for programmingequipment to automatically match a device to be pro-grammed with its corresponding programming algo-rithm. This mode is functional in the 25C 5Cambient temperature range that is required when pro-gramming the device.To activate this mode, the programming equipmentmust force VH on address line A9. Two identifier bytesmay then be sequenced from the device outputs by tog-gling address line A0 from VIL to VIH (that is, changingthe address from 00h to 01h). All other address linesmust be held at VIL during the autoselect mode.Byte 0 (A0 = VIL) represents the manufacturer code,and Byte 1 (A0 = VIH), the device identifier code. Bothcodes have odd parity, with DQ7 as the parity bit.Read ModeTo obtain data at the device outputs, Chip Enable (CE#)and Output Enable (OE#) must be driven low. CE# con-trols the power to the device and is typically used to se-lect the device. OE# enables the device to output data,independent of device selection. Addresses must bestable for at least tACCtOE. Refer to the SwitchingWaveforms section for the timing diagram.

Standby ModeThe device enters the CMOS standby mode when CE#is at VCC 0.3 V. Maximum VCC current is reduced to100 A. The device enters the TTL-standby modewhen CE# is at VIH. Maximum VCC current is reducedto 1.0 mA. When in either standby mode, the deviceplaces its outputs in a high-impedance state, indepen-dent of the OE# input.

Output OR-TieingTo accommodate multiple memory connections, atwo-line control function provides:n Low memory power dissipation, andn Assurance that output bus contention will not occur.CE# should be decoded and used as the primary de-vice-selecting function, while OE# be made a commonAm27C256 5

6ctsloo

SDti

M

N1234onnection to all devices in the array and connected tohe READ line from the system control bus. This as-ures that all deselected memory devices are in their

ow-power standby mode and that the output pins arenly active when data is desired from a particular mem-ry device.

ystem Applicationsuring the switch between active and standby condi-

ions, transient current peaks are produced on the ris-ng and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-put capacitance loading of the device. At a minimum, a0.1 F ceramic capacitor (high frequency, low inherentinductance) should be used on each device betweenVCC and VSS to minimize transient effects. In addition,to overcome the voltage drop caused by the inductiveeffects of the printed circuit board traces on EPROM ar-rays, a 4.7 F bulk electrolytic capacitor should be usedbetween VCC and VSS for each eight devices. The loca-tion of the capacitor should be close to where thepower supply is connected to the array.

ODE SELECT TABLE

otes:. VH = 12.0 V 0.5 V.. X = Either VIH or VIL.. A1A8 and A1014 = VIL. See DC Programming Characteristics for VPP voltage during programming.

Mode CE# OE# A0 A9 VPP Outputs

Read VIL VIL X X X DOUTOutput Disable X VIH X X X High Z

Standby (TTL) VIH X X X X High ZStandby (CMOS) VCC 0.3 V X X X X High ZProgram VIL X X X VPP DINProgram Verify VIL VIL X X VPP DOUTProgram Inhibit VIH VIH X X VPP High Z

Autoselect (Note 3)

Manufacturer Code VIL VIL VIL VH X 01h

Device Code VIL VIL VIH VH X 10hAm27C256

ASOAAw

VAAVN1

2

SisottmBSOLUTE MAXIMUM RATINGStorage TemperatureTP Products. . . . . . . . . . . . . . . . . . 65C to +125Cll Other Products . . . . . . . . . . . . . . 65C to +150Cmbient Temperatureith Power Applied. . . . . . . . . . . . . . 55C to +125Coltage with Respect to VSSll pins except A9, VPP, VCC . . 0.6 V to VCC + 0.6 V9 and VPP (Note 2) . . . . . . . . . . . . .0.6 V to 13.5 VCC (Note 1). . . . . . . . . . . . . . . . . . . . .0.6 V to 7.0 Votes:. Minimum DC voltage on input or I/O pins 0.5 V. During

voltage transitions, the input may overshoot VSS to 2.0 Vfor periods of up to 20 ns. Maximum DC voltage on inputand I/O pins is VCC + 5 V. During voltage transitions, inputand I/O pins may overshoot to VCC + 2.0 V for periods upto 20 ns.

. Minimum DC input voltage on A9 is 0.5 V. During voltagetransitions, A9 and VPP may overshoot VSS to 2.0 V forperiods of up to 20 ns. A9 and VPP must not exceed +13.5V at any time.

tresses above those listed under Absolute Maximum Rat-ngs may cause permanent damage to the device. This is atress rating only; functional operation of the device at theser any other conditions above those indicated in the opera-

ional sections of this specification is not implied. Exposure ofhe device to absolute maximum ratings for extended periods

ay affect device reliability.

OPERATING RANGESCommercial (C) DevicesAmbient Temperature (TA) . . . . . . . . . . .0C to +70CIndustrial (I) DevicesAmbient Temperature (TA) . . . . . . . . .40C to +85CExtended (E) DevicesAmbient Temperature (TA) . . . . . . . .55C to +125CSupply Read VoltagesVCC for 5% devices . . . . . . . . . . +4.75 V to +5.25 VVCC for 10% devices . . . . . . . . . +4.50 V to +5.50 VOperating ranges define those limits between which the func-tionality of the device is guaranteed.Am27C256 7

8D

CN123C CHARACTERISTICS over operating range (unless otherwise specified)

aution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.otes:. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP... ICC1 is tested with OE# = VIH to simulate open outputs.. Minimum DC Input Voltage is 0.5 V. During transitions, the inputs may overshoot to 2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

Figure 1. Typical Supply Current vs. FrequencyVCC = 5.5 V, T = 25C

Figure 2. Typical Supply Current vs. TemperatureVCC = 5.5 V, f = 10 MHz

Parameter Symbol Parameter Description Test Conditions Min Max Unit

VOH Output HIGH Voltage IOH = 400 A 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.45 V

VIH Input HIGH Voltage 2.0 VCC + 0.5 V

VIL Input LOW Voltage 0.5 +0.8 V

ILI Input Load Current VIN = 0 V to VCC 1.0 A

ILO Output Leakage Current VOUT = 0 V to VCCC/I Devices 1.0

AE Devices 5.0

ICC1 VCC Active Current (Note 2) CE# = VIL, f = 10 MHz, IOUT = 0 mA

25 mA

ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA

ICC3 VCC CMOS Standby Current CE# = VCC 0.3 V 100 A

IPP1 VPP Supply Current (Read) CE# = OE# = VIL, VPP = VCC 100 A

08007I-5

1 2 3 4 5 6 7 8 9 10

30

25

20

15

10

Frequency in MHz

Supp

ly Cu

rre

nt

in m

A

08007I-6

75 50 55 0 25 50 75 100 125 150

30

25

20

15

10

Temperature in C

Supp

ly Cu

rre

nt

in m

AAm27C256

TS

KEST CONDITIONS

Table 1. Test Specifications

WITCHING TEST WAVEFORM

EY TO SWITCHING WAVEFORMS

2.7 k

CL 6.2 k

5.0 V

DeviceUnderTest

08007I-7

Figure 3. Test Setup

Note:Diodes are IN3064 or equivalents.

Test Condition-45, -55 and -70

Allothers Unit

Output Load 1 TTL gate

Output Load Capacitance, CL(including jig capacitance) 30 100 pF

Input Rise and Fall Times 20 ns

Input Pulse Levels 0.03.0 0.452.4 V

Input timing measurement reference levels 1.5 0.8, 2.0 V

Output timing measurement reference levels 1.5 0.8, 2.0 V

2.4 V

0.45 VInput Output

Test Points

2.0 V 2.0 V

0.8 V0.8 V

08007I-8

3 V

0 VInput Output

1.5 V 1.5 VTest Points

Note: For CL = 100 pF.Note: For CL = 30 pF.

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Dont Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z) Am27C256 9

1A

CN1234

S

N12

P

N12C CHARACTERISTICS

aution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.otes:. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.. This parameter is sampled and not 100% tested.. Switching characteristics are over operating range, unless otherwise specified.. See Figure 3 and Table 1 for test specifications.

WITCHING WAVEFORMS

otes:. OE# may be delayed up to tACC tOE after the falling edge of the addresses without impact on tACC.. tDF is specified from OE# or CE#, whichever occurs first.

ACKAGE CAPACITANCE

otes:. This parameter is only sampled and not 100% tested.. TA = +25C, f = 1 MHz.

Parameter Symbols

Description Test Setup

Am27C256

UnitJEDEC Standard -45 -55 -70 -90 -120 -150 -200 -255

tAVQV tACC Address to Output DelayCE#, OE# = VIL

Max 45 55 70 90 120 150 200 250 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 45 55 70 90 120 150 200 250 ns

tGLQV tOEOutput Enable to Output Delay CE# = VIL Max 30 35 40 40 50 50 50 50 ns

tEHQZtGHQZ

tDF(Note 2)

Chip Enable High or Output Enable High to Output High Z, Whichever Occurs First

Max 25 25 25 25 30 30 30 30 ns

tAXQX tOHOutput Hold Time from Addresses, CE# or OE#, Whichever Occurs First

Min 0 0 0 0 0 0 0 0 ns

Addresses

CE#

OE#

Output08007I-9

Addresses Valid

High Z High Z

tCE

Valid Output

2.4

0.452.00.8

2.00.8

tACC (Note 1)

tOEtDF (Note 2)

tOH

Parameter SymbolParameter

Description Test Conditions

CDV028 PL 032 PD 028

UnitTyp Max Typ Max Typ Max

CIN Input Capacitance VIN = 0 8 12 8 12 6 10 pF

COUT Output Capacitance VOUT = 0 8 12 8 12 8 10 pF0 Am27C256

PC

*

PHYSICAL DIMENSIONS*DV02828-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

For reference only. BSC is an ANSI standard for Basic Space Centering.

D 02828-Pin Plastic Dual In-Line Package (measured in inches)

TOP VIEW

SIDE VIEW END VIEW

INDEX ANDTERMINAL NO. 1

I.D. AREA

.565

.605

1.4351.490

.005 MIN.045.065

.014

.026.100 BSC

.015

.060

.160

.220

.125

.200

BASE PLANESEATING PLANE

.300 BSC.600BSC

.008

.018

94105

.700MAX

16-000038H-3CDV028DF103-30-95 ae

DATUM DCENTER PLANE

DATUM DCENTER PLANE

1

UV Lens

Pin 1 I.D.

1.4401.480

.530

.580

.005 MIN.045.065

.090

.110

.140

.225

.120

.160.014.022

SEATING PLANE.015.060

.630

.700

010

.600

.625

16-038-SB-AGPD 028DG757-13-95 ae

28 15

14

.008

.015Am27C256 11

1PP

l

RRGCDF5

PA

T

CAFPHYSICAL DIMENSIONS L 03232-Pin Plastic Leaded Chip Carrier (measured in inches)

EVISION SUMMARY FOR AM27C256evision Ilobalhanged formatting to match current data sheets.istinctive Characteristicsast access time: Changed Speed options as fast as5 ns to Speed options as fast as 45 ns.roduct Selector Guidedded the -45 speed option.

Ordering InformationUV EPROM Products: Added the AM27C256-45 ValidCombination.Test ConditionsTable 1. Test Specifications: Added the -45 speed op-tion.

AC CharacteristicsAdded the -45 speed option.

rademarks

opyright 1998 Advanced Micro Devices, Inc. All rights reserved.MD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.lashrite is a trademark of Advanced Micro Devices, Inc.roduct names used in this publication are for identification purposes only and may be trademarks of their respective companies.

.050 REF..026.032

TOP VIEW

Pin 1 I.D.

.485

.495.447.453

.585

.595.547.553

16-038FPO-5PL 032DA796-28-94 aeSIDE VIEW

SEATINGPLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400REF.

.490

.5302 Am27C256

This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.

Am27C256Distinctive CharacteristicsGeneral DescriptionBlock DiagramProduct Selector GuideConnection DiagramsDIPPLCC

Pin DesignationsLogic SymbolOrdering InformationUV EPROM ProductsOTP EPROM Products

Functional DescriptionDevice ErasureDevice ProgrammingProgram InhibitProgram VerifyAutoselect ModeRead ModeStandby ModeOutput ORTieingSystem Applications

Mode Select TableAbsolute Maximum RatingsOperating RangesDC CharacteristicsFigure 1. Typical Supply Current vs. Frequency VCC = 5.5 V, T = 25CFigure 2. Typical Supply Current vs. Temperature VCC = 5.5 V, f = 10 MHz

Test ConditionsFigure 3. Test SetupTable 1. Test Specifications

Switching Test WaveformKey to Switching WaveformsAC CharacteristicsSwitching WaveformsPackage CapacitancePhysical DimensionsCDV02828-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)PD 02828-Pin Plastic Dual In-Line Package (measured in inches)PL 03232-Pin Plastic Leaded Chip Carrier (measured in inches)

Revision Summary for Am27C256Revision IGlobalDistinctive CharacteristicsProduct Selector GuideOrdering InformationTest ConditionsAC Characteristics