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Introduction to Computer Organization

KR ChowdharyProfessor & Head

Email: kr.chowdhary@acm.org

Department of Computer Science and EngineeringMBM Engineering College, Jodhpur

February 5, 2011

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Processor level design

memory

CPU or processor (instruction sets)Input/output Devices

networks

Information transferred is in words

CPU Address bus

databus

Address bus

databus

Control bus

Control busmemory

Interconnection networks (busses) provide dynamic connectionbetween components-handshake

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Instruction cycle

begin

fetch

execute

isinterrupt

waiting?

NO

YES

NO

YES

Serviceinterrupt

areinstructions

waitingexecutions?

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CPU Architecture

ALU

PC IR

ctrl ckts

ctrl lines

ACDR

AR

program control unit

AC f(AC,DR)

One CPU Cycle tcpu =smallest micro-operation of CPU,1/ccpu=maximum clock freq. of CPU.Execution time=no. ofcpu clock cycle tcpuOne memory cycle tm= time spent between address applied tomemory, to data released by memory.tm/tcpu 10.

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detailed instruction cycle

start

cpu activated? NO

YES

AR

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Intel 8085 Internal architecture

Stores 8-bit data (registers, accumulator)

performs arithmetic, logic, and data movement operations

Tests for conditions (if/then)Sequence the execution of instructions

Stores temporary data in RAM during execution

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Intel 8085 registers

6 general purpose registers, 8-bit, B,C, D, E, H, L, which canbe used to form 3 - 16 bit registers, BC, DE, HL.

Accumulator is 8 - bit register

Tests for conditions (if/then)

Flag bits:

Indicate the result of condition sets: C, Z, S, P,

Program counter: Contains memory address of nextinstruction, Stack register: holds the return address forsubroutine call, can save registers(PUSH, POP Instructions)

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Intel 8085 assembly language programming

Program to add two numbers:MVI A, 7BHMVI B, 67HADD BHLT

Program to multiply a number 4:MVI A, 30HRRCRRCMOV B, AHLT

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I l 808 bl l i

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Intel 8085 assembly language programming

Find greater between two numbers:

MVI B, 30HMVI C, 40HMOV A, BCMP CJZ EQU

JC GRTMVI D, 01HHLT

EQU: MVI D, 00H

HLT

GRT: MVI D, 02HHLT

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I l 8085 A hi

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Intel 8085 Architecture

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P i h l ith ROM

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Peripheral processor with ROM

CLK

RDY

AD0-AD7

A8-A10

CE

IO/MALE

RD

IOW

Reset

IOR

Prog/CEVDD

Vcc

PA0-7

PB0-7

2k X 8

EPROM

A

B

8755 2kx8 bytes EPROM with I/O

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