3 orcad si for electrical constraints determination

8/10/2019 3 OrCAD SI for Electrical Constraints Determination

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Design Flow Chart

CIS

DesignOrCAD

PSpice

ons ra n s

PCB

Designer


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Traditional Signal Integrity Flow

Design Reuse?etlistt

Constraints Update ?Design

Analyze / Edit TopologyoPCB

Co

nst

Editor

raints

Topology Extraction

opo ogy ssoc a on

o e ssoc a on


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Topic

Chan e our constraints desi n flow with OrCAD SI

Determine desi n constraints from Ca ture to OrCAD SI

Back annotate ECsets and store information in Capture Directly translate design constraints from netlist files.

Enhance the smoothness for PCB design flow


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OrCAD Schematic w/ Signal Integrity Flow

SI Model Association

na yze opo ogy

Topology Extraction

etl

ist

Topology Association

oPCB

Editor


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Determine Hi-Speed Constraints in OrCAD SI

1. Impendence control

2. Timing control


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SI Analysis in Capture

.


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Assign SI Model

Assign SI model for others

Xnet


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r gna n egr y or

-

From OrCAD Ca ture to OrCAD SI


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Impendence Control - Terminator

=

R16 = 100 Ohm


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Virtual Layer Stackup


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Virtual Via Padstack


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Edit & Assume Transmission Line


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Edit & Assume Layer Stackup forTransmission Line Via Model

-


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Define Constraints in OrCAD SigXplorer


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Update to Capture

Reusable Schematic &Constraints


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Apply Differential Pair ECSet


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Update To Capture and Netin toAllegro/OrCAD PCB


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Import ECSet From Constraint Manager


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DDRx Routing Topology

RAM Chip

RAM Chip

Controller

RAM Chip

RAM Chip

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D i R l i P i D l


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Determine Relative Propagation DelayConstraints

Build BUS Group

Create pin-pair by each net

Match Group by pin-pair

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Determine who is the target for each group

Is it possible to be much faster and easier ?

D t i R l ti P ti D l


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Determine Relative Propagation DelayConstraints from OrCAD SI

D fi R l ti P ti D l


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Define Relative Propagation DelayConstraints

A l ECS t i C t i t M


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Apply ECSets in Constraint Manager

Auto create Pin-Pair b Each Net Auto match Group by Pin-Pair

Auto assign constraints by each Pin-Pair


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*

DSN

One mouse clickmakes you ready for

From Processor =>

.

Topology Embedded in DSN file

SI Analysis

F A B


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F.A.B.

Enhance constraints design flow with OrCAD SI

r can e p us o e erm ne es gn cons ra n s It can back annotate ECSets and store information in Capture

Directly translate design constraints from netlist files

3 orcad si for electrical constraints determination

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