3. overall connection diagram and block diagram · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b...

24
PDP-502MX, PDP-502MXE 18 A B C D 1 2 3 4 1 2 3 4 INPUT ASSY (AWZ6394) PDP-502MX Only PDP-502MXE Only PDP-502MX Only VIDEO ASSY (AWZ6441: PDP-502MX) (AWZ6448: PDP-502MXE) To PDA-5001 (VIDEO BOX) YC SEPA. ASSY (AWV1776) DIGITAL VIDEO ASSY CN3402 DIGITAL VIDEO ASSY CN2301 DIGITAL VIDEO ASSY CN551 DIGITAL VIDEO ASSY CN3271 CONTROL ASSY CN5749 CABLE ASSY (3) CN1106 CABLE ASSY (4) CN1106 CABLE ASSY (5) CN1106 Y DRIVE ASSY CN3753 CABLE ASSY (8) CN1106 CABLE ASSY (7) CN1106 CABLE ASSY (6) CN1106 CABLE ASSY (2) CN1106 CABLE ASSY (1) CN1106 DIGITAL VIDEO ASSY CN3403 DIGITAL VIDEO ASSY CN3404 UCOM ASSY CN3611 CN3610 MAIN POWER ASSY CN306 CONTROL ASSY (AWZ6414) UCOM ASSY (AWZ6395: PDP-502MX) (AWZ6473: PDP-502MXE) IR RECEIVER ASSY (AWZ6399) SIDE SWITCH ASSY (AWZ6398) AUDIO ASSY (AWZ6413) 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM 3.1 OVERALL CONNECTION DIAGRAM (1/2)

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Page 1: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

18

A

B

C

D

1 2 3 4

1 2 3 4

INPUT ASSY(AWZ6394)

PDP-502MX Only

PDP-502MXE Only

PDP-502MX Only

VIDEO ASSY(AWZ6441: PDP-502MX)(AWZ6448: PDP-502MXE)

To

PD

A-5

001

(VID

EO

BO

X)

YC SEPA.ASSY(AWV1776)

DIGITAL VIDEO ASSYCN3402

DIGITAL VIDEO ASSYCN2301

DIGITAL VIDEO ASSYCN551

DIGITAL VIDEO ASSYCN3271

CONTROL ASSYCN5749

CABLE ASSY (3)CN1106

CABLE ASSY (4)CN1106

CABLE ASSY (5)CN1106

Y DRIVE ASSYCN3753

CABLE ASSY (8)CN1106

CABLE ASSY (7)CN1106

CABLE ASSY (6)CN1106

CABLE ASSY (2)CN1106

CABLE ASSY (1)CN1106

DIGITAL VIDEO ASSYCN3403

DIGITAL VIDEO ASSYCN3404

UCOM ASSYCN3611 CN3610

MAIN POWER ASSYCN306

CONTROL ASSY(AWZ6414)

UCOM ASSY(AWZ6395: PDP-502MX)(AWZ6473: PDP-502MXE)

IR RECEIVERASSY(AWZ6399)

SIDE SWITCHASSY(AWZ6398)

AUDIO ASSY(AWZ6413)

3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM3.1 OVERALL CONNECTION DIAGRAM (1/2)

Page 2: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

19

A

B

C

D

5 6 7 8

5 6 7 8

AKP1202: PDP-502MXAKP1193: PDP-502MXE

X DRIVE ASSYCN3451

CONTROL ASSYCN5747

CABLE ASSY (9)CN1106

CABLE ASSY (10)CN1106

VIDEO ASSYCN3401

DIGITAL VIDEO ASSYCN3283

RCC CONTROL (C)ASSY (AWZ6408)

MAIN POWER ASSY(AWZ6405)

OTL CONTROL (C)ASSY (AWZ6411)

SP TERMINALASSY(AWZ6415)

RCC CONTROL (A)ASSY (AWZ6406)

FAN CABLE AASSY(AWZ6403)

SENSOR A ASSY(AWZ6400)

FAN CABLE BASSY(AWZ6404)

OTL CONTROL (A)ASSY (AWZ6409)

RCC CONTROL (B)ASSY (AWZ6407)

OTL CONTROL (B)ASSY (AWZ6410)

VF DD CONVERTERASSY (AWZ6412)

Y DRIVE ASSYCN3801

Y DRIVE ASSYCN3601

Y DRIVE ASSYCN3601

X DRIVE ASSYCN3451

Note: When ordering service parts, be sure to refer to "EXPLODED VIEWS AND PARTS LIST" or "PCB PARTS LIST".

Page 3: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

20

A

B

C

D

1 2 3 4

1 2 3 4

3.2 OVERALL CONNECTION DIAGRAM (2/2)

CABLE ASSY (2)(AWV1816)

CABLE ASSY (1)(AWV1816)

CABLE ASSY (3)(AWV1816)

To PLASMA PANEL ASSY

To

PL

AS

MA

PA

NE

L A

SS

Y

To PLASMA PANEL ASSY

CABLE ASSY (8)(AWV1816)

CABLE ASSY (7)(AWV1816)

DIGITAL VIDEO ASSY(AWV1815)

CABLE ASSY (6)(AWV1816)

X DRIVE ASSY(AWV1817)

X C

AB

LE

D A

SS

Y(A

WZ

6397

)X

CA

BL

E U

AS

SY

(AW

Z63

96)

UCOM ASSYCN3929

UCOM ASSYCN3920

UCOMASSYCN3920

UCOM ASSYCN3912

UCOM ASSYCN3921

UCOM ASSYCN3606

UCOMASSYCN3915

J124ADX2669-

UCOMASSYCN3929

VIDEO ASSYCN2001

VIDEO ASSYCN3404

VIDEO ASSYCN2901 CN2902

Page 4: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

21

A

B

C

D

5 6 7 8

5 6 7 8

3)

To

PL

AS

MA

PA

NE

L A

SS

Y

CABLE ASSY (4)(AWV1816)

CABLE ASSY (5)(AWV1816)

SC

AN

MO

DU

LE

(MC

-163

43)

SC

AN

MO

DU

LE

(MC

-163

43)

SC

AN

MO

DU

LE

(MC

-163

43)

SC

AN

MO

DU

LE

(MC

-163

43)

CABLE ASSY (10)(AWV1816)

CABLE ASSY (9)(AWV1816)

Y DRIVE ASSY(AWV1818)

UCOM ASSYCN3929

UCOM ASSYCN3926

UCOM ASSYCN3926

UCOM ASSYCN3916

UCOM ASSYCN3930

UCOM ASSYCN3608

UCOM ASSYCN3607

UCOM ASSYCN3607

UCOM ASSYCN3920

UCOM ASSYCN3617

UCOMASSYCN3953

E28

UCOM ASSY CN3926

Y

Page 5: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

22

Each Flexible Flat Cable Terminal Name

Page 6: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

23

Page 7: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

24

A

B

C

D

1 2 3 4

1 2 3 4

E17

E7

E12E10

E8

E22E15

E16

E20

E1

E19 E2

E5E3

E35 E6

E21

E24

E23

EEPROMIC3601

S5V

S5V14V

E33

RST

REG

R5V

SYSTEMCONT CPU

IC3604

PWR

U-COM ASSY

E18

SustainPulse Gen.

IC3454

Vsus

SUSOUT

Psu

s(X

)

F9

Psu

s(X

)

X DRIVE ASSYTo

Pan

el X

-Ele

ctro

de

Vsus12VVfx

Vsus12VVfx

SustainPulse Gen.

IC3455

SustainPulse Gen.

IC3459

SustainPulse Gen.

IC3460

Vsus12VVfx

Vsus12VVfx

To

Pan

el X

-Ele

ctro

de

SUSOUT

F5

Vsus

F6

12VVfx

5V

+RST OUT

Psu

s(X

)

RST

SUS

5V

DRVSig.

LogicBLK

OC

PD

Isol

atio

n (P

C)

BLK

+ Reset Pulse Gen.

PD CONTRelay

AC IN

Vad

r

Vsu

s

PD

STB5V

HI PWROFF SW

STB12V

MAIN POWER ASSYP1

P4

P6

P3

P2

P5

P7

FU101

+B

STBYPWR

PWR

DELAYDELAY

VSUSSW PWR

Vsu

s10

V

VADRSW PWR

12V

8V 14V

PFC

-8V

VF D-D CONVFY, VFZVFX

OCOVC

PD

VCCSW PWR

RGBDAT

C

RG

B A

DA

T

RG

B B

DA

T,H

D,V

D

D4

D1

D19

D18

D12

D13 D14

D17

D20 D21

CLP

IPProcess

CLP PulseGen.

AsCF

CABLE ASSY CABLE ASS

AUDIO ASSYA33 A34

A19

A20

A1

A2

A3

A5 ANALOG VIDEO ASSY

5V_P5_PL

5V_R

YCSVDRPr

HDCS

GY

BPb

RGBOUT

RGBIn IN 2

IN 3IN 4

Y,

SS

RGBDecoderIC1401

WB/BRI/CON

CONTROL

ADC

In3/In4SEL

YCbCr

YPbPr

HDVD

YPbPrY

Y

RGB

RGB

RGB Int/ExtSEL

RGB

(A)

(B)

P&P

SyncSepa

G/Y

HDVD

SyncSEL

PLL

HD,VD

HD

VD

CLK

CLK

V.ROMRGB

502MXEOnly

SCL, SDA

SyncU-ComF-DET

CLP,HVBLK

CLP,HVBLK

SyncSEL

CONT

DATCLK

DAC

A17

A30 A31

-5V_IO5V_AD

5APLL5VBPLL

9V_PIC9V_SIG

REG

12V

SEL

Audio1/2

Audio3/4

LRLR

12V

CABLE ASSY

B2 B3

12V15VD-D

CON

PWR AMPIC4502

DCDET

PD

R L

12VSTB5V

LR VO

L

13V

MUTE

VOLCONT

(Main/Sub)LR

R10V

REG

14V

FANDRV

14V

FANCONTBLK

SENSSD

FANMAX

OS

D D

AT

TO SIDE SWASSY

KEY, LED

12V5V

5V

5V

Vadr Vadr

VadrVadr

Vsus

Vsus

5V

C6 C5 C4 C2

C1

R OUT AudioOut

CombiIn Out

SRIn

SROut

IRRECEIVE

ASSY TxRx

REM

LR

12V

R

S5VPD, VOL

13V,S5V

K1 K2 K1 K2 K1 K2

SDet

REM, Tx, Rx,Vol, Mute

PD

13V DAT, CLKSDet, FDet

SDASCK

RGB

CABLE ASSY

K1

K2

ADRU/B/D/G

VADR

IC IC IC IC

VADR

IC IC IC IC

VADR

DEF DEF DEF DEF

DA

T3

(64b

it)

RG

BR

GB

RG

B

RG

B

RG

B

RG

B

RG

B

RGB

CLKB CLKBCLK CLKVADRGen.

12V5V

3.3V

DA

T2

(64b

it)

DA

T1

(64b

it)

DA

T0

(64b

it)

K1

K2

ADRU/B/D/G

VADR

IC IC IC IC

VADR

IC IC IC IC

VADR

DEF DEF DEF DEF

DA

T3

(64b

it)

RG

BR

GB

RG

B

RG

B

RG

B

RG

B

RG

B

RGB

CLKB CLKBCLK CLKVADRGen.

12V5V

3.3V

DA

T2

(64b

it)

DA

T1

(64b

it)

DA

T0

(64b

it)

CA

BL

E A

SS

Y

K1

K2

ADRU/B/D/G

VADR

IC IC IC IC

VADR

IC IC IC

VADR

DEF DEF DEF DEF

DA

T3

(64b

it)

RG

BR

GB

RG

B

RG

B

RG

B

RG

B

RG

B

CLKB CLKBCLK CVADRGen.

15

3

DA

T2

(64b

it)

DA

T1

(64b

it)

DA

T0

(64b

it)

CA

BL

E A

SS

Y

3.3 BLOCK DIAGRAM3.3.1 OVERALL BLOCK DIAGRAM

Page 8: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

25

A

B

C

D

5 6 7 8

5 6 7 8

E38

E26

E27

E28

OM1

E33

DIGITAL VIDEO ASSY

RGBDAT

DRVSig

TOP ADR DAT(64bit * RGB * 20)

Sub-FieldConv.

* Field MEM

IP CPU

PanelCPU

RG

B A

DA

T

RG

B B

DA

T,H

D,V

D

XY DRVSequencepattern

Gen.

RGBDAT

D16D11

D3 D5

D7

D9

D8

D10

D6D13 D14

D17

D20 D21

CLP

5V3.3V

12V

IPProcess

CLP PulseGen.

RGBDAT

AspectConv.FIFO

Gamma-1ABL

DitherOSD Add

OSDGen

Xtal60M

Xtal50M

BOTTOM ADR DAT(64bit * RGB * 20)

VA

DR

Con

t

REG

OCUPV

PD

20

20

V/Y

ADC

YC9

V/Y

3DY/Y/SY SEL

C

C SEL

3D Y/C forNTSC 3Line Y/C

forPAL/60PAL

V/YC

NTFIL

PALFIL

3DY Y

3DC

PA

LY

SE

C Y

C C

YC6

Y SEL C SEL

SDAT

CONT

SERPARACONV.

SinY SECFIL

12V8V,5V

FILTER

REG

5V, 3V

Y/C SEPA ASSY(502MX only)

Y

CABLE ASSY CABLE ASSY CABLE ASSY

A13

ALOG VIDEO ASSY

A24

5V_PIC5_PLD

5V_RGB

OUTVBSYCSVDIN 1IN 2

In1/In2SEL

V/YC

Y, Col diff Decoder

Y,C

SyncSepa

Bder01

YCbCr

YPbPr

HDVD

PbPrY

IC1201

SyncSEL

RGB

502MX Only

SCL, SDA

A30 A31

13V, 8V, -8V

-5V_IO5V_AD

5APLL5VBPLL

CG

REG

A21

Vsus12V

SustainPulse Gen.

IC3605

Vsus12V

Vsus12V

Vsus12V

VFY

VFY

VFY

VFY

Vsus

H13

Vsus10V

VRN

VH

Vofs

Vsus

IC5V

14V

-8V

SustainPulse Gen.

IC3604

SU

S O

UT

SustainPulse Gen.

IC3609

SustainPulse Gen.

IC3610

SU

S O

UT

Vcp

-RSTOFS

VRN

- Reset Pulse Gen.

OFSPulse Gen.

Vofs

5V

Isol

atio

n(P

C)

BLK

H12

H1

H3

H2

VcpBLK

Vcp

12VS

US

SU

S

OVP

D-DCONVBLK

OC

-8V

12V

CPMSK

OFS

Vsus10V

UVPOVP

14V

PD

5VVFYVFZ

DRV Sig.

SI ,CLK

D-D CONVBLK

CP

MS

K, O

FS

To

Pan

el Y

-Ele

ctro

de

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

�����

������

Psu

s(Y

)P

sus(

Y)

Y-SUSMASKBLK

SI ,CLK

SI ,

CLK

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

VHIC5V

ADDSEL

PULSE

To

Pan

el Y

-Ele

ctro

deT

o P

anel

Y-E

lect

rode

To

Pan

el Y

-Ele

ctro

de

H4 H6

H9H11Y DRIVE ASSY

SCAN MOD

SCAN MOD

Psu

s(Y

)

RN

TOP ADR DAT

BOTTOM ADR DAT

VHIC5V

VHIC5V

VHIC5V

VHIC5V

H5

LogicBLK

H16

10V

TEMPSENS

10V

SP(L) ASSY

L OUT

TEMPSENS

IC4101

SENSOR A ASSY

SENS A

R10V

SENS

FAN DRV AASSY

FAN DRV BASSY

FAN A

FAN B

FAN C

FAN D

FANDRV A

FANDRV B

FANDRV B

R10V

REG

FANDRV

14V

FANCONTBLK

ENSSD

ANAX

Vadr

Vadr

K1 K2 K1 K2 K2K1

K1

IC IC IC IC

VADR

DEF DEF DEF

RG

B

RG

B

RG

B

RGB

CLKB CLK

12V5V

3.3V

DA

T1

(64b

it)

DA

T0

(64b

it)

CA

BL

E A

SS

YK1

K2

ADRU/B/D/G

VADR

IC IC IC IC

VADR

IC IC IC IC

VADR

DEF DEF DEF DEF

DA

T3

(64b

it)

RG

BR

GB

RG

B

RG

B

RG

B

RG

B

RG

B

RGB

CLKB CLKBCLK CLKVADRGen.

12V5V

3.3V

DA

T2

(64b

it)

DA

T1

(64b

it)

DA

T0

(64b

it)

CABLE ASSY

K1

K2

ADRU/B/D/G

VADR

IC IC IC IC

VADR

IC IC IC IC

VADR

DEF DEF DEF DEF

DA

T3

(64b

it)

RG

BR

GB

RG

B

RG

B

RG

B

RG

B

RG

B

RGB

CLKB CLKBCLK CLKVADRGen.

12V5V

3.3V

DA

T2

(64b

it)

DA

T1

(64b

it)

DA

T0

(64b

it)

Page 9: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

26

A

B

C

D

1 2 3 4

1 2 3 4

IC305

2MHz

IC1207

VIDEO SWIC306

(BA7657F)

Multi Component ProcessorRGB Matrix

IC1401(CXA2101AQ)

RGB DECODER

LPF

Y/G 2

Pb/BPr/R

FS

CH

BLK

_CN

RC

LP_C

NR

Y C SC

LS

DA

SC

LS

DA

HD/CSVD

4

6

8

10

INP

UT

3 (R

GB

1)

INPUT ASSY(AWZ6394)

To CONTROL ASSY CN4703

RG

B2

INR

GB

2 O

UT

AU

DIO

INP

UT2

(502

MX

)IN

PU

T4 (5

02M

XE

)

AU

DIO

INP

UT1

(502

MX

)IN

PU

T3 (5

02M

XE

)

INP

UT

1IN

PU

T2

CN35062

1

410 6 1 56951

27

45

1

2

4

5

11

1213

3 R

R

L

R

LL14

15

1

2

4

5

11

12

14

15

42

Y

C

3

5

5

7976 75

4

3

11

10

9

7

55 56 31 43

8

EXT_Y

INT_Cr

INT_Cb

INT_Y

EXT_Pb

EXT_Pr

EXT_HD

EXT_VD

SC

L

SD

A

SC

P P_ACL

24

12

4

6

8

10

CN303

3 5 6 7 9CN203 11 12

7

G

7

4

4

7

1

10

HO

UT

SD

A

SC

L

SY

NC

B

R

HD

VD

9

11

23

13

G1

S_DET

S2_DET

B1

R1

HD1

VD1

G2

B2

21

9

12

5

6

3

2

37

36

35

Y

B–Y

Y SYNC

Y

RGB SYNC

R–Y

710

1

5

3

19

15

22

14

R2

HD2

VD2

R

G

B

IC1204(BA7655AF)

IC506

IC303

Comp

12V

Reg

IC301

Comp

S2_DET

S_DET

IC503

Comp

IC501

Comp

IC1205(NJN1319M)

Comp

Comp

IC507(24LCS21A)

5V_RGB

SCL

VCLK

SDA

HD

VD

Plug & PlayROM

+5V_RGB

9V_PIC

R

15

12

10

G

B HD

VD

2

5

7

12V

9V Reg

9V_S

IG

9V Reg

9V_P

IC

5V Reg

5V_R

GB

5V Reg

5V_P

IC

5V Reg

5V_P

LD

5V Reg

+5A

_PLL

+5D

_PLL

5V Reg

+5A

D

–5V

Reg

–5V

_IO

IC1202(TC74HC4538AF)

HBLK Gen.

Y/B–Y/R–Y DECODER SYNC SEPA.TV JUNGLE IC

IC1201(TB1227BW)

SCP Gen.

SHP_SWMAI_SW

FN

C_0

FNC_1

FNC_2 MR_V_SW

1 3

CN302A5

1 2 5 6 7 11CN3401

80

37

39

35

5V_PIC9V_SIG

IC651

IC102

5V_PIC

K1404

SAND CASTLE PULSE GEN.HBLK/VBLK/CLP added

K2013HBLK

K2023HD3

K2024VD3

K2025HD4

K2026VD4

K2014VBLK

4

3

INPUT

OUTPUT

Y

C

SINC

SINY

13

3 YC_VY

YC_C

1 3 CN104A24 A21

SC

LS

DA

13.5

V8V

1 2 3 5

CN304

INT

_Cr

INT

_YIN

T_C

bH

D_P

LD

VD

_PLD

L R

A31

1 3 5 7 9

CN503

11 13

A30C2

To Y/C SEPA ASSY CN701 YC9

To Y/C SEPA ASSY CN702

PDP-502MX OnlyPDP-502MXE OnlyYC6

To POWER SUPPLY ASSY CN306 P6

A13

3.3.2 VIDEO ASSY SECTION

Page 10: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

27

A

B

C

D

5 6 7 8

5 6 7 8

3

4

5

6

CN2203

2

3

4

5

6

CN2202

R–Y LEVEL

B–Y LEVEL

VD_PLD

HD_PLD

Peak ACL

1

3

5

7

9

11

R

G

B

IN Screen K2904(VD)

K2903(HD)

K2901(CLK)

AD OUT IP Process

NTSC 4:3 60 15.734k 40.28M Single (A) IP

PAL Wide 50 15.625k 53.63M Single (A) IP

PCXGA (60) ORG 60 48.36k 32.50M Dual (A/B) Through

G1

B1

R2

G2

B2

21

19

15

3

8

13

18

R

G

B

35

30

P_ACL_SW

CLP

_AM

P

Picture Control

EN

T/E

XT

_SW

25

CN2901

IC104

5 6

5V_PIC

Video DataROM

(24LC01B)

IC140412

1314

SEL_Vout V_STATE

G-Out

B-Out

R-Out

12

2

9

24

11

10

151415142

S_DET

97421

VD_FIL

HD_FIL

VD

_MA

SK

HD

_MA

SK

3

19

4HD/VD

NOISE GATEPULSE Gen.

IC2004(TC74VHC123AFT)

MMVMMV

HBLK_MAT/VBLK_MAT/CLP_MAT

HD3/VD3/HD4/VD4

5V_PIC 2

11

6

VRB

CLK

CLK_AD

CLK_AD

RST

VRT

IN 43

8R (B)

R (A)

G (B)

G (A)

B (B)

B (A)

8

2 2

+5AD

+5AD

SD

A

SC

L

A/DIC2401

(CXA3256R)

RG

B A

mp.

IC17

01(M

5233

7SP

)

INT/EXTRGB SWIC1702

(BA7657F)

Reg.

K2404

K240512V

K2419

K2401

K2402

K2403

8

88 9

2

11

6

VRB

CLK

RST

VRT

IN

8

8

2 2

+5AD

A/DIC2402

(CXA3256R)

K2406

K2407

K2901K2903K2904

K20

29

K20

30

K2031

K2015CLP

K27

15

VD_PLDK2032

HD_PLDK2033

G/YK2004

CLP_AMPK2004

K2716

VD_DSEL

HD

_DS

EL

K27

06K

2707

K22

03

K22

04K

2201

K22

02

K2210

K2704VCO VD1

K2211

K2711

K2710

K2209

K2212K2213

CLP1CLP2HBLKVBLK

K27

08K

2709

K27

13

3

2

11

6

CN2902VRB

CLK

DATA

CLK

DAC_CE

RST

VRT

IN

8

8

2

3

2

1

2

+5AD

A/DIC2403

(CXA3256R)

D/AIC1704

(M6235FP)

HD_PLLIC2701

(CXA3106Q)

Sync. U-COMIC2201

(PD2060A9)

Sync. Sepa for Y/GIC2002

(M52346SP)

Sync. ControlSync. Select

PLDIC2005

(PE9006A)

D/AIC2301

(CXA1875AM)

D/AIC2302

(CXA1875AM)

K2408

K2409

5V_PLD

12V

+5A_PLL

5V_PIC

+5D_PLL

5V_PIC

5V_PLD

K2021K2020

4

150

148

146

6

4

8

2

SDA

S2_DET

SCL

SD

A

SC

L

11

12

18

FN

C_1

FN

C_0

SH

P_S

W

MA

T_S

W

FN

C_2

MR

_V_S

W

94

5V_PIC

INT

/EX

T_S

W

P_A

CL_

SW

19

31

16

152

28

154

10

2

4

2 22,23

4

4

4

11

21 HD_PLL

23 HOLD_PLL

ULK_PLL

HD_u, VD_u

PLL_CE

DATA

CLK

CLK

DA_0_SV

35 37 396

3

4

HD

_SE

P

VD

_SE

P

8

8

8

8

8

8

2

Reset

Input Freq. Det.

Gate

To

DIG

ITA

L V

IDE

O A

SS

Y

C

N34

03D

20T

o D

IGIT

AL

VID

EO

AS

SY

CN

3404

D21

To

U-C

OM

AS

SY

CN

3612

E24

To

U-C

OM

AS

SY

CN

2202

E23

A33

A34

A2

A1

8

9

10

11

CN2001

To

DIG

ITA

L V

IDE

O A

SS

Y

C

N34

02D

17

A3

Video: Dual OutputPC: Single Output

Page 11: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

28

A

B

C

D

1 2 3 4

1 2 3 4

SYNC SEPA ICIC2002

(M52346S)

SYNC_SEPA

CONTROLLOGIC

CLP_SEPA

HSTATE

HPOLVSTATE

VPOL

CLAMP/BLANKING

PULSECONTROL

SYNC CONTROL PLDIC2005(PE9006A)

MASK_DSW

CLP_SW1,2

HD_PLD

HD_3HD_4

VD_4VD_3

VD_PLD

IC2004(2/2)TC74VHC123

IC2004(2/2)TC74VHC123

CLP_AMPCLP_MAT

HBLK_MATVBLK_MAT

NoiseMaskGate

VD_FIL

VD_MASK

HD_FIL

HD_MASK

NoiseMaskGate

K2033

K2025K2023

K2032

K2026K2024

K2004

K2021

K2020

K2012K2015K2013K2014

13pin

8pin6pin

14pin HD_+

HD_SEP

VD_SEP

HD_–

VD_+

15pin

17pin

4pin

19pin18pin1 pin2pin

Input from IC1201 (Jungle-IC)

in Comp/S input (Positive polarity)

Separate HD/CS, VD SYNC signal input from BNC/D-sub 15p

Y/G ON SYNC signal in inputting Y color-difference or RGB signals

Clamp & Blanking pulse output to Analog Video block

Control signal for switching mask width (Lo : In PC input)

Noise cancel processing Limit to U-com processing velocity (Max: 200Hz)

HD/VD SYNC signal selected by input functionfor generating Mask pulse(except for when selecting HD_PLD, VD_PLD)

Noise cancel processing Countermeasure for copy guard

Limit to U-com processing velocity (Max: 200kHz)

SYNC signal output separated from Y/G ON SYNC signal

Selected HD/VD signal used for Separate input SYNC signal detection

Information on detecting Separate input SYNC signal & the polarity

CLP_SEP (Switching Clamp pulse width

Clamp pulse generated by SYNC Separate IC (Used in PC input)

SYNC signal selected based on input function & HD/VD signal detected (Unify the polarity to negative polarity)

Signal selector for

SYNC signal &

Circuit for switching polarity

Decoding HD/VD signal

detected

Selecting input SYNC signal

Setting value of HOLD Pulse width

20 bit / Parallel

data

3.3.3 SYNC SIGNAL PROCESSING BLOCK

Page 12: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

29

A

B

C

D

5 6 7 8

5 6 7 8

Signal Frequency DETU-COMIC2201

( PD2060A )

PLL ICIC2701

(CXA3106Q)

HD_U

VD_U

HD_PLL

DIGITAL VIDEO ASSY

CLP1CLP2

HBLK1VBLK2

ULK_PLL

Serial Control sigPLD_CEDATACLK

VD_DSEL

SER-->PARACONV

HOLD_PLL

DIVOUT

U-COM ASSY

V_STD

Serial dataREQ_Su

HOLD_Su

PLL input HD

HD FreqCounter

LineNumberCounter

SYNC STATE

K2030

K2019

K2029

K2018

K2031

K2715

K2702

K2027

HD_DSEL

ADCIC2401IC2402IC2403

( CXA3256R )

ADCK+

ADCK-

RST-

RST+

CLK_ADK2716

K2419

H_COUNT(0:10)

LINE(0:10)

HOLD signal generation circuit for

PLL control

Inverted PLL unlock information (Lo: When PLL is not locked)

Clamp & Blanking signal output from Digital Assy

PLL output HD for A/D sampling &clock SYNC reference

HOLD controlling signal for comparing PLL phase comparison.

PLL unlock information (Hi: When PLL is not locked)

Vertical line number count value (11-bit data) Data is updated every 1 V sync.

Signal for detecting abnormal SYNC signal (Hi: in detecting)

Count value in the period of 1H by 16MHz clock (11-bit data) Data is updated at the rate of HD1/8 dividing

Timing signal for capturing horizontal frequency count value (HD 1/8 dividing)

Vertical SYNC signal for input signal detection

Signal for detecting vertical frequency limitLo: Vertical frequency value is higher than standard value (In PC input : fixed Hi)

VD SYNC signal sent to Digital Assy

*Input signal detection (stability) *No signal input detection *Detecting vertical frequency *Controlling V_STD (detecting frequency value)

Sampling clock for A/D (differential output)

Reset signal for A/D (differential output)

Sending*Data of vertical frequency*Data of horizontal frequency *Data of total numbers of lines*Information on inapplicable frequency

K2709

K2707

K2706

K2708

Page 13: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

30

A

B

C

D

1 2 3 4

1 2 3 4

3.3.4 DIGITAL VIDEO ASSY SECTION

27

R (A)

G (A)

B (A) R (A)/G (A)/B (A)

VD_102

DE_102FLD_102

HD_102

RA_102RB_102

8bit × 28bit × 2

GA_102GB_102

BA_102BB_102

R (B)/G (B)/B (B)

OSD_DATA1

OSD_CLK1

OSD_CE1

OSD_CLR1

SDATA1

SCLK1

PN_MUTEY

PN_MUTEX

PBUSY0

PERR0

IPBUSY0

IPERR0RMT0RESET_RET

D_CLK1D_DATA1

PN_RST1

28

29

30

IC1801(PE5067A)

Sync CONTCLAMP PULSE

GEN.

RGB≠

YPbPr

SharpnessArrange

IC2001IP U-com.

(IC#101)

(IC#102) (IC#20)

IC1901(PE5066A)

IP PROCESSOR

I/FIP

ProcessX SpeedX dencity

IC1951(UPD4811650GF-A10)

16M SGRAM

+3.3V

CLK_101

IC2101(PE5061A)

IC2260(PDY061A)

OSDPROCESSOR

+3.3V 62M

+3.3V

205

+3.3V

+5V

67

67

ULK_PLL

+3.3V

Y (8bit)Pb (8bit)Pr (8bit)

Y (8bit)Pb (8bit)Pr (8bit)

Y (16bit)Pb (16bit)Pr (16bit)

+3.3V

IC1952(UPD4811650GF-A10)

16M SGRAM

+3.3V

8

TP3413

TP

3411

TP

3410

TP

3412

TP

3414

FLD_IP

DE_IP

VD_IPHD_IP

CLK_102

CLK_101

8

8

5

7

R (B)

G (B)

B (B)

8

8

8

CN3404D21

CN3403

5

IC2151(PE5062A)

IC22(PE50

DRIVE SEPATTER

8

5

9

10

11

12

CN3402D17

CN3273

D13

D20

TP

3408

TP

3409

TP

3407

TP

3406

TP

3405

VBLK1

V_STD

HBLK1

CLP2

CLP1

TP

2102

TP

2103

IC2301

PANEL U-com.

S2301RST

TP2303

D2306

D2302

R (IP BUSY)

G (IP ERR)RG(P ERR)

RS

T

+5V

X200120M

X230120M +5V

5

4

6

7

8

9

CN3271

D14

2

1

4

5

6

7

8

9

10

11

12

RAI/RBI

WRITE CLK (SYSTEM CLK)

GAI/GBI

BAI/BBI

HVFLDVLD

CLKOSD_HOSD_V

RGBBLK

RGB

6

5

63

IC2251(PD5538B)

OSD ICSer=Para

IC2255(MBM29F200BC-70PFTN-K)

FLASH ROM

+5V

IC2256(LC3564BM)

64k SRAM

To

U-C

OM

AS

SY

C

N36

08E

5F

rom

U-C

OM

AS

SY

C

N36

06E

6T

o V

IDE

O A

SS

Y

CN

2001

A3

To

VID

EO

AS

SY

C

N29

02A

34T

o V

IDE

O A

SS

Y

CN

2901

A33

26

25

TP

3415

+5V+5V

OS

D M

IX

AB

L

γ –1

Dith

er

YPbPr≠

RGB

ASPECTRATIOCONV.

W

R

SyncProcess

SC

MASK CONT

FIFO

R (P BUSY)

G (STOP B)

+

Page 14: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

31

A

B

C

D

5 6 7 8

5 6 7 8

16bit × 2(IC#21)

260061A)

SDESSOR

205

+3.3V

IC2151(PE5062A)

IC2201(PE5064A)

DRIVE SEQUENCEPATTERN GEN.

IC2601(PE5063A)SUB FIELD

CONVERSIONR

ADRBUFFER

IC2901–IC2910IC3001–IC3010IC3301–IC3304IC3308, IC3309IC3311, IC3312

IC2701(PE5063A)SUB FIELD

CONVERSIONG

R

WDATA

ARRANGE

DATACONVERT

CONT

(IC#22)

IC2801(PE5063A)SUB FIELD

CONVERSIONB

Q605IC601

Q554IC551

IC2602(HY58163210TQ-10)

16M SGRAM

IC2603(HY58163210TQ-10)

16M SGRAM

IC2702(HY58163210TQ-10)

16M SGRAM

IC2703(HY58163210TQ-10)

16M SGRAM

IC2802(HY58163210TQ-10)

16M SGRAM

IC2803(HY58163210TQ-10)

16M SGRAM

+3.3V

R

W

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

40

40

40

RDAT

GDAT

BDAT

+3.3V

CN3252

CN3256

D9

D4

TP

2154

TP

2155

EM CLK)

VACANT

To Panel U-com

VLD_AVLD_BFIELD

RA/RB

GA/GB

BA/BB

H

V

LKSD_HSD_V

RGBBLK

3

6

8CD

50M

25M

3

IC3101

X DRIVE BUFFER

XSUS-B/U/D/GXPR, XR

IC3102–IC3104

Y DRIVE BUFFER

X320250MHzOSC

SGRAM • READ OUT MASTER CLOCK

X320162MHzOSC

1/2

To

X D

RIV

E A

SS

Y

CN

3402

F9

To

Y D

RIV

E A

SS

Y

CN

3751

H1

To

AD

DR

ES

S M

OD

UL

E

+5V

+3.3V

CN551D16

825 ADR/LBLK

MN (X Drive Gen. Pulse)EF/GH/IJ (Y Drive Gen. Pulse)24

TP601

TP553

D555

Digital P.D.

D605

Q551Q552

TP555+5V OVP

TP604+3.3V OVP

REG

REG

AB

L

γ –1

Dith

er

LUT

DATAARRANGE

DATACONVERT

CONT

SYNCCONT

K CONT

(IC#22)

R

WDATA

ARRANGE

DATACONVERT

CONT

(IC#22)

(IC#23)

YSUS-B/U/D/GSI, MSK, CLK, PFS, OE, YNR, YR

D6

+

+

+12V

D556

Q553

TP556+5V UVP

Q601Q602

D606

TP603+3.3V UVP

Q603

Page 15: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

32

A

B

C

D

1 2 3 4

1 2 3 4

1 3 7 9 11 12

1 3 5 6 7 9 11 12

VC

_YV

3D_Y

in

3D_C

in

CN

701

CN

702

5VR

EG

.

LPF

(6.7

MH

z)

LPF

(6.7

MH

z)

LPF

(6.

7MH

z)

IC70

1

Low

Lum

.C

NR

Cla

mp

Del

ay

250n

S

3.58

BP

FD

/AIC

703

(CX

A18

75A

M)

SC

L

SD

A 54

4.43

BP

F2

13

45

67

9

12

152 3 5 13 12

11 12 14 2 13

144115

13

4 14

13 1514

2 1 4 3 5

IC10

06

IC10

05

IC10

08

IC10

09

IC90

4

(PS

T62

3XW

)

Sin

_C

3L_V

in

IC10

03(U

PC

659A

GS

)

SCL

SDA

IC70

2IC

704

NT

SC

NT

SC

PA

L

PA

L

SE

CA

M

SE

CA

M_C

SIN

C

SECAM

3.3V

RE

G.

RE

SE

TIC

VID

EO

A/D

IC10

01(U

PD

6408

1BG

F-3

BA

-K)

IC90

1(C

XD

2064

Q)

HY

5142

64B

JC-5

0A

IC10

07

LPF

(6.

7MH

z)

4M D

RA

M

SE

CA

MC

hrom

a T

rap

5VR

EG

.

YC

_C 12V

12V

1 476 96 57

59

843D

_Y

3D_C

18 5

483

60

84

CS

I

CLP

O

AD

INA

YO

AC

O

9 7

8 5

1 21 4

37

2325

1726

FIN

MN

BPFSW

VSTRP1TRP2

VSBWNPMN

TRP0TRP1

TRP0TRP1

TRP2DLSW10

BPFSW

DLSWTRP2

TR

P2

VS/BW

NP

AC

I

RS

TB

6

IC90

3IC

902

1 4

8 5

5V_P

IC

5V_P

IC

5V_S

IG5V

_3D

5V_3

D

5V_3

D

AY

O

AC

O

5V_3

L

5V_3

L

3.3V

_3D

3.3V

_3D

5V_P

IC

5V_S

IG

8V

TR

P2

FS

C

HB

LK_C

NR

CLP

_CN

R

Y C SC

L

SD

A

8V

3D Y

/C

3Lin

e Y

/C

MA (0:8)

3DY

A (

0:9)

MD (0:15)

To VIDEO Assy CN104, CN3403

To VIDEO Assy CN202, CN203

3L_Y

3D_C

NTSC_CPAL_C

3.3.

5 Y

C S

EP

A. A

SS

Y S

EC

TIO

N (

PD

P-5

02M

X O

nly)

Page 16: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

33

A

B

C

D

1 2 3 4

1 2 3 4

XS

US

-BR

3401

R3473

IC34

02

IC34

02

+ 5

VR

EG

.

R34

05

IC34

01(T

C74

AC

11F

)

IC34

51(M

611-

TLB

)IC

3461

IC34

65

IC34

62

IC34

63

IC34

52(M

611-

TLB

)

IC34

53(M

611-

TLB

)

PD

P P

uls

e M

od

ule

IC34

54(S

TK

795-

120B

)

SU

ST

AIN

BL

OC

K

+RE

SE

T B

LO

CK

LO

GIC

BL

OC

K

IC34

56

D3451

IC34

57

IC34

58

IC34

03(T

C74

AC

08F

)

IC34

01

R34

85

R34

64

R34

70

+5V

Q34

53

Q34

51

D34

57

K34

56P

.D. (

X.C

.P)

C34

60

Q34

54

IC34

66(T

ND

301S

)

11

XS

US

-VX

SU

S-D

XS

US

-GX

PR

-U

9 7

1 3 5

5

6 638

51

4O

I

G

OI

G

OI

G

3 9 2 1 5 44 11 10

SU

S-B

1 1312

SUS-DK3406

SUS-GK3408 SUS-U

K3407

SUS-BK3403

PR-UK3404

22 4

7 5

6+

12V

75 3

+5V

+5V

VS

US

(175

V)

1

+12

VV

FX

+V

FX

–X

PD

3 6 7 9

VS

US

(175

V)

1

SU

SG

ND

2 3 4

51

51

4 44

1

+5V

RE

G.

PD

DE

T.

12V

O. C

DE

T.

+5V

RE

G.

SU

S-U

181175 14 214

917

5V175V

0V

VS

US

(175

V)

P-S

US

(X

)

SU

SG

ND

SU

SG

ND

SU

SG

ND

To

PA

NE

L

16V

SU

S/2

VS

US

SU

SO

UT

SUSG

ND

SU

S-D

VD

D2

VD

D1

VS

S2

23S

US

-G

PD

P P

uls

e M

od

ule

IC34

55(S

TK

795-

120B

)

SU

S-B

SU

S-U

181175 14 214

9VS

US

(175

V)

SU

SG

ND

16V

SU

S/2

VS

US

SU

SO

UT

SU

S-D

VD

D2

VD

D1

VS

S2

23S

US

-G

PD

P P

uls

e M

od

ule

IC34

59(S

TK

795-

120B

)

SU

S-B

SU

S-U

181175 14 214

9VS

US

(175

V)

SU

SG

ND

SU

SG

ND

16V

SU

S/2

VS

US

SU

SO

UT

SUSG

ND

SU

S-D

VD

D2

VD

D1

VS

S2

23S

US

-G

PD

P P

uls

e M

od

ule

IC34

60(S

TK

795-

120B

)

SU

S-B

SU

S-U

181175 14 214

9VS

US

(175

V) SU

SG

ND

RP

-U

16V

SU

S/2

VS

US

SU

SO

UT

SUSG

ND

SU

S-D

VD

D2

VD

D1

VS

S2

VS

US

23S

US

-G

SU

S-G

SU

S-U

SU

S-B

SU

S-D

175V 0V

175V 0V

175V 0V

R3471R3490

D3456

D3451

t

tX

-PS

US

SU

SG

ND

VS

US

RP

-UF

6

F5

F9

D4 From DIGITAL VIDEO Assy E17 From U-COM AssyE16 From U-COM Assy

SUSG

ND

3.3.

6 X

DR

IVE

AS

SY

SE

CT

ION

Page 17: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

34

A

B

C

D

1 2 3 4

1 2 3 4

IC3757

IC3752(2/2)

R3760

R3761

IC3753 (2/2)

11121356

38

1

9

10

28

26

24

22

20

36

34

38

40

42

44

32

30

18

16

14

4

46

43

30

60

31

1

43

30

60

31

1

43

30

60

31

1

43

30

60

31

1

41

10

SUS GND

D763

D710

D709

D759

D852

14V

–8V

D3751

D853

D702

Q752

Q755

D813

D809

Q802

Q805

Q3751

Q701

H9

SC

AN

MO

D 4

SC

AN

MO

D 3

SC

AN

MO

D 2

SC

AN

MO

D 1

H1

Fro

m D

IGIT

AL

VID

EO

AS

SY

H8 H7 H6

YNR-D

MUTE

OFSYSUS-MSKYCP-MSKSUS-GSUS-DSUS-USUS-B

PLD

& M

UT

E

YSUS-BHBLKLBLKCLR

YNR-DYSUS-GYSUS-DYSUS-U

YNR-U

MUTEYYSUSPD

+5V+12VVFY+VFY–VYZ+VYZ–

DRV PDDC PD

+14V

VSUSSUS GND

VSUS+10V

–8V

OFSYCP-MSK

YSUS-MSK

LECLK

SIOE

1911

12131817161514

1118121716151413

11

5

7

1213141516

76985432

987654

R3755

R3752

R3756

R3781

+5V

IC3753 (1/2)(TC74VHC541)

IC3751(TC74ACT541)

IC3755(PDT043A)

3

2

IC3660

5

SCAN BLOCK

OFS BLOCK

–R

DC–DC CONVERT BLOCK

SU

S-U

SU

S-B

K36

12K851

K855

S701ON

S701: ON OFF= Noise at high temp.

PSUS

TEMP COMPENSATION

K701

K753+

+

OEK3760

SIK3764

CLKK3765

LEK3766

CLRK3767

IC3752 (1/2)(TC74VHC541)

12348

IC3654

5

IC3655

5

IC3656

5

IC3657

5SI DATA

PSUSIC5V

IC3658

5

IC3659

VH DC–DCCONV.

IC755, IC752T751

K854IC5V OVP

K754VH OVP

K751VH UVP

K706VOFS OVP

K705VOFS UVP

K804VRN OVP

K801VRN UVP

VOFSK702

OFSK3756

IC5VDC–DC CONV.IC852, IC853

T851

VOFSDC–DC CONV.IC701, IC704

T701

VRNDC–DC CONV.IC802, IC803

T801

5

IC3752

SUSGND

SUSGND

SUSGND

VSUS

VSUS

VSUS

SUSGND

D753

IC5V

VHVSUS175V

D803

K802VRN

(–180V)

K803

+

+

+ 5VREG.

IC3803

IC3801

IC3804

55

7

Q3802R3822R3823

R3824R3825

R3826VOFS

VFZ+

VRN

R3820

Q3804

YSUS STOPPD

VH

H12

Fro

m U

CO

M A

SS

YH

13F

rom

UC

OM

AS

SY

IC5V

“ L ” for 1 sec = PD

3.3.7 Y DRIVE ASSY SECTION

Page 18: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

35

A

B

C

D

5 6 7 8

5 6 7 8

To SCAN MODULE Copper Plate

D3608

D3701IC3702

IC3704

IC3703

IC3706

IC3705

IC3701

IC3707

R3701YSUS-MSKR3730

R3728

D3705 D3704

Q3601

Q3605Q3604

R3634

R3614

R3618

R36

36

+ 5VREG.

IC3601(M611-TLB) IC3611

IC3615

IC3612

IC3613

IC3602(M611-TLB)

IC3603(M611-TLB)

PDP Pulse ModuleIC3604

(STK795-120B)

SUSTAIN BLOCK

IC3606

D36

01R

3635

D36

06

IC3607

IC3608

R3623

5 1

4O I

G

O I

G

O I

G

SUS-B

SU

S-D

K36

03

5 1

5 1

4

4

4

1

+5VREG.

+5VREG.

SUS-U

18

11

75

14

21

4 9 175V0V

VSUS(175V) K3703

SUS-OUT

SUSGND

SUSGND

16VSUS/2

VSUS

SUSOUT

SUSGND

SUS-D

VDD2

VDD1

VSS2

23SUS-G

PDP Pulse ModuleIC3605

(STK795-120B)

SUS-B

SUS-U

18

11

75

14

21

4 9

VSUS(175V)

SUSGND

16VSUS/2

VSUS

SUSOUT

SUS-D

VDD2

VDD1

VSS2

23SUS-G

PDP Pulse ModuleIC3609

(STK795-120B)

SUS-B

SUS-U

18

11

75

14

21

4 9

VSUS(175V)

SUSGND

SUSGND

16VSUS/2

VSUS

SUSOUT

SUSGND

SUS-D

VDD2

VDD1

VSS2

23SUS-G

PDP Pulse ModuleIC3610

(STK795-120B)

SUS-B

SUS-U

18

11

75

14

21

4 9

VSUS(175V)

SUSGND

16VSUS/2

VSUS

SUSOUT

SUSGND

SUS-D

VDD2

VDD1

VSS2

23SUS-G

175V0V

175V0V

175V0V

5

SUSGND

VCP BLOCK

–RESET BLOCK

SUSTAIN MASK BLOCK

SU

S-G

K36

04

SU

S-U

K36

11

SU

S-B

K36

12

K3758YSUS-MSK

K3701PSUS

K3606VCP

VC

P

SUSGND

+5V ForLogic Block

R36

15PDDET.

7

5

R3732R3736

R3731R3735

IC37082

4

+ 5VREG.

O

G

I

D3703R3717

Q3802

26

Q3804

Q3708R3710

Q3707

Q3709

Q3703

R3707R3729

R3708R3709

R3722R3723

R3724R3725

R3703R3724

R3705R3706

R3718R3719

R3720R3721

Q37

10Q

3704

Q3705

5

7

7

5

7

5

7

5

Q3711

Q37

12Q

3706

K3770YCP-MSK

K3607

K3704

D37

09

D37

08

+5V

Q3702D3702

PDDET.

RESETO. C DET.

+12VO. C DET.

PSUS

Page 19: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

36

A

B

C

D

1 2 3 4

1 2 3 4

3.3.8 UCOM ASSY SECTION

Hi

Lo

E2PROM24LC01B

64k E2PROM24LC64

RESETMATRIX ICTC7W08FU

Y SIGNALDETECTCIRCUIT

S2 DETECTCIRCUIT

RGB AMP ICM52337SP

FULL AUTOZOOM IC

HG62G010R29FB

AUDIOCIRCUIT

AUDIO PRE-AMPIC

SMOOTHINGCIRCUIT

RS-232CDRIVER/RECEIVER

MC145407F

RS-232CCONTROLLERTC74HC00AF

MEDIARECEIVER

KEY SCAN uCOM.PD5136

LEDDRIVE/CONTROL

CIRCUIT

M.R. (C.B.)CONNECTION

DETECT CIRCUIT

REMOTE CONTROLSIGNAL

CONTROL CIRCUIT

REMOTE CONTROLRECEIVER CIRCUIT

FAN CONTROLBLOCK

Y DRIVEPLD

X DRIVEPLD

23

SCLSDA

∗OSD_CLR

∗DAC_CE

∗PLD_CE

∗PLL_CE

∗RST2

HOLD_SU∗SU_CE

∗PN_CE

∗POWER

∗RST

SC_DT(ULK_PLL)

CLK2DATA2

D_CLKD_DATA

25

26

4091569

4357

16

4142

53433

78

51

31

52

56

54

64

53

63

80

23

68

22

67

20

213214

10

596062

7

44

1

4

47

61

35

1217

13 (E) SDA

∗PN_RST

∗PN_MUTEY

∗PN_MUTEX

FAN_MAX

(E) SCLEP_RST

S_DTEMP2TEMP

Y_DETI

S2_DET

V_MUTE

DATA2

VOL 0–5V DC

RXD RXDRXD/CB OUT

TXD

REM

REMSW

MR_KEY (SYSTEM)

REM_MPREM_PM

(SYSTEM)

REM

REM(MONITOR)

MR_KEY

PM_ST

KEY (MONITOR)

RTSCTS

CLK2∗ZOOM_CE

∗A_MUTE1∗A_MUTE2A_MUTE3

∗CB_MUTE

∗GRN∗RED∗YLW

∗KEY

48

747576

858

373839

PN BUSYPN ERR

RMT

IP BUSYIP ERR

RESET_RET

RESET_SU

V_STDDTO_SUREQ_SU

PLK_ID

POWER

∗OSD_CE

OSD_H

Jungle ICTB1227BN

MATRIX ICCXA2101

AN

AL

OG

VID

EO

AS

SY

AN

AL

OG

VID

EO

AS

SY

AU

DIO

AS

SY

UC

OM

AS

SY

UC

OM

AS

SY

AN

AL

OG

VID

EO

AS

SY

AN

AL

OG

VID

EO

AS

SY

DIG

ITA

L V

IDE

O A

SS

YD

IGIT

AL

VID

EO

AS

SY

YC SEPA.ASSY

UCOMASSY

UCOM ASSY

UCOMASSY

UCOMASSY

CONTROLASSY

IRRECEIVERASSY

UCOMASSY

Y DRIVEASSY

X DRIVEASSY

DIGITALVIDEOASSY

UCOMASSY

CCD/TELTEXTTPU3050

EXPANDERCXA1875AM

3D Y/C SEPA.LSI

uPD64081B

OSD ICM35070 (35071)

SYSTEMCONTROL

u-COM.(M38869)

OSD ICPD0264AM-TFB

(PDP-505HD Only)

PICTURE CONT.DAC

M62358

PLDPE9006B

PLLCXA3106A

PANEL u-COMHD64F3067

IP u-COMHD64F3067

SYNC u-COMHD64F3067

POWER SUPPLYASSY

STB 5VRESET ICPST9146N

RESET ICPST9146N

RESET ICPST9146N

SERIALCLK/DATA

CONTROLLERTC74VHC02FT-TBB

PD5531: PDP-502MX PD5549:PDP-502MXEPD5561: PDP-505HD

Page 20: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

39

A

B

C

D

1 2 3 4

1 2 3 4

3.3.

9 F

AN

CO

NT

RO

L S

EC

TIO

N

TE

MP

SE

NS

IC41

01

R

EG

VIN

Vo

Vad

IC39

52P

Q20

VZ

IUF

AN

AX

M10

36

+ –

IC39

54

SE

NS

A

3

10V

RE

G1

1

E27

LM50

CIM

3-T

LB

SE

NS

OR

A A

SS

YA

WZ

6400

K39

52S

EN

S A

21

23

R41

51D

3952

IC39

53

Fro

m P

ower

Sup

ply

assy

0.7V

DC

GE

NE

FA

N M

AX

CO

NT

Q39

59

Q39

60

R

EG

VIN

Vo

Vad

IC39

56P

Q20

VZ

IU

+–

+ –

1 1 44

33

7+

14V

P1

E2

R39

71

+10

VR

EG

IC39

51P

Q20

VZ

IU

13

4.5V

DC

FA

N M

INV

OL

GE

NE

10V

RE

G

61

Q39

66

IC36

04S

YS

TE

MC

ON

T U

-CO

M

Q3962

D3953

Q3957

Q3951

Q3952

Q3953

Q3954D3951

+14V_FAN1

Q3958

FA

N M

AX

Shu

tDow

n

TE

MP

SE

NS

76

D39

59

57

6

IC39

54

K39

54S

DU

CO

M A

SS

YA

WZ

6395

(P

DP

-502

MX

)A

WZ

6473

(P

DP

-502

MX

E)

EN

V.

TE

MP

MIN

30.0

43.0

45.0

50 (

S.D

)

IC39

54P

in1

Out

4.45

V5.

22V

5.55

V6.

46V

FA

ND

RV

TP

6.04

V6.

08V

13.2

8V16

.58V

ST

OP

MIN

30de

gC

45de

gC(M

AX

)

FA

N S

PE

ED

S.D

= C

autio

n di

spla

y fo

r 30

sec

.

6.5V

DC

S.D

DE

T

K39

51F

AN

DR

V

FA

NA

XM

1036

FA

NA

XM

1036

FA

NA

XM

1036

Page 21: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

40

A

B

C

D

1 2 3 4

1 2 3 4

FU1011

2

D113

+

D112

D115

R12

1D

117

R12

2

D116

R167R131R132

R133R134R168

Q132

D15

1

D132RY101 L133

D131

1

4

1

3

2

In rush R

Q136Q131

D15

0

+B AdjVR131

R140R166

IC131PowerFactor

Correction

1

3

8

6

7

5Q134

R15

4R

155

D13

8

4

D111

ATK1133

T111

STBY TRANS

IC1123

4

1

2

IC113 R113

VR111+5V Adj

SW111AC100V (PDP-502MX)AC200V (PDP-502MXE)

D118

Q111

4

3

52 IC111

SWIC

3

R12

3

TP112

Q401

D401

Q402

D40

2

TP111STB+5V

STB +12V

D458D459

AC200VPD

D45

7

OVP

P.ON:Lo

RY131

POWER Down Detection Block

D433Audio

Digital PD

D441X DRV

PD

D439Y DCDC

PD

D437Y DRV

PD

D407Main PWR

PD

+B OVP

1 3

ST

B+

5V PO

WE

R

To U-COM

ASSY

P1

D44

8

VF OVP PD

R48

7

D408

+

UVP PD

R41

5

P4

11 7 13 12

P2 P3

D44

7

D44

6

D44

5

D40

6

To U-COM

ASSY

POWER

D413

D41

4

Q408Q40

7

D41

2

Q406

STB +12V

UVPMUTEat P.ON

R42

4D405

PFC STOP PD

IC401

Q42

5R

410

P.O

FF

:Hi

P.O

N:L

o

AEK1071

14V

14V

D463R406

SW103ON /OFF

Q437

Q439

DRV&

UVP MUTE

R426 PFC STOPDET

R156

ErrorAMP

Comp

R36

4R

385

54RCC CONT

1

7

1

2ErrorAMP

Comp

R31

6R

347

2

3

54

3

RCC CONT

1

7

Trig (-V)

+

ErrorAMP

Comp

2

54

1

3

R23

2

R253

D188Q183

D183

D189

Q186

D186

D191

D190

Q185

D185

R19

0

R189

C20

2

R18

5R

184

DRVON/OFF

VADR VSUSSEQUENCE

Lo V VADRSEQUENCE

Q201 SW Tr(2SK2847)

Q301 SW Tr(2SK2847)

SW Tr(2SK2847)

RCC CONT

POWER FACTOR CONTROL

D46

1

STBYPOWER

IC18

1

R16

5R

139

R312

R363

Q351Q352

Mute

AC OFF DET

TP131+B (380V)

+B

+B

+B

3.3.10 MAIN POWER ASSY SECTION

Page 22: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

41

A

B

C

D

5 6 7 8

5 6 7 8

VADROVP

VADROVP

T202ATK1128

IC2013

4

2

1

+

One ShotIC204

SUSGND IC

202

R208

D202

D206R

206

VR201VSUS

AdjOTL CONT(A) ASSY

R21

0

Q202

T301ATK1129

+

One ShotIC304

ADRGND

IC302

D302

R30

6R

348

VR301VADR

AdjOTL CONT(B) ASSY

Q302

R315

D305Vadr up

R46

3

6

5

7

IC405

R46

2R

461

IC403

Q416

Q304 Q416

D427VADRUVP

VSUSUVP

D42

1

R26

8

T351ATK1130

IC3513

4

2

1

+

One ShotIC354

R35

6

OTL CONT(C) ASSY

Q354

IC352

Q422

Q435

D35

6

14V

8V

-8V

12V

60V

170V

D35

2

D373

R358

R360 R357VR356

14V Adj

Q421

Q420

R44

5

R358

8V UVP

D44

9

D451

D45

3

D432

R49

1R

490

R44

7

R45

1

R443

D434

D42

9

IC402

14V

D35514V up

12V

-8V UVP

14VUVP 14V OVP

Q415

R43

6R

437

D42

2

Q417

R44

0R

441

D42

8

IC404

12VUVP

Q419

R44

4R

493

D43

1

10V

1 3 5

1 3 5

1 3 5

D205VSUS

UP

1

SUSGND

ADRGND

P5

T201ATK1128

14V UP

R228 R227 R226 R262 R263 R264 D213 D212

VSUS+10V

DisChargeQ207, Q206

Q205,

VSUS Discharging R

P6

2

4

6

7

8

D.GND

-8V

8V

14V

11

7

6

5

2

1

1

6

D.GND

12V

P4

A.GND

12

8

7

5

3

2

1

9

10

1

2

4

5

P2 P312V

D.GND

-8V

14V

8V

UVPOVP

14V

-8V

14V

SG

S D

SW IC

IC5031

3

8

5

4 CONT

T501

IC502

IC501

1 3

D506

R507

R506

VR501VF Adj

VFZ+(12V)VFZ-

VFY+(12V)VFY-

VFZ+(12V)VFZ-

VF DC/DC CONV

+

D413

D41

4

Q408Q40

7

STB +12V

UVPMUTEat P.ON

R42

4

1

2

1

2

ErrorAMP

Comp

R36

4R

385

2

3

54

3

CC CONT

1

7

Trig

(-V

)

1

2

mp

2

3

54

3

Trig (-V)

IC3013

4

2

1

ErrorAMP

2

54

1

3

VADR TRANS

VSUS TRANS

VSUS TRANS

Q201 SW Tr(2SK2847)

SW Tr(2SK2847)

Q351

UVP MUTEQ212Q213

Mute

UVP

TP201VSUS(170V)

TP301VADR(60V)

TP351-8V

TP352+8V

TP355+14V

TP353+12V

2

CN363

CN363

14V

To

UC

OM

AS

SY

To

UC

OM

AS

SY

To

UC

OM

AS

SY

To

AN

AL

OG

VID

EO

AS

SY

Page 23: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

62

A

B

C

D

1 2 3 4

1 2 3 4

Protection Circuits

X DRIVE ASSY

MAIN POWER ASSY

AUDIO ASSY

DIGITAL VIDEO ASSY

UCOM ASSY

+12V OCP

AUDIO P.D.

+3.3V OVP +3.3V UVP +5V OVP +5V UVP

VSUS OVPVSUS UVPVADROVP

VADR UVP

VF OVP +8V UVP

AC200V P.D.+B OVP

–8V UVP +14VUVP

+14VOVP

+12V UVP

Page 24: 3. OVERALL CONNECTION DIAGRAM AND BLOCK DIAGRAM · 2010. 4. 22. · 5v_r r vd s c y pr hd cs g y b pb rgb out rgb in in 2 in 4 in 3 y, s s rgb decoder ic1401 wb/bri/ con control adc

PDP-502MX, PDP-502MXE

63

A

B

C

D

5 6 7 8

5 6 7 8

Y DRIVE ASSY

VRN UVP

VRN OVP

VH UVP

VH OVP

IC5V OVP

DRIVE STOP P.D.

12V OCP

RESETOCP

Y DC/DC BLOCK Y DRIVE BLOCK

VOFS OVP

VOFS UVP