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Combinational & Sequential Logic

ENGG1203 2nd Semester, 2017/18

Dr. Hayden So

Department of Electrical and

Electronic Engineering

http://www.eee.hku.hk/~engg1203

Outlinen  Simplifying logic circuits

•  Minimization by Boolean algebra •  Minimization by Karnaugh maps

n  Adders, muxes and other

n  Sequential circuits •  Output depends on both the current input and the

state of the circuit •  Output of combinational circuit depends only on

the current input •  Flip-Flops

2 2nd semester, 2017/18 ENGG1203 - H. So

LOGIC MINIMIZATION

2nd semester, 2017/18 ENGG1203 - H. So 3

3 Representations of Logic Functionsn  Only truth table representation is unique n  Boolean expression and schematics can be

rearranged to suit actual engineering requirement


Truth Table

Schematics Boolean Expression

Why rearrange logic circuits?n  In digital systems:

•  é no. of logic gates è é area è é power consumption

•  é no. of logic gates usually increases delay of circuit è slower circuit

n  Logic minimization helps to make logic circuits smaller, faster and lower power consumption


Two ways to simplify logic circuits:


Boolean Algebra K-Map

Minimization by Algebran  Make use of relationships and theorems of

Boolean algebra to simplify the expressions •  this method relies on your algebraic skill

n  E.g. Simplify


ABC + AB ⋅ (AC)

= ABC + AB ⋅ (A+C) [cancel double inverions]

= ABC + ABA+ ABC [multiply out]

= ABC + AB ⋅ (A+C) [by DeMorgan thm]

= ABC + AB + ABC [A ⋅ A= A]

= AC(B+ B)+ AB

= AC + AB [B+ B =1]

Karnaugh Map (K-map)n  A graphical tool to facilitate logic minimization n  Derive simplest SOP expression by

systematically looping “1”s in the K-map


A B C Y

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

ABC + ABC + ABC + ABC

BC

00 01 11 10

A0

1

1

0

Gray Code

0 1 1

0 0 1

Looping in K-Mapn  To simplify logic express, make “loops” around all 1s n  Rules:

•  Loops consist of rectangle blocks of adjacent 1s •  Size of a loop must be power of 2: 1, 2, 4, 8, 16, … •  Use minimum number of loops (use loops as big as

possible) •  Loops may overlap •  NOTE: Edges of K-map wrap around


BC

00 01 11 10

A0 0 1 1 1

1 0 0 0 1


Write out simplified expressionn  The simplified logic expression is a sum of the

expression for each loop n  The expression for each loop is the product of

the common terms


BC

00 01 11 10

A0 0 1 1 1

1 0 0 0 1


AC BC+Simplified Expression

K-map with 4 inputsn  K-map can be extended to 4 or more inputs n  4-input K-map is similar to 3-input K-map except

both axes represent 2 variables each •  5 or more input rarely used as they require drawing

map in 3D, 4D, or higher


CD

00 01 11 10

AB00

01

11

10

Example: 4-input K-map


A B C D Y

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0 0

0 1 0 1 1

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

CD

00 01 11 10

AB00

01

11

10

1

1

0 1 1 1

0 0 1

1 1 1

0 1 1 0

2nd semester, 2017/18

More examples on looping of two

ENGG1203 - H. So 13 2nd semester, 2017/18

Looping group of four (quads)

ENGG1203 - H. So 14

n  A K map may contain a group of four 1s that are adjacent to each other. This group is called quad

n  Looping a quad of adjacent 1s eliminates the two variables that appear in both complemented and uncomplemented form

n  Examples:


Looping group of eight (Octets) n  A group of eight 1s that are adjacent to one another is called an octet n  Looping an octet of adjacent 1s eliminates the three variables that

appear in both complemented and uncomplemented form

n  Examples:

ENGG1203 - H. So 15

How K-map Works?n  Gray code encoding in K-map ensures that only 1

variable differs between every two adjacent cells n  The loops help to extract common terms in Boolean

expression n  Result is in simplest canonical SOP form


BC

00 01 11 10

A0 0 1 1 0

1 0 0 0 0

ABC ABC+ = AC(B +B)= AC

More examples


BC

00 01 11 10

A0 0 1 1 0

1 0 0 1 0

ABC ABC+ = ABC + ABC + ABC + ABC= AC(B+B)+BC(A + A)= AC +BC

ABC+


n  Examples: AB\CD 00 01 11 10

00 0 1 0 0

01 0 1 0 0

11 1 1 1 1

10 0 1 0 0

AB\CD 00 01 11 10

00 0 0 0 0

01 1 0 0 1

11 1 0 1 1

10 0 0 0 0

AB CD+ BD ABC+

ENGG1203 - H. So 18


Filling out a Karnaugh Map n  Given an initial (unsimplified) logic Boolean expression n  Write the expression in SOP form

n  For each product term, write a 1 in all the squares which are included in the term, 0 elsewhere •  All variables present in the product term: one square •  One variable missing: two adjacent squares •  Two terms missing: 4 adjacent squares

n  Example 1:

n  Example 2:

n  Example 3:

A\BC 00 01 11 10

0 0 0 1 0

1 0 1 1 1

X ABC ABC ABC ABC= + + +

X BC ABC AC= + +

A\BC 00 01 11 10

0 1 0 0 0

1 1 1 1 1

X B ABC A= + +

A\BC 00 01 11 10

0 1 1 0 1

1 1 1 1 1

ENGG1203 - H. So 19

Don’t Care Conditions n  In certain cases, some of the input conditions may never occur or it

may not matter what happens even if they do •  In such cases we fill in the K map with an X

•  meaning don't care •  When minimizing an X is like a "joker"

•  X can be 0 or 1 - whatever helps best with the minimization •  E.g.,: will never occur or we “don’t care” what is the output

even if it occur •  simplifies to B if X is assumed 1 •  If we assume X = 0, the output becomes AB+BC, which is more

complicated

A\BC 00 01 11 10

0 0 0 1 X

1 0 0 1 1

ABC



AB\CD 00 01 11 10

00 0 0 0 1

01 0 1 1 0

11 0 1 1 0

10 0 0 X X

AB\CD 00 01 11 10

00 0 1 0 0

01 0 1 1 1

11 1 1 X 0

10 0 0 X 0

ENGG1203 - H. So

BCD BD+

BCD BD+

ABCD BD+

ABCD BD+

1

2

3

4

ABC ACD ABC+ +

ABC ACD ACD ABC+ + +

ABC ACD ACD ABC+ + +

ABC ACD ABC BD+ + +

1

2

3

4

21

Quick Quiz

MULTI-BIT ADDER

Putting It Together


Binary Numbersn  Represents numbers in base 2 n  E.g.: 2310 = 101112

n  Almost all computers today utilize binary representation of numbers internally


Decimal Binary

0 0

1 1

2 10

3 11

4 100

5 101

6 110

7 111

8 1000

9 1001

10 1010

11 1011

12 1100

From Binary to Decimaln  Note that the value of a binary number is

given by: where bi is the digital at position i, starting counting from zero from the far right.

n  Converting from binary to decimal can be done by adding the power-of-2 where there is a 1


€

2ibii= 0

∞

∑

Examplen  Convert the binary number 11001 into

decimal representation


202122232425

10011

€

=1× 24 +1× 23 + 0 × 22 + 0 × 21 +1× 20

= 24 + 23 + 20

=16 + 8 +1= 25

Similar to Decimal


100101102103104105

80032 = 2×104 +3×103 + 0×102 + 0×101 +8×100

= 20000+3000+8= 23008

From Decimal to Binaryn  Can be found using “short

division”: •  Successively divide the

dividend by 2 •  The remainders form the

resulting binary number when counted from the bottom

n  Example: Converts 1910 into binary


192

9

1

2 1

42 0

22 0

1

è 1910 = 100112

Positive Integersn  Non-negative binary numbers

(0, 1, 2, 3, …) can be represented naturally with bitstrings that corresponds to their binary representation

n  Represents equally spaced integers on the number line

n  Sometimes called unsigned integer


Value Binary Bitstring (8-bit)

0 0 00000000

1 1 00000001

2 10 00000010

3 11 00000011

4 100 00000100

5 101 00000101

6 110 00000110

7 111 00000111

8 1000 00001000

9 1001 00001001

10 1010 00001010

11 1011 00001011

∞0 1 2 3 4 5 6 7 8

Positive Integersn  With a bitstring of width n, the following

properties hold:

n  The value of a bistring can be calculated as:

n  E.g. The value of


€

min value : 0max value : 2n −1

€

bn−1bn−2b0{ }

€

2ibii= 0

n−1

∑

€

101112 = 24 + 22 + 21 + 20

=16 + 4 + 2 +1= 23

Positive Integers Additionn  Two +ve integers can be added similar to the

way decimal numbers are added in “long addition”


2 31 9+

21

41+

1 11011 1001

1 00101

1 1 1

How do we implement binary addition in hardware?

Half Addern  Basic addition of two 1-bit values n  Generate a carry out to the next bit if the

result is 2


1+

1 11011 1001

1 00101

1 1 1

a b co s

0 0

0 1

1 0

1 1

0

1

1

0

0

0

0

1

s = a⊕ bco = a ⋅b

ci a b co s

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0

1 0 1

1 1 0

1 1 1

Full Addern  The subsequent bits need to be slightly

smarter than a half adder •  There may be carry input from the bit to the right

n  A 3-input function (a, b, ci)

ENGG1203 - H. So 32

1+

1 11011 1001

1 00101

1 1 1

1

0

0

1

0

1

1

1

s = a⊕ b⊕ cico = a ⋅b+ ci a+ b( )


Multi-bit Addern  Both HA and FA can add 1 bit only

•  A half-adder is simply a full-adder with the carry input tied to ‘0’

n  To make a multi-bit adder, we can connect the carry output from one FA to the carry input of another one

n  Start from least significant bit (usually rightmost bit) and propagate the carry to the left (the most significant bit)

n  Mimic the action of a “long addition”


1+

1 11011 1001

1 00101

1 1 1

Multi-bit Adder

n  Note: the <> notation is a shorthand to denote a bit within a multi-bit signal. •  Other common notation: a(0), a[0], a0, etc

n  Engineer sometimes call multi-bit signal a bus, or a signal bus.


FA

a b

cico

s

a<0> b<0>

s<0>

FA

a b

cico

s

a<1> b<1>

s<1>

FA

a b

cico

s

a<2> b<2>

s<2>

FA

a b

cico

s

a<3> b<3>

s<3>

‘0’Carry out

Bus Notation

n  A bus is a bundle of wire signals that work independently n  Most often used to denote a signal with more than 1 bit

•  e.g. a 32-bit value has 32 wires n  For a 32 bit signal X, we use this notation:

•  X[31:0] or X n  To refer to a particular bit of the bus, we use these notations:

•  X[2:0] (3 bits starting from position 2 down to 0) •  X[4] •  X4

n  As a convention, we always denote the leftmost, aka most significant bit (MSB) with the largest index in a bus. The rightmost, aka least significant bit (LSB) always has index 0 •  e.g. x[3:0] denotes a 4 bit signals with the following position in an actual

number:


1 1 0 1x3 x2 x1 x0

x[3:0] = 11012 = 13

Bus Notation Example


a[3]a[2]a[1]a[0]

b[3]b[2]b[1]b[0]

s[3]s[2]s[1]s[0]

cin

cout

a[3:0]

b[3:0]

s[3:0]

cin

cout

Multiplexer (Mux)

n  A mux passes one of its N inputs to the output according to the value of its sel input


2-to-1 mux

outA

B

sel

0

1

ifsel==0{out=A}else{out=B}

4-to-1 mux

outA

sel[1:0]

0

1BCD

2

3

ifsel==0{out=A}elseifsel==1{out=B}elseifsel==2{out=C}elseifsel==3{out=D}

Implementing a 2-to-1 Muxn  One way to implement a mux is to treat it as a

simple combinational logic: •  determine its truth table •  implement the truth table using logic gates

n  Example, a 2-to-1 mux


sel a b out0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

0

1

1

out = sel •a+ sel •b

0

1

0

1

Short Summaryn  Truth Table, Schematics and Boolean Expression

are 3 different ways to represent the same functionality •  Conversion between the 3 is relatively straight-forward •  TT is the only representation that is unique

n  Logic circuits can be minimized/manipulated by Boolean algebra •  May use TTs for proofs as they are unique •  K map is a handy graphical ways to obtain minimized

logic functions

n  Combinational techniques allow us to build large circuits •  Multi-bit Adder from single-bit HA and FA

2nd semester, 2017/18 ENGG1203 - H. So 39 2nd semester, 2017/18 ENGG1203 - H. So 40

Combinational vs Sequential

n  In combinational logic, the output is a pure function of the present input only, i.e. no memory effect

n  In sequential logic, the output depends not only on the present input, but also on the history of the input, i.e. memory effect


CombinationalSequential

Sequential Logicn  Sequential logic circuits are circuits that

contains state elements n  State elements are circuits that remember its

input •  Allow a circuit to have memory of its past

n  All state elements of a circuit collectively store the current state of the circuit

n  The output of the circuit depends on both •  Current Input •  State (memory) of circuit


Why Sequential Circuit?

n  Provide order to the operation of the circuit •  E.g. part of a circuit must not start computing until the

inputs are ready

n  Coordinate different parts of circuit to operate on the correct set of data •  E.g. A circuit that computes the final grade should take

input (homework, exam grades, etc) of the same student

n  Recall previous values •  E.g. Echo cancellation by subtracting previous output

sound wave 1 ms ago from input signals

43

Introduces the notion of time in the circuit

2nd semester, 2017/18 ENGG1203 - H. So

State Elementsn  A state element (circuit component) stores a

‘1’ or ‘0’ permanently regardless of the changes in input

n  Simple example (but not quite useful): •  If x is 0, then y is 1, then x is 0, … •  If x is 1, then y is 0, then x is 1, … •  The value stored inside the circuit will not change

44

x y

To be useful: Need a way to change the state


Flip-Flopsn  An edge-trigger flip-flop (FF) is a circuit that

changes it output only when the value of it’s clock input changes •  0 è 1 = Rising Edge •  1 è 0 = Falling Edge

n  Ignore input when clock is not changing n  For simplicity, we will only use rising edge

triggered FF in this class n  An edge-triggering signal pin is usually

denoted by a wedge in the schematic symbol.

45

clk


D

Q

clk1

D Flip-Flop

n  A D-FF has 1 data input port D, and a single output port Q, plus •  Clock input •  Optional: reset (clear) input •  Optional: enable

n  At the rising edge of clock signal, the value at input D is captured.

n  Captured data is output at Q after a small delay •  In this class, it is denoted:

46

clkD Q

time


Timing Diagram

Ignore all input between clock edges

Schematic Symbol

Tclk→Q

one signal per row

Ex – Delay Line/Shift Register

n  One simple (but useful) way to use DFFs is to form a delay line.

n  A delay line with n DFFs delays the input signal by n clock cycles

n  Note: In hardware designs, all parts of the circuit operate in parallel •  Since the same clk is connected to both DFFs, both of them

operate synchronously

47

clkD Q

clkD Qa

bc

clk


a

b

c

clk1

Quick Quiz

n  Which of the following best describes the function of the circuit above? •  y always output the inverse of x •  y always output value of x from previous cycle •  y outputs ‘1’ when x changes its value from

previous cycle •  y outputs ‘1’ when x stays ‘0’ for 2 cycles

48

clkD Qx

y

clk

1

2

3

4


x

x’

y

clk1

Timing

49

clkD Qx

y

clk

x’

x’ is a delayed version of x

time


x

x’

y

clk1

Timing

50

clkD Qx

y

clk

x’

combinational (regardless of clk)

y = x⊕ "x

time


x

x’

y

clk1

Timing

51

clkD Qx

y

clk

x’

time


if x was 1 in last clock cycle, but now is 0, then y becomes 1

if x was 0 in last clock cycle, but now is 1, then y becomes 0

Quick Quiz Explained

n  The value at x’ contains the value of x from previous cycle

n  = TRUE iff exactly one of the two is TRUE •  x=0, x’=1 •  x=1, x’=0

n  y is TRUE if the value of x changes from its value in previous cycle

n  Note the DFF has given us memory of x from previous cycle

52

clkD Q

xy

clk

x’

y = x⊕ "x


T

Q

clk1

Example – Implement Toggle FF with DFFn  A toggle flip-flop (T-flip-flop) toggles the

output at rising clock edge when the toggle signal (T) is HIGH. •  Otherwise, the output remains unchanged.

53

clkT Q

Can we use a DFF to implement a TFF?


Ex: Implementing TFF with DFFn  Step 0: Define a signal nextQ

•  nextQ denotes the value that should be output at Q after the next clock edge

n  Step 1: Express nextQ as a function of input T and Q •  “Given the current output Q is __ and the input at T is __, then

the next value of Q after the clock edge should be __” •  nextQ is a combinational function on T,Q. Use a truth table to

list out its behavior

54

T Q nextQ

0 0

0 1

1 0

1 1

0

1

1

0

Current cycle

Next cycle

T

nextQQ


T

Q

clk1

Ex: Implement TFF using DFFn  Step 2: Use a DFF to implement the function of

“storing nextQ into Q after the next clock edge”

55

T

nextQ

clkD Q Q

clk

Q


T

Q

nextQ

clk1

Registern  A register is a parallel

composition of D-flip-flops. •  An n-bit register contains n

DFFs

n  A register stores multi-bit values

56

clkD Q

clkD Q

clk

clkD Q

clkD Q

d3

d2

d1

d0

q3

q2

q1

q0clk clk


d q d q

Accumulatorn  An accumulator accumulates the input values (x)

into the internally stored sum on every clock edge.

NOTE n  Instead of simple ‘0’ and ‘1’, the value in the

signal X and S are used n  The initial value of S must be reset to the value

zero for correct behavior

57

X x0 x1 x2

sum 0 x0 x0 + x1 x0 + x1 + x2

clk

1


Accumulator

n  It can be constructed using an adder with a register: •  Step 1: the next value of sum after the clock edge

should be the sum of input x and the current_sum •  Step 2: At clock edge, we store the value of next_sum

using a register •  Step 3: the newly stored value becomes the

current_sum after the clock edge

58

A

BS

x clk

sum

clk

current_sum next_sum


Synchronous vs Asynchronous Sequential Circuit

n  In synchronous sequential circuits, all state elements are updated synchronously according to a single clock signal

n  In asynchronous sequential circuits, state elements may be updated with multiple clocks, no clock signal, or any other schemes.

59

Combinational

synchronous

asynchronous

Sequential

This Course


Synchronous Sequential Circuitsn  A synchronous sequential circuit contains exactly 1

clock signal n  All state elements are connected to the same clock

signal •  è the state of the entire circuit is updated at the same time

n  Common form of synchronous sequential circuits:

60

clk

Comb Logic

clk

input

clk

Comb Logic

clk

Comb Logic

Comb Logic

output


Clock Signaln  A clock signal is particularly important signal in a

synchronous sequential circuit •  It controls the action of all DFFs

n  A clock signal toggles between ‘0’ and ‘1’ periodically

n  The frequency of the toggling determines the maximum speed of the circuit •  E.g.: in the accumulator example earlier, the output S

cannot change faster than the clock frequency

61

X x0 x1 x2

S 0 x0 x0 + x1 x0 + x1 + x2

clk

1

clock period

1clock period

= clock frequency

e.g. Intel CPU runs at 3 GHz, Mobile phone processors at 1 GHz Lab FPGA board at 50 MHz


Timing of Circuitsn  So far, we have assumed:

•  output of a combinational circuit changes instantaneous w.r.t. input

•  Output of a FF changes instantaneously w.r.t. clock edge

n  In reality, it takes finite amount of time for a signal to travel through a circuit.

n  The timing of different parts of a circuit •  may cause glitches in output, •  limit the maximum speed of a design


Propagation Delay

n  Each logic gate incurs delay between the input and output to allow signal to propagate •  Usually referred as propagation delay or gate delay

n  Exact value is technology-dependent n  In this class, we assume all gates have the same

unit propagation delay. •  The speed of a circuit is always limited by the slowest

path

63

a

b

c

d y

•  3 units of delay from a to y

•  1 unit of delay from d to y

• Worst case delay = 3 units


Timing in Synchronous Circuits

n  In a synchronous sequential circuit, signal changes occur only during clock edge

n  All signals are therefore synchronized to change values right after a clock edge

n  In the above example, need to make sure correct value of y available BEFORE next clock edge •  Avoid glitches

64

a

b

c

dy

clk clk

clk


Timing in Synchronous Circuitsn  In general, the propagation

delay through the combinational logic between any two registers must be shorter than the clock period

n  The longest such path is called the critical path of the circuit

n  The critical path determines the maximum clock speed

65

clk

clk clk

Comb Logic

a

b

x

y

clk

1

Stable before clock edge


Synchronous Circuits Timing

n  Since only values right before the clock edge in the input ports are captured •  All changes between clock edges are ignored

n  A short period of time before a clock edge must be allocated to ensure stable inputs •  Too small è Chance of failing circuit •  Too big è Wasted idle time

n  Since all circuit runs on the same clock, clock frequency limited by the longest critical path



Where are these materials being used in our everyday lives?

Google – TPUn  Tensor Processing Unit n  A dedicated hardware

accelerator to accelerate machine learning applications

n  High performance, Low Power n  Deployed in global datacenters


Summaryn  Simplifying logic circuits

•  Minimization by Boolean algebra •  Minimization by Karnaugh maps •  Adders

n  In sequential circuits, output depends on both the current input and the state of the circuit •  Output of combinational circuit depends only on the

current input

n  D-Flip-Flops are the most common state element to hold states in a circuit •  The output value of and edge-triggered DFF only

changes at positive clock edge. •  A multi-bit DFF is sometimes referred as a register


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